arch/arm/mach-s3c24xx/mach-bast.c

   1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
   2  *
   3  * Copyright 2003-2008 Simtec Electronics
   4  *   Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://www.simtec.co.uk/products/EB2410ITX/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/gpio.h>
  20 #include <linux/syscore_ops.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dm9000.h>
  24 #include <linux/ata_platform.h>
  25 #include <linux/i2c.h>
  26 #include <linux/io.h>
  27
  28 #include <net/ax88796.h>
  29
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33
  34 #include <mach/bast-map.h>
  35 #include <mach/bast-irq.h>
  36 #include <mach/bast-cpld.h>
  37
  38 #include <mach/hardware.h>
  39 #include <asm/irq.h>
  40 #include <asm/mach-types.h>
  41
  42 //#include <asm/debug-ll.h>
  43 #include <plat/regs-serial.h>
  44 #include <mach/regs-gpio.h>
  45 #include <mach/regs-mem.h>
  46 #include <mach/regs-lcd.h>
  47
  48 #include <linux/platform_data/hwmon-s3c.h>
  49 #include <linux/platform_data/mtd-nand-s3c2410.h>
  50 #include <linux/platform_data/i2c-s3c2410.h>
  51 #include <mach/fb.h>
  52
  53 #include <linux/mtd/mtd.h>
  54 #include <linux/mtd/nand.h>
  55 #include <linux/mtd/nand_ecc.h>
  56 #include <linux/mtd/partitions.h>
  57
  58 #include <linux/serial_8250.h>
  59
  60 #include <plat/clock.h>
  61 #include <plat/devs.h>
  62 #include <plat/cpu.h>
  63 #include <plat/cpu-freq.h>
  64 #include <plat/gpio-cfg.h>
  65 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
  66
  67 #include "simtec.h"
  68 #include "common.h"
  69
  70 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
  71
  72 /* macros for virtual address mods for the io space entries */
  73 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  74 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  75 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  76 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  77
  78 /* macros to modify the physical addresses for io space */
  79
  80 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  81 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  82 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  83 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  84
  85 static struct map_desc bast_iodesc[] __initdata = {
  86   /* ISA IO areas */
  87   {
  88           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  89           .pfn          = PA_CS2(BAST_PA_ISAIO),
  90           .length       = SZ_16M,
  91           .type         = MT_DEVICE,
  92   }, {
  93           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  94           .pfn          = PA_CS3(BAST_PA_ISAIO),
  95           .length       = SZ_16M,
  96           .type         = MT_DEVICE,
  97   },
  98   /* bast CPLD control registers, and external interrupt controls */
  99   {
 100           .virtual      = (u32)BAST_VA_CTRL1,
 101           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
 102           .length       = SZ_1M,
 103           .type         = MT_DEVICE,
 104   }, {
 105           .virtual      = (u32)BAST_VA_CTRL2,
 106           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
 107           .length       = SZ_1M,
 108           .type         = MT_DEVICE,
 109   }, {
 110           .virtual      = (u32)BAST_VA_CTRL3,
 111           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
 112           .length       = SZ_1M,
 113           .type         = MT_DEVICE,
 114   }, {
 115           .virtual      = (u32)BAST_VA_CTRL4,
 116           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
 117           .length       = SZ_1M,
 118           .type         = MT_DEVICE,
 119   },
 120   /* PC104 IRQ mux */
 121   {
 122           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
 123           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
 124           .length       = SZ_1M,
 125           .type         = MT_DEVICE,
 126   }, {
 127           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
 128           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
 129           .length       = SZ_1M,
 130           .type         = MT_DEVICE,
 131   }, {
 132           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
 133           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
 134           .length       = SZ_1M,
 135           .type         = MT_DEVICE,
 136   },
 137
 138   /* peripheral space... one for each of fast/slow/byte/16bit */
 139   /* note, ide is only decoded in word space, even though some registers
 140    * are only 8bit */
 141
 142   /* slow, byte */
 143   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 144   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 145   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 146
 147   /* slow, word */
 148   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 149   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 150   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 151
 152   /* fast, byte */
 153   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 154   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 155   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 156
 157   /* fast, word */
 158   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 159   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 160   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 161 };
 162
 163 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 164 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 165 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 166
 167 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 168         [0] = {
 169                 .hwport      = 0,
 170                 .flags       = 0,
 171                 .ucon        = UCON,
 172                 .ulcon       = ULCON,
 173                 .ufcon       = UFCON,
 174         },
 175         [1] = {
 176                 .hwport      = 1,
 177                 .flags       = 0,
 178                 .ucon        = UCON,
 179                 .ulcon       = ULCON,
 180                 .ufcon       = UFCON,
 181         },
 182         /* port 2 is not actually used */
 183         [2] = {
 184                 .hwport      = 2,
 185                 .flags       = 0,
 186                 .ucon        = UCON,
 187                 .ulcon       = ULCON,
 188                 .ufcon       = UFCON,
 189         }
 190 };
 191
 192 /* NAND Flash on BAST board */
 193
 194 #ifdef CONFIG_PM
 195 static int bast_pm_suspend(void)
 196 {
 197         /* ensure that an nRESET is not generated on resume. */
 198         gpio_direction_output(S3C2410_GPA(21), 1);
 199         return 0;
 200 }
 201
 202 static void bast_pm_resume(void)
 203 {
 204         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 205 }
 206
 207 #else
 208 #define bast_pm_suspend NULL
 209 #define bast_pm_resume NULL
 210 #endif
 211
 212 static struct syscore_ops bast_pm_syscore_ops = {
 213         .suspend        = bast_pm_suspend,
 214         .resume         = bast_pm_resume,
 215 };
 216
 217 static int smartmedia_map[] = { 0 };
 218 static int chip0_map[] = { 1 };
 219 static int chip1_map[] = { 2 };
 220 static int chip2_map[] = { 3 };
 221
 222 static struct mtd_partition __initdata bast_default_nand_part[] = {
 223         [0] = {
 224                 .name   = "Boot Agent",
 225                 .size   = SZ_16K,
 226                 .offset = 0,
 227         },
 228         [1] = {
 229                 .name   = "/boot",
 230                 .size   = SZ_4M - SZ_16K,
 231                 .offset = SZ_16K,
 232         },
 233         [2] = {
 234                 .name   = "user",
 235                 .offset = SZ_4M,
 236                 .size   = MTDPART_SIZ_FULL,
 237         }
 238 };
 239
 240 /* the bast has 4 selectable slots for nand-flash, the three
 241  * on-board chip areas, as well as the external SmartMedia
 242  * slot.
 243  *
 244  * Note, there is no current hot-plug support for the SmartMedia
 245  * socket.
 246 */
 247
 248 static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
 249         [0] = {
 250                 .name           = "SmartMedia",
 251                 .nr_chips       = 1,
 252                 .nr_map         = smartmedia_map,
 253                 .options        = NAND_SCAN_SILENT_NODEV,
 254                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 255                 .partitions     = bast_default_nand_part,
 256         },
 257         [1] = {
 258                 .name           = "chip0",
 259                 .nr_chips       = 1,
 260                 .nr_map         = chip0_map,
 261                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 262                 .partitions     = bast_default_nand_part,
 263         },
 264         [2] = {
 265                 .name           = "chip1",
 266                 .nr_chips       = 1,
 267                 .nr_map         = chip1_map,
 268                 .options        = NAND_SCAN_SILENT_NODEV,
 269                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 270                 .partitions     = bast_default_nand_part,
 271         },
 272         [3] = {
 273                 .name           = "chip2",
 274                 .nr_chips       = 1,
 275                 .nr_map         = chip2_map,
 276                 .options        = NAND_SCAN_SILENT_NODEV,
 277                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 278                 .partitions     = bast_default_nand_part,
 279         }
 280 };
 281
 282 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
 283 {
 284         unsigned int tmp;
 285
 286         slot = set->nr_map[slot] & 3;
 287
 288         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
 289                  slot, set, set->nr_map);
 290
 291         tmp = __raw_readb(BAST_VA_CTRL2);
 292         tmp &= BAST_CPLD_CTLR2_IDERST;
 293         tmp |= slot;
 294         tmp |= BAST_CPLD_CTRL2_WNAND;
 295
 296         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
 297
 298         __raw_writeb(tmp, BAST_VA_CTRL2);
 299 }
 300
 301 static struct s3c2410_platform_nand __initdata bast_nand_info = {
 302         .tacls          = 30,
 303         .twrph0         = 60,
 304         .twrph1         = 60,
 305         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
 306         .sets           = bast_nand_sets,
 307         .select_chip    = bast_nand_select,
 308 };
 309
 310 /* DM9000 */
 311
 312 static struct resource bast_dm9k_resource[] = {
 313         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
 314         [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
 315         [2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
 316                                         | IORESOURCE_IRQ_HIGHLEVEL),
 317 };
 318
 319 /* for the moment we limit ourselves to 16bit IO until some
 320  * better IO routines can be written and tested
 321 */
 322
 323 static struct dm9000_plat_data bast_dm9k_platdata = {
 324         .flags          = DM9000_PLATF_16BITONLY,
 325 };
 326
 327 static struct platform_device bast_device_dm9k = {
 328         .name           = "dm9000",
 329         .id             = 0,
 330         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
 331         .resource       = bast_dm9k_resource,
 332         .dev            = {
 333                 .platform_data = &bast_dm9k_platdata,
 334         }
 335 };
 336
 337 /* serial devices */
 338
 339 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
 340 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
 341 #define SERIAL_CLK   (1843200)
 342
 343 static struct plat_serial8250_port bast_sio_data[] = {
 344         [0] = {
 345                 .mapbase        = SERIAL_BASE + 0x2f8,
 346                 .irq            = IRQ_PCSERIAL1,
 347                 .flags          = SERIAL_FLAGS,
 348                 .iotype         = UPIO_MEM,
 349                 .regshift       = 0,
 350                 .uartclk        = SERIAL_CLK,
 351         },
 352         [1] = {
 353                 .mapbase        = SERIAL_BASE + 0x3f8,
 354                 .irq            = IRQ_PCSERIAL2,
 355                 .flags          = SERIAL_FLAGS,
 356                 .iotype         = UPIO_MEM,
 357                 .regshift       = 0,
 358                 .uartclk        = SERIAL_CLK,
 359         },
 360         { }
 361 };
 362
 363 static struct platform_device bast_sio = {
 364         .name                   = "serial8250",
 365         .id                     = PLAT8250_DEV_PLATFORM,
 366         .dev                    = {
 367                 .platform_data  = &bast_sio_data,
 368         },
 369 };
 370
 371 /* we have devices on the bus which cannot work much over the
 372  * standard 100KHz i2c bus frequency
 373 */
 374
 375 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
 376         .flags          = 0,
 377         .slave_addr     = 0x10,
 378         .frequency      = 100*1000,
 379 };
 380
 381 /* Asix AX88796 10/100 ethernet controller */
 382
 383 static struct ax_plat_data bast_asix_platdata = {
 384         .flags          = AXFLG_MAC_FROMDEV,
 385         .wordlength     = 2,
 386         .dcr_val        = 0x48,
 387         .rcr_val        = 0x40,
 388 };
 389
 390 static struct resource bast_asix_resource[] = {
 391         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
 392         [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
 393         [2] = DEFINE_RES_IRQ(IRQ_ASIX),
 394 };
 395
 396 static struct platform_device bast_device_asix = {
 397         .name           = "ax88796",
 398         .id             = 0,
 399         .num_resources  = ARRAY_SIZE(bast_asix_resource),
 400         .resource       = bast_asix_resource,
 401         .dev            = {
 402                 .platform_data = &bast_asix_platdata
 403         }
 404 };
 405
 406 /* Asix AX88796 10/100 ethernet controller parallel port */
 407
 408 static struct resource bast_asixpp_resource[] = {
 409         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
 410                                         0x30 * 0x20),
 411 };
 412
 413 static struct platform_device bast_device_axpp = {
 414         .name           = "ax88796-pp",
 415         .id             = 0,
 416         .num_resources  = ARRAY_SIZE(bast_asixpp_resource),
 417         .resource       = bast_asixpp_resource,
 418 };
 419
 420 /* LCD/VGA controller */
 421
 422 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
 423         {
 424                 .type           = S3C2410_LCDCON1_TFT,
 425                 .width          = 640,
 426                 .height         = 480,
 427
 428                 .pixclock       = 33333,
 429                 .xres           = 640,
 430                 .yres           = 480,
 431                 .bpp            = 4,
 432                 .left_margin    = 40,
 433                 .right_margin   = 20,
 434                 .hsync_len      = 88,
 435                 .upper_margin   = 30,
 436                 .lower_margin   = 32,
 437                 .vsync_len      = 3,
 438
 439                 .lcdcon5        = 0x00014b02,
 440         },
 441         {
 442                 .type           = S3C2410_LCDCON1_TFT,
 443                 .width          = 640,
 444                 .height         = 480,
 445
 446                 .pixclock       = 33333,
 447                 .xres           = 640,
 448                 .yres           = 480,
 449                 .bpp            = 8,
 450                 .left_margin    = 40,
 451                 .right_margin   = 20,
 452                 .hsync_len      = 88,
 453                 .upper_margin   = 30,
 454                 .lower_margin   = 32,
 455                 .vsync_len      = 3,
 456
 457                 .lcdcon5        = 0x00014b02,
 458         },
 459         {
 460                 .type           = S3C2410_LCDCON1_TFT,
 461                 .width          = 640,
 462                 .height         = 480,
 463
 464                 .pixclock       = 33333,
 465                 .xres           = 640,
 466                 .yres           = 480,
 467                 .bpp            = 16,
 468                 .left_margin    = 40,
 469                 .right_margin   = 20,
 470                 .hsync_len      = 88,
 471                 .upper_margin   = 30,
 472                 .lower_margin   = 32,
 473                 .vsync_len      = 3,
 474
 475                 .lcdcon5        = 0x00014b02,
 476         },
 477 };
 478
 479 /* LCD/VGA controller */
 480
 481 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
 482
 483         .displays = bast_lcd_info,
 484         .num_displays = ARRAY_SIZE(bast_lcd_info),
 485         .default_display = 1,
 486 };
 487
 488 /* I2C devices fitted. */
 489
 490 static struct i2c_board_info bast_i2c_devs[] __initdata = {
 491         {
 492                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
 493         }, {
 494                 I2C_BOARD_INFO("simtec-pmu", 0x6b),
 495         }, {
 496                 I2C_BOARD_INFO("ch7013", 0x75),
 497         },
 498 };
 499
 500 static struct s3c_hwmon_pdata bast_hwmon_info = {
 501         /* LCD contrast (0-6.6V) */
 502         .in[0] = &(struct s3c_hwmon_chcfg) {
 503                 .name           = "lcd-contrast",
 504                 .mult           = 3300,
 505                 .div            = 512,
 506         },
 507         /* LED current feedback */
 508         .in[1] = &(struct s3c_hwmon_chcfg) {
 509                 .name           = "led-feedback",
 510                 .mult           = 3300,
 511                 .div            = 1024,
 512         },
 513         /* LCD feedback (0-6.6V) */
 514         .in[2] = &(struct s3c_hwmon_chcfg) {
 515                 .name           = "lcd-feedback",
 516                 .mult           = 3300,
 517                 .div            = 512,
 518         },
 519         /* Vcore (1.8-2.0V), Vref 3.3V  */
 520         .in[3] = &(struct s3c_hwmon_chcfg) {
 521                 .name           = "vcore",
 522                 .mult           = 3300,
 523                 .div            = 1024,
 524         },
 525 };
 526
 527 /* Standard BAST devices */
 528 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 529
 530 static struct platform_device *bast_devices[] __initdata = {
 531         &s3c_device_ohci,
 532         &s3c_device_lcd,
 533         &s3c_device_wdt,
 534         &s3c_device_i2c0,
 535         &s3c_device_rtc,
 536         &s3c_device_nand,
 537         &s3c_device_adc,
 538         &s3c_device_hwmon,
 539         &bast_device_dm9k,
 540         &bast_device_asix,
 541         &bast_device_axpp,
 542         &bast_sio,
 543 };
 544
 545 static struct clk *bast_clocks[] __initdata = {
 546         &s3c24xx_dclk0,
 547         &s3c24xx_dclk1,
 548         &s3c24xx_clkout0,
 549         &s3c24xx_clkout1,
 550         &s3c24xx_uclk,
 551 };
 552
 553 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
 554         .refresh        = 7800, /* 7.8usec */
 555         .auto_io        = 1,
 556         .need_io        = 1,
 557 };
 558
 559 static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
 560         .have_mic       = 1,
 561         .have_lout      = 1,
 562 };
 563
 564 static void __init bast_map_io(void)
 565 {
 566         /* initialise the clocks */
 567
 568         s3c24xx_dclk0.parent = &clk_upll;
 569         s3c24xx_dclk0.rate   = 12*1000*1000;
 570
 571         s3c24xx_dclk1.parent = &clk_upll;
 572         s3c24xx_dclk1.rate   = 24*1000*1000;
 573
 574         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 575         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 576
 577         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 578
 579         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
 580
 581         s3c_hwmon_set_platdata(&bast_hwmon_info);
 582
 583         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
 584         s3c24xx_init_clocks(0);
 585         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
 586 }
 587
 588 static void __init bast_init(void)
 589 {
 590         register_syscore_ops(&bast_pm_syscore_ops);
 591
 592         s3c_i2c0_set_platdata(&bast_i2c_info);
 593         s3c_nand_set_platdata(&bast_nand_info);
 594         s3c24xx_fb_set_platdata(&bast_fb_info);
 595         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 596
 597         i2c_register_board_info(0, bast_i2c_devs,
 598                                 ARRAY_SIZE(bast_i2c_devs));
 599
 600         usb_simtec_init();
 601         nor_simtec_init();
 602         simtec_audio_add(NULL, true, &bast_audio);
 603
 604         WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
 605
 606         s3c_cpufreq_setboard(&bast_cpufreq);
 607 }
 608
 609 MACHINE_START(BAST, "Simtec-BAST")
 610         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 611         .atag_offset    = 0x100,
 612         .map_io         = bast_map_io,
 613         .init_irq       = s3c24xx_init_irq,
 614         .init_machine   = bast_init,
 615         .timer          = &s3c24xx_timer,
 616         .restart        = s3c2410_restart,
 617 MACHINE_END