2 * linux/arch/arm/mach-sa1100/irq.c
4 * Copyright (C) 1999-2001 Nicolas Pitre
6 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/ioport.h>
19 #include <linux/syscore_ops.h>
21 #include <mach/hardware.h>
22 #include <mach/irqs.h>
23 #include <asm/mach/irq.h>
24 #include <asm/exception.h>
30 * SA1100 GPIO edge detection for IRQs:
31 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
32 * Use this instead of directly setting GRER/GFER.
34 static int GPIO_IRQ_rising_edge;
35 static int GPIO_IRQ_falling_edge;
36 static int GPIO_IRQ_mask = (1 << 11) - 1;
38 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
44 if (type == IRQ_TYPE_PROBE) {
45 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
47 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
50 if (type & IRQ_TYPE_EDGE_RISING) {
51 GPIO_IRQ_rising_edge |= mask;
53 GPIO_IRQ_rising_edge &= ~mask;
54 if (type & IRQ_TYPE_EDGE_FALLING) {
55 GPIO_IRQ_falling_edge |= mask;
57 GPIO_IRQ_falling_edge &= ~mask;
59 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
60 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
66 * GPIO IRQs must be acknowledged. This is for IRQs from GPIO0 to 10.
68 static void sa1100_low_gpio_ack(struct irq_data *d)
73 static void sa1100_low_gpio_mask(struct irq_data *d)
75 ICMR &= ~BIT(d->hwirq);
78 static void sa1100_low_gpio_unmask(struct irq_data *d)
80 ICMR |= BIT(d->hwirq);
83 static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
86 PWER |= BIT(d->hwirq);
88 PWER &= ~BIT(d->hwirq);
92 static struct irq_chip sa1100_low_gpio_chip = {
94 .irq_ack = sa1100_low_gpio_ack,
95 .irq_mask = sa1100_low_gpio_mask,
96 .irq_unmask = sa1100_low_gpio_unmask,
97 .irq_set_type = sa1100_gpio_type,
98 .irq_set_wake = sa1100_low_gpio_wake,
101 static int sa1100_low_gpio_irqdomain_map(struct irq_domain *d,
102 unsigned int irq, irq_hw_number_t hwirq)
104 irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
106 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
111 static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
112 .map = sa1100_low_gpio_irqdomain_map,
113 .xlate = irq_domain_xlate_onetwocell,
116 static struct irq_domain *sa1100_low_gpio_irqdomain;
119 * IRQ11 (GPIO11 through 27) handler. We enter here with the
120 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
121 * and call the handler.
124 sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
128 mask = GEDR & 0xfffff800;
131 * clear down all currently active IRQ sources.
132 * We will be processing them all.
140 generic_handle_irq(irq);
145 mask = GEDR & 0xfffff800;
150 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
151 * In addition, the IRQs are all collected up into one bit in the
152 * interrupt controller registers.
154 static void sa1100_high_gpio_ack(struct irq_data *d)
156 unsigned int mask = BIT(d->hwirq);
161 static void sa1100_high_gpio_mask(struct irq_data *d)
163 unsigned int mask = BIT(d->hwirq);
165 GPIO_IRQ_mask &= ~mask;
171 static void sa1100_high_gpio_unmask(struct irq_data *d)
173 unsigned int mask = BIT(d->hwirq);
175 GPIO_IRQ_mask |= mask;
177 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
178 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
181 static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
184 PWER |= BIT(d->hwirq);
186 PWER &= ~BIT(d->hwirq);
190 static struct irq_chip sa1100_high_gpio_chip = {
192 .irq_ack = sa1100_high_gpio_ack,
193 .irq_mask = sa1100_high_gpio_mask,
194 .irq_unmask = sa1100_high_gpio_unmask,
195 .irq_set_type = sa1100_gpio_type,
196 .irq_set_wake = sa1100_high_gpio_wake,
199 static int sa1100_high_gpio_irqdomain_map(struct irq_domain *d,
200 unsigned int irq, irq_hw_number_t hwirq)
202 irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
204 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
209 static struct irq_domain_ops sa1100_high_gpio_irqdomain_ops = {
210 .map = sa1100_high_gpio_irqdomain_map,
211 .xlate = irq_domain_xlate_onetwocell,
214 static struct irq_domain *sa1100_high_gpio_irqdomain;
217 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
218 * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
220 static void sa1100_mask_irq(struct irq_data *d)
222 ICMR &= ~BIT(d->hwirq);
225 static void sa1100_unmask_irq(struct irq_data *d)
227 ICMR |= BIT(d->hwirq);
231 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
233 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
235 if (BIT(d->hwirq) == IC_RTCAlrm) {
245 static struct irq_chip sa1100_normal_chip = {
247 .irq_ack = sa1100_mask_irq,
248 .irq_mask = sa1100_mask_irq,
249 .irq_unmask = sa1100_unmask_irq,
250 .irq_set_wake = sa1100_set_wake,
253 static int sa1100_normal_irqdomain_map(struct irq_domain *d,
254 unsigned int irq, irq_hw_number_t hwirq)
256 irq_set_chip_and_handler(irq, &sa1100_normal_chip,
258 set_irq_flags(irq, IRQF_VALID);
263 static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
264 .map = sa1100_normal_irqdomain_map,
265 .xlate = irq_domain_xlate_onetwocell,
268 static struct irq_domain *sa1100_normal_irqdomain;
270 static struct resource irq_resource =
271 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
273 static struct sa1100irq_state {
280 static int sa1100irq_suspend(void)
282 struct sa1100irq_state *st = &sa1100irq_state;
290 * Disable all GPIO-based interrupts.
292 ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
293 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
297 * Set the appropriate edges for wakeup.
299 GRER = PWER & GPIO_IRQ_rising_edge;
300 GFER = PWER & GPIO_IRQ_falling_edge;
303 * Clear any pending GPIO interrupts.
310 static void sa1100irq_resume(void)
312 struct sa1100irq_state *st = &sa1100irq_state;
318 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
319 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
325 static struct syscore_ops sa1100irq_syscore_ops = {
326 .suspend = sa1100irq_suspend,
327 .resume = sa1100irq_resume,
330 static int __init sa1100irq_init_devicefs(void)
332 register_syscore_ops(&sa1100irq_syscore_ops);
336 device_initcall(sa1100irq_init_devicefs);
338 static asmlinkage void __exception_irq_entry
339 sa1100_handle_irq(struct pt_regs *regs)
341 uint32_t icip, icmr, mask;
351 handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0, regs);
355 void __init sa1100_init_irq(void)
357 request_resource(&iomem_resource, &irq_resource);
359 /* disable all IRQs */
362 /* all IRQs are IRQ, not FIQ */
365 /* clear all GPIO edge detects */
371 * Whatever the doc says, this has to be set for the wait-on-irq
372 * instruction to work... on a SA1100 rev 9 at least.
376 sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL,
378 &sa1100_low_gpio_irqdomain_ops, NULL);
380 sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
381 21, IRQ_GPIO11_27, 11,
382 &sa1100_normal_irqdomain_ops, NULL);
384 sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
386 &sa1100_high_gpio_irqdomain_ops, NULL);
389 * Install handler for GPIO 11-27 edge detect interrupts
391 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
393 set_handle_irq(sa1100_handle_irq);