arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/serial_sci.h>
  28 #include <linux/sh_dma.h>
  29 #include <linux/sh_timer.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_data/sh_ipmmu.h>
  32 #include <mach/dma-register.h>
  33 #include <mach/r8a7740.h>
  34 #include <mach/pm-rmobile.h>
  35 #include <mach/common.h>
  36 #include <mach/irqs.h>
  37 #include <asm/mach-types.h>
  38 #include <asm/mach/map.h>
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/time.h>
  41
  42 static struct map_desc r8a7740_io_desc[] __initdata = {
  43          /*
  44           * for CPGA/INTC/PFC
  45           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  46           */
  47         {
  48                 .virtual        = 0xe6000000,
  49                 .pfn            = __phys_to_pfn(0xe6000000),
  50                 .length         = 160 << 20,
  51                 .type           = MT_DEVICE_NONSHARED
  52         },
  53 #ifdef CONFIG_CACHE_L2X0
  54         /*
  55          * for l2x0_init()
  56          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  57          */
  58         {
  59                 .virtual        = 0xf0002000,
  60                 .pfn            = __phys_to_pfn(0xf0100000),
  61                 .length         = PAGE_SIZE,
  62                 .type           = MT_DEVICE_NONSHARED
  63         },
  64 #endif
  65 };
  66
  67 void __init r8a7740_map_io(void)
  68 {
  69         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  70 }
  71
  72 /* SCIFA0 */
  73 static struct plat_sci_port scif0_platform_data = {
  74         .mapbase        = 0xe6c40000,
  75         .flags          = UPF_BOOT_AUTOCONF,
  76         .scscr          = SCSCR_RE | SCSCR_TE,
  77         .scbrr_algo_id  = SCBRR_ALGO_4,
  78         .type           = PORT_SCIFA,
  79         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
  80 };
  81
  82 static struct platform_device scif0_device = {
  83         .name           = "sh-sci",
  84         .id             = 0,
  85         .dev            = {
  86                 .platform_data  = &scif0_platform_data,
  87         },
  88 };
  89
  90 /* SCIFA1 */
  91 static struct plat_sci_port scif1_platform_data = {
  92         .mapbase        = 0xe6c50000,
  93         .flags          = UPF_BOOT_AUTOCONF,
  94         .scscr          = SCSCR_RE | SCSCR_TE,
  95         .scbrr_algo_id  = SCBRR_ALGO_4,
  96         .type           = PORT_SCIFA,
  97         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
  98 };
  99
 100 static struct platform_device scif1_device = {
 101         .name           = "sh-sci",
 102         .id             = 1,
 103         .dev            = {
 104                 .platform_data  = &scif1_platform_data,
 105         },
 106 };
 107
 108 /* SCIFA2 */
 109 static struct plat_sci_port scif2_platform_data = {
 110         .mapbase        = 0xe6c60000,
 111         .flags          = UPF_BOOT_AUTOCONF,
 112         .scscr          = SCSCR_RE | SCSCR_TE,
 113         .scbrr_algo_id  = SCBRR_ALGO_4,
 114         .type           = PORT_SCIFA,
 115         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
 116 };
 117
 118 static struct platform_device scif2_device = {
 119         .name           = "sh-sci",
 120         .id             = 2,
 121         .dev            = {
 122                 .platform_data  = &scif2_platform_data,
 123         },
 124 };
 125
 126 /* SCIFA3 */
 127 static struct plat_sci_port scif3_platform_data = {
 128         .mapbase        = 0xe6c70000,
 129         .flags          = UPF_BOOT_AUTOCONF,
 130         .scscr          = SCSCR_RE | SCSCR_TE,
 131         .scbrr_algo_id  = SCBRR_ALGO_4,
 132         .type           = PORT_SCIFA,
 133         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
 134 };
 135
 136 static struct platform_device scif3_device = {
 137         .name           = "sh-sci",
 138         .id             = 3,
 139         .dev            = {
 140                 .platform_data  = &scif3_platform_data,
 141         },
 142 };
 143
 144 /* SCIFA4 */
 145 static struct plat_sci_port scif4_platform_data = {
 146         .mapbase        = 0xe6c80000,
 147         .flags          = UPF_BOOT_AUTOCONF,
 148         .scscr          = SCSCR_RE | SCSCR_TE,
 149         .scbrr_algo_id  = SCBRR_ALGO_4,
 150         .type           = PORT_SCIFA,
 151         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
 152 };
 153
 154 static struct platform_device scif4_device = {
 155         .name           = "sh-sci",
 156         .id             = 4,
 157         .dev            = {
 158                 .platform_data  = &scif4_platform_data,
 159         },
 160 };
 161
 162 /* SCIFA5 */
 163 static struct plat_sci_port scif5_platform_data = {
 164         .mapbase        = 0xe6cb0000,
 165         .flags          = UPF_BOOT_AUTOCONF,
 166         .scscr          = SCSCR_RE | SCSCR_TE,
 167         .scbrr_algo_id  = SCBRR_ALGO_4,
 168         .type           = PORT_SCIFA,
 169         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
 170 };
 171
 172 static struct platform_device scif5_device = {
 173         .name           = "sh-sci",
 174         .id             = 5,
 175         .dev            = {
 176                 .platform_data  = &scif5_platform_data,
 177         },
 178 };
 179
 180 /* SCIFA6 */
 181 static struct plat_sci_port scif6_platform_data = {
 182         .mapbase        = 0xe6cc0000,
 183         .flags          = UPF_BOOT_AUTOCONF,
 184         .scscr          = SCSCR_RE | SCSCR_TE,
 185         .scbrr_algo_id  = SCBRR_ALGO_4,
 186         .type           = PORT_SCIFA,
 187         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
 188 };
 189
 190 static struct platform_device scif6_device = {
 191         .name           = "sh-sci",
 192         .id             = 6,
 193         .dev            = {
 194                 .platform_data  = &scif6_platform_data,
 195         },
 196 };
 197
 198 /* SCIFA7 */
 199 static struct plat_sci_port scif7_platform_data = {
 200         .mapbase        = 0xe6cd0000,
 201         .flags          = UPF_BOOT_AUTOCONF,
 202         .scscr          = SCSCR_RE | SCSCR_TE,
 203         .scbrr_algo_id  = SCBRR_ALGO_4,
 204         .type           = PORT_SCIFA,
 205         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
 206 };
 207
 208 static struct platform_device scif7_device = {
 209         .name           = "sh-sci",
 210         .id             = 7,
 211         .dev            = {
 212                 .platform_data  = &scif7_platform_data,
 213         },
 214 };
 215
 216 /* SCIFB */
 217 static struct plat_sci_port scifb_platform_data = {
 218         .mapbase        = 0xe6c30000,
 219         .flags          = UPF_BOOT_AUTOCONF,
 220         .scscr          = SCSCR_RE | SCSCR_TE,
 221         .scbrr_algo_id  = SCBRR_ALGO_4,
 222         .type           = PORT_SCIFB,
 223         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
 224 };
 225
 226 static struct platform_device scifb_device = {
 227         .name           = "sh-sci",
 228         .id             = 8,
 229         .dev            = {
 230                 .platform_data  = &scifb_platform_data,
 231         },
 232 };
 233
 234 /* CMT */
 235 static struct sh_timer_config cmt10_platform_data = {
 236         .name = "CMT10",
 237         .channel_offset = 0x10,
 238         .timer_bit = 0,
 239         .clockevent_rating = 125,
 240         .clocksource_rating = 125,
 241 };
 242
 243 static struct resource cmt10_resources[] = {
 244         [0] = {
 245                 .name   = "CMT10",
 246                 .start  = 0xe6138010,
 247                 .end    = 0xe613801b,
 248                 .flags  = IORESOURCE_MEM,
 249         },
 250         [1] = {
 251                 .start  = evt2irq(0x0b00),
 252                 .flags  = IORESOURCE_IRQ,
 253         },
 254 };
 255
 256 static struct platform_device cmt10_device = {
 257         .name           = "sh_cmt",
 258         .id             = 10,
 259         .dev = {
 260                 .platform_data  = &cmt10_platform_data,
 261         },
 262         .resource       = cmt10_resources,
 263         .num_resources  = ARRAY_SIZE(cmt10_resources),
 264 };
 265
 266 /* IPMMUI (an IPMMU module for ICB/LMB) */
 267 static struct resource ipmmu_resources[] = {
 268         [0] = {
 269                 .name   = "IPMMUI",
 270                 .start  = 0xfe951000,
 271                 .end    = 0xfe9510ff,
 272                 .flags  = IORESOURCE_MEM,
 273         },
 274 };
 275
 276 static const char * const ipmmu_dev_names[] = {
 277         "sh_mobile_lcdc_fb.0",
 278         "sh_mobile_lcdc_fb.1",
 279         "sh_mobile_ceu.0",
 280 };
 281
 282 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 283         .dev_names = ipmmu_dev_names,
 284         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 285 };
 286
 287 static struct platform_device ipmmu_device = {
 288         .name           = "ipmmu",
 289         .id             = -1,
 290         .dev = {
 291                 .platform_data = &ipmmu_platform_data,
 292         },
 293         .resource       = ipmmu_resources,
 294         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 295 };
 296
 297 static struct platform_device *r8a7740_early_devices[] __initdata = {
 298         &scif0_device,
 299         &scif1_device,
 300         &scif2_device,
 301         &scif3_device,
 302         &scif4_device,
 303         &scif5_device,
 304         &scif6_device,
 305         &scif7_device,
 306         &scifb_device,
 307         &cmt10_device,
 308         &ipmmu_device,
 309 };
 310
 311 /* DMA */
 312 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 313         {
 314                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 315                 .addr           = 0xe6850030,
 316                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 317                 .mid_rid        = 0xc1,
 318         }, {
 319                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 320                 .addr           = 0xe6850030,
 321                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 322                 .mid_rid        = 0xc2,
 323         }, {
 324                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 325                 .addr           = 0xe6860030,
 326                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 327                 .mid_rid        = 0xc9,
 328         }, {
 329                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 330                 .addr           = 0xe6860030,
 331                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 332                 .mid_rid        = 0xca,
 333         }, {
 334                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 335                 .addr           = 0xe6870030,
 336                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 337                 .mid_rid        = 0xcd,
 338         }, {
 339                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 340                 .addr           = 0xe6870030,
 341                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 342                 .mid_rid        = 0xce,
 343         }, {
 344                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 345                 .addr           = 0xfe1f0024,
 346                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 347                 .mid_rid        = 0xb1,
 348         }, {
 349                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 350                 .addr           = 0xfe1f0020,
 351                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 352                 .mid_rid        = 0xb2,
 353         }, {
 354                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 355                 .addr           = 0xfe1f0064,
 356                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 357                 .mid_rid        = 0xb5,
 358         },
 359 };
 360
 361 #define DMA_CHANNEL(a, b, c)                    \
 362 {                                               \
 363         .offset         = a,                    \
 364         .dmars          = b,                    \
 365         .dmars_bit      = c,                    \
 366         .chclr_offset   = (0x220 - 0x20) + a    \
 367 }
 368
 369 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 370         DMA_CHANNEL(0x00, 0, 0),
 371         DMA_CHANNEL(0x10, 0, 8),
 372         DMA_CHANNEL(0x20, 4, 0),
 373         DMA_CHANNEL(0x30, 4, 8),
 374         DMA_CHANNEL(0x50, 8, 0),
 375         DMA_CHANNEL(0x60, 8, 8),
 376 };
 377
 378 static struct sh_dmae_pdata dma_platform_data = {
 379         .slave          = r8a7740_dmae_slaves,
 380         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 381         .channel        = r8a7740_dmae_channels,
 382         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 383         .ts_low_shift   = TS_LOW_SHIFT,
 384         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 385         .ts_high_shift  = TS_HI_SHIFT,
 386         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 387         .ts_shift       = dma_ts_shift,
 388         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 389         .dmaor_init     = DMAOR_DME,
 390         .chclr_present  = 1,
 391 };
 392
 393 /* Resource order important! */
 394 static struct resource r8a7740_dmae0_resources[] = {
 395         {
 396                 /* Channel registers and DMAOR */
 397                 .start  = 0xfe008020,
 398                 .end    = 0xfe00828f,
 399                 .flags  = IORESOURCE_MEM,
 400         },
 401         {
 402                 /* DMARSx */
 403                 .start  = 0xfe009000,
 404                 .end    = 0xfe00900b,
 405                 .flags  = IORESOURCE_MEM,
 406         },
 407         {
 408                 .name   = "error_irq",
 409                 .start  = evt2irq(0x20c0),
 410                 .end    = evt2irq(0x20c0),
 411                 .flags  = IORESOURCE_IRQ,
 412         },
 413         {
 414                 /* IRQ for channels 0-5 */
 415                 .start  = evt2irq(0x2000),
 416                 .end    = evt2irq(0x20a0),
 417                 .flags  = IORESOURCE_IRQ,
 418         },
 419 };
 420
 421 /* Resource order important! */
 422 static struct resource r8a7740_dmae1_resources[] = {
 423         {
 424                 /* Channel registers and DMAOR */
 425                 .start  = 0xfe018020,
 426                 .end    = 0xfe01828f,
 427                 .flags  = IORESOURCE_MEM,
 428         },
 429         {
 430                 /* DMARSx */
 431                 .start  = 0xfe019000,
 432                 .end    = 0xfe01900b,
 433                 .flags  = IORESOURCE_MEM,
 434         },
 435         {
 436                 .name   = "error_irq",
 437                 .start  = evt2irq(0x21c0),
 438                 .end    = evt2irq(0x21c0),
 439                 .flags  = IORESOURCE_IRQ,
 440         },
 441         {
 442                 /* IRQ for channels 0-5 */
 443                 .start  = evt2irq(0x2100),
 444                 .end    = evt2irq(0x21a0),
 445                 .flags  = IORESOURCE_IRQ,
 446         },
 447 };
 448
 449 /* Resource order important! */
 450 static struct resource r8a7740_dmae2_resources[] = {
 451         {
 452                 /* Channel registers and DMAOR */
 453                 .start  = 0xfe028020,
 454                 .end    = 0xfe02828f,
 455                 .flags  = IORESOURCE_MEM,
 456         },
 457         {
 458                 /* DMARSx */
 459                 .start  = 0xfe029000,
 460                 .end    = 0xfe02900b,
 461                 .flags  = IORESOURCE_MEM,
 462         },
 463         {
 464                 .name   = "error_irq",
 465                 .start  = evt2irq(0x22c0),
 466                 .end    = evt2irq(0x22c0),
 467                 .flags  = IORESOURCE_IRQ,
 468         },
 469         {
 470                 /* IRQ for channels 0-5 */
 471                 .start  = evt2irq(0x2200),
 472                 .end    = evt2irq(0x22a0),
 473                 .flags  = IORESOURCE_IRQ,
 474         },
 475 };
 476
 477 static struct platform_device dma0_device = {
 478         .name           = "sh-dma-engine",
 479         .id             = 0,
 480         .resource       = r8a7740_dmae0_resources,
 481         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 482         .dev            = {
 483                 .platform_data  = &dma_platform_data,
 484         },
 485 };
 486
 487 static struct platform_device dma1_device = {
 488         .name           = "sh-dma-engine",
 489         .id             = 1,
 490         .resource       = r8a7740_dmae1_resources,
 491         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 492         .dev            = {
 493                 .platform_data  = &dma_platform_data,
 494         },
 495 };
 496
 497 static struct platform_device dma2_device = {
 498         .name           = "sh-dma-engine",
 499         .id             = 2,
 500         .resource       = r8a7740_dmae2_resources,
 501         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 502         .dev            = {
 503                 .platform_data  = &dma_platform_data,
 504         },
 505 };
 506
 507 /* USB-DMAC */
 508 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 509         {
 510                 .offset = 0,
 511         }, {
 512                 .offset = 0x20,
 513         },
 514 };
 515
 516 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 517         {
 518                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 519                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 520         }, {
 521                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 522                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 523         },
 524 };
 525
 526 static struct sh_dmae_pdata usb_dma_platform_data = {
 527         .slave          = r8a7740_usb_dma_slaves,
 528         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 529         .channel        = r8a7740_usb_dma_channels,
 530         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 531         .ts_low_shift   = USBTS_LOW_SHIFT,
 532         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 533         .ts_high_shift  = USBTS_HI_SHIFT,
 534         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 535         .ts_shift       = dma_usbts_shift,
 536         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 537         .dmaor_init     = DMAOR_DME,
 538         .chcr_offset    = 0x14,
 539         .chcr_ie_bit    = 1 << 5,
 540         .dmaor_is_32bit = 1,
 541         .needs_tend_set = 1,
 542         .no_dmars       = 1,
 543         .slave_only     = 1,
 544 };
 545
 546 static struct resource r8a7740_usb_dma_resources[] = {
 547         {
 548                 /* Channel registers and DMAOR */
 549                 .start  = 0xe68a0020,
 550                 .end    = 0xe68a0064 - 1,
 551                 .flags  = IORESOURCE_MEM,
 552         },
 553         {
 554                 /* VCR/SWR/DMICR */
 555                 .start  = 0xe68a0000,
 556                 .end    = 0xe68a0014 - 1,
 557                 .flags  = IORESOURCE_MEM,
 558         },
 559         {
 560                 /* IRQ for channels */
 561                 .start  = evt2irq(0x0a00),
 562                 .end    = evt2irq(0x0a00),
 563                 .flags  = IORESOURCE_IRQ,
 564         },
 565 };
 566
 567 static struct platform_device usb_dma_device = {
 568         .name           = "sh-dma-engine",
 569         .id             = 3,
 570         .resource       = r8a7740_usb_dma_resources,
 571         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 572         .dev            = {
 573                 .platform_data  = &usb_dma_platform_data,
 574         },
 575 };
 576
 577 /* I2C */
 578 static struct resource i2c0_resources[] = {
 579         [0] = {
 580                 .name   = "IIC0",
 581                 .start  = 0xfff20000,
 582                 .end    = 0xfff20425 - 1,
 583                 .flags  = IORESOURCE_MEM,
 584         },
 585         [1] = {
 586                 .start  = intcs_evt2irq(0xe00),
 587                 .end    = intcs_evt2irq(0xe60),
 588                 .flags  = IORESOURCE_IRQ,
 589         },
 590 };
 591
 592 static struct resource i2c1_resources[] = {
 593         [0] = {
 594                 .name   = "IIC1",
 595                 .start  = 0xe6c20000,
 596                 .end    = 0xe6c20425 - 1,
 597                 .flags  = IORESOURCE_MEM,
 598         },
 599         [1] = {
 600                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 601                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 602                 .flags  = IORESOURCE_IRQ,
 603         },
 604 };
 605
 606 static struct platform_device i2c0_device = {
 607         .name           = "i2c-sh_mobile",
 608         .id             = 0,
 609         .resource       = i2c0_resources,
 610         .num_resources  = ARRAY_SIZE(i2c0_resources),
 611 };
 612
 613 static struct platform_device i2c1_device = {
 614         .name           = "i2c-sh_mobile",
 615         .id             = 1,
 616         .resource       = i2c1_resources,
 617         .num_resources  = ARRAY_SIZE(i2c1_resources),
 618 };
 619
 620 static struct resource pmu_resources[] = {
 621         [0] = {
 622                 .start  = evt2irq(0x19a0),
 623                 .end    = evt2irq(0x19a0),
 624                 .flags  = IORESOURCE_IRQ,
 625         },
 626 };
 627
 628 static struct platform_device pmu_device = {
 629         .name   = "arm-pmu",
 630         .id     = -1,
 631         .num_resources = ARRAY_SIZE(pmu_resources),
 632         .resource = pmu_resources,
 633 };
 634
 635 static struct platform_device *r8a7740_late_devices[] __initdata = {
 636         &i2c0_device,
 637         &i2c1_device,
 638         &dma0_device,
 639         &dma1_device,
 640         &dma2_device,
 641         &usb_dma_device,
 642         &pmu_device,
 643 };
 644
 645 /*
 646  * r8a7740 chip has lasting errata on MERAM buffer.
 647  * this is work-around for it.
 648  * see
 649  *      "Media RAM (MERAM)" on r8a7740 documentation
 650  */
 651 #define MEBUFCNTR       0xFE950098
 652 void r8a7740_meram_workaround(void)
 653 {
 654         void __iomem *reg;
 655
 656         reg = ioremap_nocache(MEBUFCNTR, 4);
 657         if (reg) {
 658                 iowrite32(0x01600164, reg);
 659                 iounmap(reg);
 660         }
 661 }
 662
 663 #define ICCR    0x0004
 664 #define ICSTART 0x0070
 665
 666 #define i2c_read(reg, offset)           ioread8(reg + offset)
 667 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 668
 669 /*
 670  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 671  * this is work-around for it.
 672  */
 673 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 674 {
 675         struct resource *res;
 676         void __iomem *reg;
 677
 678         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 679         if (unlikely(!res)) {
 680                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 681                 return;
 682         }
 683
 684         reg = ioremap(res->start, resource_size(res));
 685         if (unlikely(!reg)) {
 686                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 687                 return;
 688         }
 689
 690         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 691         i2c_read(reg, ICCR); /* dummy read */
 692
 693         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 694         i2c_read(reg, ICSTART); /* dummy read */
 695
 696         udelay(10);
 697
 698         i2c_write(reg, ICCR, 0x01);
 699         i2c_write(reg, ICSTART, 0x00);
 700
 701         udelay(10);
 702
 703         i2c_write(reg, ICCR, 0x10);
 704         udelay(10);
 705         i2c_write(reg, ICCR, 0x00);
 706         udelay(10);
 707         i2c_write(reg, ICCR, 0x10);
 708         udelay(10);
 709
 710         iounmap(reg);
 711 }
 712
 713 void __init r8a7740_add_standard_devices(void)
 714 {
 715         /* I2C work-around */
 716         r8a7740_i2c_workaround(&i2c0_device);
 717         r8a7740_i2c_workaround(&i2c1_device);
 718
 719         r8a7740_init_pm_domains();
 720
 721         /* add devices */
 722         platform_add_devices(r8a7740_early_devices,
 723                             ARRAY_SIZE(r8a7740_early_devices));
 724         platform_add_devices(r8a7740_late_devices,
 725                              ARRAY_SIZE(r8a7740_late_devices));
 726
 727         /* add devices to PM domain  */
 728
 729         rmobile_add_device_to_domain("A3SP",    &scif0_device);
 730         rmobile_add_device_to_domain("A3SP",    &scif1_device);
 731         rmobile_add_device_to_domain("A3SP",    &scif2_device);
 732         rmobile_add_device_to_domain("A3SP",    &scif3_device);
 733         rmobile_add_device_to_domain("A3SP",    &scif4_device);
 734         rmobile_add_device_to_domain("A3SP",    &scif5_device);
 735         rmobile_add_device_to_domain("A3SP",    &scif6_device);
 736         rmobile_add_device_to_domain("A3SP",    &scif7_device);
 737         rmobile_add_device_to_domain("A3SP",    &scifb_device);
 738         rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 739 }
 740
 741 static void __init r8a7740_earlytimer_init(void)
 742 {
 743         r8a7740_clock_init(0);
 744         shmobile_earlytimer_init();
 745 }
 746
 747 void __init r8a7740_add_early_devices(void)
 748 {
 749         early_platform_add_devices(r8a7740_early_devices,
 750                                    ARRAY_SIZE(r8a7740_early_devices));
 751
 752         /* setup early console here as well */
 753         shmobile_setup_console();
 754
 755         /* override timer setup with soc-specific code */
 756         shmobile_timer.init = r8a7740_earlytimer_init;
 757 }
 758
 759 #ifdef CONFIG_USE_OF
 760
 761 void __init r8a7740_add_early_devices_dt(void)
 762 {
 763         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
 764
 765         early_platform_add_devices(r8a7740_early_devices,
 766                                    ARRAY_SIZE(r8a7740_early_devices));
 767
 768         /* setup early console here as well */
 769         shmobile_setup_console();
 770 }
 771
 772 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
 773         { }
 774 };
 775
 776 void __init r8a7740_add_standard_devices_dt(void)
 777 {
 778         /* clocks are setup late during boot in the case of DT */
 779         r8a7740_clock_init(0);
 780
 781         platform_add_devices(r8a7740_early_devices,
 782                             ARRAY_SIZE(r8a7740_early_devices));
 783
 784         of_platform_populate(NULL, of_default_bus_match_table,
 785                              r8a7740_auxdata_lookup, NULL);
 786 }
 787
 788 static const char *r8a7740_boards_compat_dt[] __initdata = {
 789         "renesas,r8a7740",
 790         NULL,
 791 };
 792
 793 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
 794         .map_io         = r8a7740_map_io,
 795         .init_early     = r8a7740_add_early_devices_dt,
 796         .init_irq       = r8a7740_init_irq,
 797         .handle_irq     = shmobile_handle_irq_intc,
 798         .init_machine   = r8a7740_add_standard_devices_dt,
 799         .timer          = &shmobile_timer,
 800         .dt_compat      = r8a7740_boards_compat_dt,
 801 MACHINE_END
 802
 803 #endif /* CONFIG_USE_OF */