arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/arm-gic.h>
  27 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/platform_data/sh_ipmmu.h>
  34
  35 #include <asm/mach-types.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/time.h>
  39
  40 #include "common.h"
  41 #include "dma-register.h"
  42 #include "irqs.h"
  43 #include "pm-rmobile.h"
  44 #include "r8a7740.h"
  45
  46 static struct map_desc r8a7740_io_desc[] __initdata = {
  47          /*
  48           * for CPGA/INTC/PFC
  49           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  50           */
  51         {
  52                 .virtual        = 0xe6000000,
  53                 .pfn            = __phys_to_pfn(0xe6000000),
  54                 .length         = 160 << 20,
  55                 .type           = MT_DEVICE_NONSHARED
  56         },
  57 #ifdef CONFIG_CACHE_L2X0
  58         /*
  59          * for l2x0_init()
  60          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  61          */
  62         {
  63                 .virtual        = 0xf0002000,
  64                 .pfn            = __phys_to_pfn(0xf0100000),
  65                 .length         = PAGE_SIZE,
  66                 .type           = MT_DEVICE_NONSHARED
  67         },
  68 #endif
  69 };
  70
  71 void __init r8a7740_map_io(void)
  72 {
  73         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  74 }
  75
  76 /* PFC */
  77 static const struct resource pfc_resources[] = {
  78         DEFINE_RES_MEM(0xe6050000, 0x8000),
  79         DEFINE_RES_MEM(0xe605800c, 0x0020),
  80 };
  81
  82 void __init r8a7740_pinmux_init(void)
  83 {
  84         platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
  85                                         ARRAY_SIZE(pfc_resources));
  86 }
  87
  88 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
  89         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
  90 };
  91
  92 static struct resource irqpin0_resources[] = {
  93         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
  94         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
  95         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
  96         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
  97         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
  98         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
  99         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
 100         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
 101         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
 102         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
 103         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
 104         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
 105         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
 106 };
 107
 108 static struct platform_device irqpin0_device = {
 109         .name           = "renesas_intc_irqpin",
 110         .id             = 0,
 111         .resource       = irqpin0_resources,
 112         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 113         .dev            = {
 114                 .platform_data  = &irqpin0_platform_data,
 115         },
 116 };
 117
 118 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 119         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 120 };
 121
 122 static struct resource irqpin1_resources[] = {
 123         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 124         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 125         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 126         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 127         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 128         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
 129         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
 130         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
 131         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
 132         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
 133         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
 134         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
 135         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
 136 };
 137
 138 static struct platform_device irqpin1_device = {
 139         .name           = "renesas_intc_irqpin",
 140         .id             = 1,
 141         .resource       = irqpin1_resources,
 142         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 143         .dev            = {
 144                 .platform_data  = &irqpin1_platform_data,
 145         },
 146 };
 147
 148 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 149         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 150 };
 151
 152 static struct resource irqpin2_resources[] = {
 153         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 154         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
 155         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
 156         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
 157         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
 158         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
 159         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
 160         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
 161         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
 162         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
 163         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
 164         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
 165         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
 166 };
 167
 168 static struct platform_device irqpin2_device = {
 169         .name           = "renesas_intc_irqpin",
 170         .id             = 2,
 171         .resource       = irqpin2_resources,
 172         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 173         .dev            = {
 174                 .platform_data  = &irqpin2_platform_data,
 175         },
 176 };
 177
 178 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 179         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 180 };
 181
 182 static struct resource irqpin3_resources[] = {
 183         DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
 184         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 185         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 186         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 187         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 188         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
 189         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
 190         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
 191         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
 192         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
 193         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
 194         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
 195         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
 196 };
 197
 198 static struct platform_device irqpin3_device = {
 199         .name           = "renesas_intc_irqpin",
 200         .id             = 3,
 201         .resource       = irqpin3_resources,
 202         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 203         .dev            = {
 204                 .platform_data  = &irqpin3_platform_data,
 205         },
 206 };
 207
 208 /* SCIF */
 209 #define R8A7740_SCIF(scif_type, index, baseaddr, irq)           \
 210 static struct plat_sci_port scif##index##_platform_data = {     \
 211         .type           = scif_type,                            \
 212         .flags          = UPF_BOOT_AUTOCONF,                    \
 213         .scscr          = SCSCR_RE | SCSCR_TE,                  \
 214 };                                                              \
 215                                                                 \
 216 static struct resource scif##index##_resources[] = {            \
 217         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 218         DEFINE_RES_IRQ(irq),                                    \
 219 };                                                              \
 220                                                                 \
 221 static struct platform_device scif##index##_device = {          \
 222         .name           = "sh-sci",                             \
 223         .id             = index,                                \
 224         .resource       = scif##index##_resources,              \
 225         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 226         .dev            = {                                     \
 227                 .platform_data  = &scif##index##_platform_data, \
 228         },                                                      \
 229 }
 230
 231 R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
 232 R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
 233 R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
 234 R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
 235 R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
 236 R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
 237 R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
 238 R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
 239 R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
 240
 241 /* CMT */
 242 static struct sh_timer_config cmt1_platform_data = {
 243         .channels_mask = 0x3f,
 244 };
 245
 246 static struct resource cmt1_resources[] = {
 247         DEFINE_RES_MEM(0xe6138000, 0x170),
 248         DEFINE_RES_IRQ(gic_spi(58)),
 249 };
 250
 251 static struct platform_device cmt1_device = {
 252         .name           = "sh-cmt-48",
 253         .id             = 1,
 254         .dev = {
 255                 .platform_data  = &cmt1_platform_data,
 256         },
 257         .resource       = cmt1_resources,
 258         .num_resources  = ARRAY_SIZE(cmt1_resources),
 259 };
 260
 261 /* TMU */
 262 static struct sh_timer_config tmu0_platform_data = {
 263         .channels_mask = 7,
 264 };
 265
 266 static struct resource tmu0_resources[] = {
 267         DEFINE_RES_MEM(0xfff80000, 0x2c),
 268         DEFINE_RES_IRQ(gic_spi(198)),
 269         DEFINE_RES_IRQ(gic_spi(199)),
 270         DEFINE_RES_IRQ(gic_spi(200)),
 271 };
 272
 273 static struct platform_device tmu0_device = {
 274         .name           = "sh-tmu",
 275         .id             = 0,
 276         .dev = {
 277                 .platform_data  = &tmu0_platform_data,
 278         },
 279         .resource       = tmu0_resources,
 280         .num_resources  = ARRAY_SIZE(tmu0_resources),
 281 };
 282
 283 /* IPMMUI (an IPMMU module for ICB/LMB) */
 284 static struct resource ipmmu_resources[] = {
 285         [0] = {
 286                 .name   = "IPMMUI",
 287                 .start  = 0xfe951000,
 288                 .end    = 0xfe9510ff,
 289                 .flags  = IORESOURCE_MEM,
 290         },
 291 };
 292
 293 static const char * const ipmmu_dev_names[] = {
 294         "sh_mobile_lcdc_fb.0",
 295         "sh_mobile_lcdc_fb.1",
 296         "sh_mobile_ceu.0",
 297 };
 298
 299 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 300         .dev_names = ipmmu_dev_names,
 301         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 302 };
 303
 304 static struct platform_device ipmmu_device = {
 305         .name           = "ipmmu",
 306         .id             = -1,
 307         .dev = {
 308                 .platform_data = &ipmmu_platform_data,
 309         },
 310         .resource       = ipmmu_resources,
 311         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 312 };
 313
 314 static struct platform_device *r8a7740_early_devices[] __initdata = {
 315         &scif0_device,
 316         &scif1_device,
 317         &scif2_device,
 318         &scif3_device,
 319         &scif4_device,
 320         &scif5_device,
 321         &scif6_device,
 322         &scif7_device,
 323         &scif8_device,
 324         &irqpin0_device,
 325         &irqpin1_device,
 326         &irqpin2_device,
 327         &irqpin3_device,
 328         &tmu0_device,
 329         &ipmmu_device,
 330         &cmt1_device,
 331 };
 332
 333 /* DMA */
 334 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 335         {
 336                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 337                 .addr           = 0xe6850030,
 338                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 339                 .mid_rid        = 0xc1,
 340         }, {
 341                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 342                 .addr           = 0xe6850030,
 343                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 344                 .mid_rid        = 0xc2,
 345         }, {
 346                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 347                 .addr           = 0xe6860030,
 348                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 349                 .mid_rid        = 0xc9,
 350         }, {
 351                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 352                 .addr           = 0xe6860030,
 353                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 354                 .mid_rid        = 0xca,
 355         }, {
 356                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 357                 .addr           = 0xe6870030,
 358                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 359                 .mid_rid        = 0xcd,
 360         }, {
 361                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 362                 .addr           = 0xe6870030,
 363                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 364                 .mid_rid        = 0xce,
 365         }, {
 366                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 367                 .addr           = 0xfe1f0024,
 368                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 369                 .mid_rid        = 0xb1,
 370         }, {
 371                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 372                 .addr           = 0xfe1f0020,
 373                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 374                 .mid_rid        = 0xb2,
 375         }, {
 376                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 377                 .addr           = 0xfe1f0064,
 378                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 379                 .mid_rid        = 0xb5,
 380         }, {
 381                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 382                 .addr           = 0xe6bd0034,
 383                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 384                 .mid_rid        = 0xd1,
 385         }, {
 386                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 387                 .addr           = 0xe6bd0034,
 388                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 389                 .mid_rid        = 0xd2,
 390         },
 391 };
 392
 393 #define DMA_CHANNEL(a, b, c)                    \
 394 {                                               \
 395         .offset         = a,                    \
 396         .dmars          = b,                    \
 397         .dmars_bit      = c,                    \
 398         .chclr_offset   = (0x220 - 0x20) + a    \
 399 }
 400
 401 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 402         DMA_CHANNEL(0x00, 0, 0),
 403         DMA_CHANNEL(0x10, 0, 8),
 404         DMA_CHANNEL(0x20, 4, 0),
 405         DMA_CHANNEL(0x30, 4, 8),
 406         DMA_CHANNEL(0x50, 8, 0),
 407         DMA_CHANNEL(0x60, 8, 8),
 408 };
 409
 410 static struct sh_dmae_pdata dma_platform_data = {
 411         .slave          = r8a7740_dmae_slaves,
 412         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 413         .channel        = r8a7740_dmae_channels,
 414         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 415         .ts_low_shift   = TS_LOW_SHIFT,
 416         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 417         .ts_high_shift  = TS_HI_SHIFT,
 418         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 419         .ts_shift       = dma_ts_shift,
 420         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 421         .dmaor_init     = DMAOR_DME,
 422         .chclr_present  = 1,
 423 };
 424
 425 /* Resource order important! */
 426 static struct resource r8a7740_dmae0_resources[] = {
 427         {
 428                 /* Channel registers and DMAOR */
 429                 .start  = 0xfe008020,
 430                 .end    = 0xfe00828f,
 431                 .flags  = IORESOURCE_MEM,
 432         },
 433         {
 434                 /* DMARSx */
 435                 .start  = 0xfe009000,
 436                 .end    = 0xfe00900b,
 437                 .flags  = IORESOURCE_MEM,
 438         },
 439         {
 440                 .name   = "error_irq",
 441                 .start  = gic_spi(34),
 442                 .end    = gic_spi(34),
 443                 .flags  = IORESOURCE_IRQ,
 444         },
 445         {
 446                 /* IRQ for channels 0-5 */
 447                 .start  = gic_spi(28),
 448                 .end    = gic_spi(33),
 449                 .flags  = IORESOURCE_IRQ,
 450         },
 451 };
 452
 453 /* Resource order important! */
 454 static struct resource r8a7740_dmae1_resources[] = {
 455         {
 456                 /* Channel registers and DMAOR */
 457                 .start  = 0xfe018020,
 458                 .end    = 0xfe01828f,
 459                 .flags  = IORESOURCE_MEM,
 460         },
 461         {
 462                 /* DMARSx */
 463                 .start  = 0xfe019000,
 464                 .end    = 0xfe01900b,
 465                 .flags  = IORESOURCE_MEM,
 466         },
 467         {
 468                 .name   = "error_irq",
 469                 .start  = gic_spi(41),
 470                 .end    = gic_spi(41),
 471                 .flags  = IORESOURCE_IRQ,
 472         },
 473         {
 474                 /* IRQ for channels 0-5 */
 475                 .start  = gic_spi(35),
 476                 .end    = gic_spi(40),
 477                 .flags  = IORESOURCE_IRQ,
 478         },
 479 };
 480
 481 /* Resource order important! */
 482 static struct resource r8a7740_dmae2_resources[] = {
 483         {
 484                 /* Channel registers and DMAOR */
 485                 .start  = 0xfe028020,
 486                 .end    = 0xfe02828f,
 487                 .flags  = IORESOURCE_MEM,
 488         },
 489         {
 490                 /* DMARSx */
 491                 .start  = 0xfe029000,
 492                 .end    = 0xfe02900b,
 493                 .flags  = IORESOURCE_MEM,
 494         },
 495         {
 496                 .name   = "error_irq",
 497                 .start  = gic_spi(48),
 498                 .end    = gic_spi(48),
 499                 .flags  = IORESOURCE_IRQ,
 500         },
 501         {
 502                 /* IRQ for channels 0-5 */
 503                 .start  = gic_spi(42),
 504                 .end    = gic_spi(47),
 505                 .flags  = IORESOURCE_IRQ,
 506         },
 507 };
 508
 509 static struct platform_device dma0_device = {
 510         .name           = "sh-dma-engine",
 511         .id             = 0,
 512         .resource       = r8a7740_dmae0_resources,
 513         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 514         .dev            = {
 515                 .platform_data  = &dma_platform_data,
 516         },
 517 };
 518
 519 static struct platform_device dma1_device = {
 520         .name           = "sh-dma-engine",
 521         .id             = 1,
 522         .resource       = r8a7740_dmae1_resources,
 523         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 524         .dev            = {
 525                 .platform_data  = &dma_platform_data,
 526         },
 527 };
 528
 529 static struct platform_device dma2_device = {
 530         .name           = "sh-dma-engine",
 531         .id             = 2,
 532         .resource       = r8a7740_dmae2_resources,
 533         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 534         .dev            = {
 535                 .platform_data  = &dma_platform_data,
 536         },
 537 };
 538
 539 /* USB-DMAC */
 540 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 541         {
 542                 .offset = 0,
 543         }, {
 544                 .offset = 0x20,
 545         },
 546 };
 547
 548 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 549         {
 550                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 551                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 552         }, {
 553                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 554                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 555         },
 556 };
 557
 558 static struct sh_dmae_pdata usb_dma_platform_data = {
 559         .slave          = r8a7740_usb_dma_slaves,
 560         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 561         .channel        = r8a7740_usb_dma_channels,
 562         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 563         .ts_low_shift   = USBTS_LOW_SHIFT,
 564         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 565         .ts_high_shift  = USBTS_HI_SHIFT,
 566         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 567         .ts_shift       = dma_usbts_shift,
 568         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 569         .dmaor_init     = DMAOR_DME,
 570         .chcr_offset    = 0x14,
 571         .chcr_ie_bit    = 1 << 5,
 572         .dmaor_is_32bit = 1,
 573         .needs_tend_set = 1,
 574         .no_dmars       = 1,
 575         .slave_only     = 1,
 576 };
 577
 578 static struct resource r8a7740_usb_dma_resources[] = {
 579         {
 580                 /* Channel registers and DMAOR */
 581                 .start  = 0xe68a0020,
 582                 .end    = 0xe68a0064 - 1,
 583                 .flags  = IORESOURCE_MEM,
 584         },
 585         {
 586                 /* VCR/SWR/DMICR */
 587                 .start  = 0xe68a0000,
 588                 .end    = 0xe68a0014 - 1,
 589                 .flags  = IORESOURCE_MEM,
 590         },
 591         {
 592                 /* IRQ for channels */
 593                 .start  = gic_spi(49),
 594                 .end    = gic_spi(49),
 595                 .flags  = IORESOURCE_IRQ,
 596         },
 597 };
 598
 599 static struct platform_device usb_dma_device = {
 600         .name           = "sh-dma-engine",
 601         .id             = 3,
 602         .resource       = r8a7740_usb_dma_resources,
 603         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 604         .dev            = {
 605                 .platform_data  = &usb_dma_platform_data,
 606         },
 607 };
 608
 609 /* I2C */
 610 static struct resource i2c0_resources[] = {
 611         [0] = {
 612                 .name   = "IIC0",
 613                 .start  = 0xfff20000,
 614                 .end    = 0xfff20425 - 1,
 615                 .flags  = IORESOURCE_MEM,
 616         },
 617         [1] = {
 618                 .start  = gic_spi(201),
 619                 .end    = gic_spi(204),
 620                 .flags  = IORESOURCE_IRQ,
 621         },
 622 };
 623
 624 static struct resource i2c1_resources[] = {
 625         [0] = {
 626                 .name   = "IIC1",
 627                 .start  = 0xe6c20000,
 628                 .end    = 0xe6c20425 - 1,
 629                 .flags  = IORESOURCE_MEM,
 630         },
 631         [1] = {
 632                 .start  = gic_spi(70), /* IIC1_ALI1 */
 633                 .end    = gic_spi(73), /* IIC1_DTEI1 */
 634                 .flags  = IORESOURCE_IRQ,
 635         },
 636 };
 637
 638 static struct platform_device i2c0_device = {
 639         .name           = "i2c-sh_mobile",
 640         .id             = 0,
 641         .resource       = i2c0_resources,
 642         .num_resources  = ARRAY_SIZE(i2c0_resources),
 643 };
 644
 645 static struct platform_device i2c1_device = {
 646         .name           = "i2c-sh_mobile",
 647         .id             = 1,
 648         .resource       = i2c1_resources,
 649         .num_resources  = ARRAY_SIZE(i2c1_resources),
 650 };
 651
 652 static struct resource pmu_resources[] = {
 653         [0] = {
 654                 .start  = gic_spi(83),
 655                 .end    = gic_spi(83),
 656                 .flags  = IORESOURCE_IRQ,
 657         },
 658 };
 659
 660 static struct platform_device pmu_device = {
 661         .name   = "arm-pmu",
 662         .id     = -1,
 663         .num_resources = ARRAY_SIZE(pmu_resources),
 664         .resource = pmu_resources,
 665 };
 666
 667 static struct platform_device *r8a7740_late_devices[] __initdata = {
 668         &i2c0_device,
 669         &i2c1_device,
 670         &dma0_device,
 671         &dma1_device,
 672         &dma2_device,
 673         &usb_dma_device,
 674         &pmu_device,
 675 };
 676
 677 /*
 678  * r8a7740 chip has lasting errata on MERAM buffer.
 679  * this is work-around for it.
 680  * see
 681  *      "Media RAM (MERAM)" on r8a7740 documentation
 682  */
 683 #define MEBUFCNTR       0xFE950098
 684 void __init r8a7740_meram_workaround(void)
 685 {
 686         void __iomem *reg;
 687
 688         reg = ioremap_nocache(MEBUFCNTR, 4);
 689         if (reg) {
 690                 iowrite32(0x01600164, reg);
 691                 iounmap(reg);
 692         }
 693 }
 694
 695 #define ICCR    0x0004
 696 #define ICSTART 0x0070
 697
 698 #define i2c_read(reg, offset)           ioread8(reg + offset)
 699 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 700
 701 /*
 702  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 703  * this is work-around for it.
 704  */
 705 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 706 {
 707         struct resource *res;
 708         void __iomem *reg;
 709
 710         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 711         if (unlikely(!res)) {
 712                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 713                 return;
 714         }
 715
 716         reg = ioremap(res->start, resource_size(res));
 717         if (unlikely(!reg)) {
 718                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 719                 return;
 720         }
 721
 722         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 723         i2c_read(reg, ICCR); /* dummy read */
 724
 725         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 726         i2c_read(reg, ICSTART); /* dummy read */
 727
 728         udelay(10);
 729
 730         i2c_write(reg, ICCR, 0x01);
 731         i2c_write(reg, ICSTART, 0x00);
 732
 733         udelay(10);
 734
 735         i2c_write(reg, ICCR, 0x10);
 736         udelay(10);
 737         i2c_write(reg, ICCR, 0x00);
 738         udelay(10);
 739         i2c_write(reg, ICCR, 0x10);
 740         udelay(10);
 741
 742         iounmap(reg);
 743 }
 744
 745 void __init r8a7740_add_standard_devices(void)
 746 {
 747         /* I2C work-around */
 748         r8a7740_i2c_workaround(&i2c0_device);
 749         r8a7740_i2c_workaround(&i2c1_device);
 750
 751         r8a7740_init_pm_domains();
 752
 753         /* add devices */
 754         platform_add_devices(r8a7740_early_devices,
 755                             ARRAY_SIZE(r8a7740_early_devices));
 756         platform_add_devices(r8a7740_late_devices,
 757                              ARRAY_SIZE(r8a7740_late_devices));
 758
 759         /* add devices to PM domain  */
 760
 761         rmobile_add_device_to_domain("A3SP",    &scif0_device);
 762         rmobile_add_device_to_domain("A3SP",    &scif1_device);
 763         rmobile_add_device_to_domain("A3SP",    &scif2_device);
 764         rmobile_add_device_to_domain("A3SP",    &scif3_device);
 765         rmobile_add_device_to_domain("A3SP",    &scif4_device);
 766         rmobile_add_device_to_domain("A3SP",    &scif5_device);
 767         rmobile_add_device_to_domain("A3SP",    &scif6_device);
 768         rmobile_add_device_to_domain("A3SP",    &scif7_device);
 769         rmobile_add_device_to_domain("A3SP",    &scif8_device);
 770         rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 771 }
 772
 773 void __init r8a7740_add_early_devices(void)
 774 {
 775         early_platform_add_devices(r8a7740_early_devices,
 776                                    ARRAY_SIZE(r8a7740_early_devices));
 777
 778         /* setup early console here as well */
 779         shmobile_setup_console();
 780 }
 781
 782 #ifdef CONFIG_USE_OF
 783
 784 void __init r8a7740_add_standard_devices_dt(void)
 785 {
 786         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 787 }
 788
 789 void __init r8a7740_init_irq_of(void)
 790 {
 791         void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
 792         void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
 793         void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
 794
 795         irqchip_init();
 796
 797         /* route signals to GIC */
 798         iowrite32(0x0, pfc_inta_ctrl);
 799
 800         /*
 801          * To mask the shared interrupt to SPI 149 we must ensure to set
 802          * PRIO *and* MASK. Else we run into IRQ floods when registering
 803          * the intc_irqpin devices
 804          */
 805         iowrite32(0x0, intc_prio_base + 0x0);
 806         iowrite32(0x0, intc_prio_base + 0x4);
 807         iowrite32(0x0, intc_prio_base + 0x8);
 808         iowrite32(0x0, intc_prio_base + 0xc);
 809         iowrite8(0xff, intc_msk_base + 0x0);
 810         iowrite8(0xff, intc_msk_base + 0x4);
 811         iowrite8(0xff, intc_msk_base + 0x8);
 812         iowrite8(0xff, intc_msk_base + 0xc);
 813
 814         iounmap(intc_prio_base);
 815         iounmap(intc_msk_base);
 816         iounmap(pfc_inta_ctrl);
 817 }
 818
 819 static void __init r8a7740_generic_init(void)
 820 {
 821         r8a7740_clock_init(0);
 822         r8a7740_add_standard_devices_dt();
 823 }
 824
 825 static const char *r8a7740_boards_compat_dt[] __initdata = {
 826         "renesas,r8a7740",
 827         NULL,
 828 };
 829
 830 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
 831         .map_io         = r8a7740_map_io,
 832         .init_early     = shmobile_init_delay,
 833         .init_irq       = r8a7740_init_irq_of,
 834         .init_machine   = r8a7740_generic_init,
 835         .init_late      = shmobile_init_late,
 836         .dt_compat      = r8a7740_boards_compat_dt,
 837 MACHINE_END
 838
 839 #endif /* CONFIG_USE_OF */