arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/uio_driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_intc.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/pm_domain.h>
  35 #include <linux/dma-mapping.h>
  36 #include <mach/hardware.h>
  37 #include <mach/irqs.h>
  38 #include <mach/sh7372.h>
  39 #include <mach/common.h>
  40 #include <asm/mach/map.h>
  41 #include <asm/mach-types.h>
  42 #include <asm/mach/arch.h>
  43 #include <asm/mach/time.h>
  44
  45 static struct map_desc sh7372_io_desc[] __initdata = {
  46         /* create a 1:1 entity map for 0xe6xxxxxx
  47          * used by CPGA, INTC and PFC.
  48          */
  49         {
  50                 .virtual        = 0xe6000000,
  51                 .pfn            = __phys_to_pfn(0xe6000000),
  52                 .length         = 256 << 20,
  53                 .type           = MT_DEVICE_NONSHARED
  54         },
  55 };
  56
  57 void __init sh7372_map_io(void)
  58 {
  59         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  60
  61         /*
  62          * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
  63          * enough to allocate the frame buffer memory.
  64          */
  65         init_consistent_dma_size(12 << 20);
  66 }
  67
  68 /* SCIFA0 */
  69 static struct plat_sci_port scif0_platform_data = {
  70         .mapbase        = 0xe6c40000,
  71         .flags          = UPF_BOOT_AUTOCONF,
  72         .scscr          = SCSCR_RE | SCSCR_TE,
  73         .scbrr_algo_id  = SCBRR_ALGO_4,
  74         .type           = PORT_SCIFA,
  75         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  76                             evt2irq(0x0c00), evt2irq(0x0c00) },
  77 };
  78
  79 static struct platform_device scif0_device = {
  80         .name           = "sh-sci",
  81         .id             = 0,
  82         .dev            = {
  83                 .platform_data  = &scif0_platform_data,
  84         },
  85 };
  86
  87 /* SCIFA1 */
  88 static struct plat_sci_port scif1_platform_data = {
  89         .mapbase        = 0xe6c50000,
  90         .flags          = UPF_BOOT_AUTOCONF,
  91         .scscr          = SCSCR_RE | SCSCR_TE,
  92         .scbrr_algo_id  = SCBRR_ALGO_4,
  93         .type           = PORT_SCIFA,
  94         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  95                             evt2irq(0x0c20), evt2irq(0x0c20) },
  96 };
  97
  98 static struct platform_device scif1_device = {
  99         .name           = "sh-sci",
 100         .id             = 1,
 101         .dev            = {
 102                 .platform_data  = &scif1_platform_data,
 103         },
 104 };
 105
 106 /* SCIFA2 */
 107 static struct plat_sci_port scif2_platform_data = {
 108         .mapbase        = 0xe6c60000,
 109         .flags          = UPF_BOOT_AUTOCONF,
 110         .scscr          = SCSCR_RE | SCSCR_TE,
 111         .scbrr_algo_id  = SCBRR_ALGO_4,
 112         .type           = PORT_SCIFA,
 113         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
 114                             evt2irq(0x0c40), evt2irq(0x0c40) },
 115 };
 116
 117 static struct platform_device scif2_device = {
 118         .name           = "sh-sci",
 119         .id             = 2,
 120         .dev            = {
 121                 .platform_data  = &scif2_platform_data,
 122         },
 123 };
 124
 125 /* SCIFA3 */
 126 static struct plat_sci_port scif3_platform_data = {
 127         .mapbase        = 0xe6c70000,
 128         .flags          = UPF_BOOT_AUTOCONF,
 129         .scscr          = SCSCR_RE | SCSCR_TE,
 130         .scbrr_algo_id  = SCBRR_ALGO_4,
 131         .type           = PORT_SCIFA,
 132         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 133                             evt2irq(0x0c60), evt2irq(0x0c60) },
 134 };
 135
 136 static struct platform_device scif3_device = {
 137         .name           = "sh-sci",
 138         .id             = 3,
 139         .dev            = {
 140                 .platform_data  = &scif3_platform_data,
 141         },
 142 };
 143
 144 /* SCIFA4 */
 145 static struct plat_sci_port scif4_platform_data = {
 146         .mapbase        = 0xe6c80000,
 147         .flags          = UPF_BOOT_AUTOCONF,
 148         .scscr          = SCSCR_RE | SCSCR_TE,
 149         .scbrr_algo_id  = SCBRR_ALGO_4,
 150         .type           = PORT_SCIFA,
 151         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 152                             evt2irq(0x0d20), evt2irq(0x0d20) },
 153 };
 154
 155 static struct platform_device scif4_device = {
 156         .name           = "sh-sci",
 157         .id             = 4,
 158         .dev            = {
 159                 .platform_data  = &scif4_platform_data,
 160         },
 161 };
 162
 163 /* SCIFA5 */
 164 static struct plat_sci_port scif5_platform_data = {
 165         .mapbase        = 0xe6cb0000,
 166         .flags          = UPF_BOOT_AUTOCONF,
 167         .scscr          = SCSCR_RE | SCSCR_TE,
 168         .scbrr_algo_id  = SCBRR_ALGO_4,
 169         .type           = PORT_SCIFA,
 170         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 171                             evt2irq(0x0d40), evt2irq(0x0d40) },
 172 };
 173
 174 static struct platform_device scif5_device = {
 175         .name           = "sh-sci",
 176         .id             = 5,
 177         .dev            = {
 178                 .platform_data  = &scif5_platform_data,
 179         },
 180 };
 181
 182 /* SCIFB */
 183 static struct plat_sci_port scif6_platform_data = {
 184         .mapbase        = 0xe6c30000,
 185         .flags          = UPF_BOOT_AUTOCONF,
 186         .scscr          = SCSCR_RE | SCSCR_TE,
 187         .scbrr_algo_id  = SCBRR_ALGO_4,
 188         .type           = PORT_SCIFB,
 189         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 190                             evt2irq(0x0d60), evt2irq(0x0d60) },
 191 };
 192
 193 static struct platform_device scif6_device = {
 194         .name           = "sh-sci",
 195         .id             = 6,
 196         .dev            = {
 197                 .platform_data  = &scif6_platform_data,
 198         },
 199 };
 200
 201 /* CMT */
 202 static struct sh_timer_config cmt2_platform_data = {
 203         .name = "CMT2",
 204         .channel_offset = 0x40,
 205         .timer_bit = 5,
 206         .clockevent_rating = 125,
 207         .clocksource_rating = 125,
 208 };
 209
 210 static struct resource cmt2_resources[] = {
 211         [0] = {
 212                 .name   = "CMT2",
 213                 .start  = 0xe6130040,
 214                 .end    = 0xe613004b,
 215                 .flags  = IORESOURCE_MEM,
 216         },
 217         [1] = {
 218                 .start  = evt2irq(0x0b80), /* CMT2 */
 219                 .flags  = IORESOURCE_IRQ,
 220         },
 221 };
 222
 223 static struct platform_device cmt2_device = {
 224         .name           = "sh_cmt",
 225         .id             = 2,
 226         .dev = {
 227                 .platform_data  = &cmt2_platform_data,
 228         },
 229         .resource       = cmt2_resources,
 230         .num_resources  = ARRAY_SIZE(cmt2_resources),
 231 };
 232
 233 /* TMU */
 234 static struct sh_timer_config tmu00_platform_data = {
 235         .name = "TMU00",
 236         .channel_offset = 0x4,
 237         .timer_bit = 0,
 238         .clockevent_rating = 200,
 239 };
 240
 241 static struct resource tmu00_resources[] = {
 242         [0] = {
 243                 .name   = "TMU00",
 244                 .start  = 0xfff60008,
 245                 .end    = 0xfff60013,
 246                 .flags  = IORESOURCE_MEM,
 247         },
 248         [1] = {
 249                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 250                 .flags  = IORESOURCE_IRQ,
 251         },
 252 };
 253
 254 static struct platform_device tmu00_device = {
 255         .name           = "sh_tmu",
 256         .id             = 0,
 257         .dev = {
 258                 .platform_data  = &tmu00_platform_data,
 259         },
 260         .resource       = tmu00_resources,
 261         .num_resources  = ARRAY_SIZE(tmu00_resources),
 262 };
 263
 264 static struct sh_timer_config tmu01_platform_data = {
 265         .name = "TMU01",
 266         .channel_offset = 0x10,
 267         .timer_bit = 1,
 268         .clocksource_rating = 200,
 269 };
 270
 271 static struct resource tmu01_resources[] = {
 272         [0] = {
 273                 .name   = "TMU01",
 274                 .start  = 0xfff60014,
 275                 .end    = 0xfff6001f,
 276                 .flags  = IORESOURCE_MEM,
 277         },
 278         [1] = {
 279                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 280                 .flags  = IORESOURCE_IRQ,
 281         },
 282 };
 283
 284 static struct platform_device tmu01_device = {
 285         .name           = "sh_tmu",
 286         .id             = 1,
 287         .dev = {
 288                 .platform_data  = &tmu01_platform_data,
 289         },
 290         .resource       = tmu01_resources,
 291         .num_resources  = ARRAY_SIZE(tmu01_resources),
 292 };
 293
 294 /* I2C */
 295 static struct resource iic0_resources[] = {
 296         [0] = {
 297                 .name   = "IIC0",
 298                 .start  = 0xFFF20000,
 299                 .end    = 0xFFF20425 - 1,
 300                 .flags  = IORESOURCE_MEM,
 301         },
 302         [1] = {
 303                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 304                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 305                 .flags  = IORESOURCE_IRQ,
 306         },
 307 };
 308
 309 static struct platform_device iic0_device = {
 310         .name           = "i2c-sh_mobile",
 311         .id             = 0, /* "i2c0" clock */
 312         .num_resources  = ARRAY_SIZE(iic0_resources),
 313         .resource       = iic0_resources,
 314 };
 315
 316 static struct resource iic1_resources[] = {
 317         [0] = {
 318                 .name   = "IIC1",
 319                 .start  = 0xE6C20000,
 320                 .end    = 0xE6C20425 - 1,
 321                 .flags  = IORESOURCE_MEM,
 322         },
 323         [1] = {
 324                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 325                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 326                 .flags  = IORESOURCE_IRQ,
 327         },
 328 };
 329
 330 static struct platform_device iic1_device = {
 331         .name           = "i2c-sh_mobile",
 332         .id             = 1, /* "i2c1" clock */
 333         .num_resources  = ARRAY_SIZE(iic1_resources),
 334         .resource       = iic1_resources,
 335 };
 336
 337 /* DMA */
 338 /* Transmit sizes and respective CHCR register values */
 339 enum {
 340         XMIT_SZ_8BIT            = 0,
 341         XMIT_SZ_16BIT           = 1,
 342         XMIT_SZ_32BIT           = 2,
 343         XMIT_SZ_64BIT           = 7,
 344         XMIT_SZ_128BIT          = 3,
 345         XMIT_SZ_256BIT          = 4,
 346         XMIT_SZ_512BIT          = 5,
 347 };
 348
 349 /* log2(size / 8) - used to calculate number of transfers */
 350 #define TS_SHIFT {                      \
 351         [XMIT_SZ_8BIT]          = 0,    \
 352         [XMIT_SZ_16BIT]         = 1,    \
 353         [XMIT_SZ_32BIT]         = 2,    \
 354         [XMIT_SZ_64BIT]         = 3,    \
 355         [XMIT_SZ_128BIT]        = 4,    \
 356         [XMIT_SZ_256BIT]        = 5,    \
 357         [XMIT_SZ_512BIT]        = 6,    \
 358 }
 359
 360 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
 361                          (((i) & 0xc) << (20 - 2)))
 362
 363 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 364         {
 365                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 366                 .addr           = 0xe6c40020,
 367                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 368                 .mid_rid        = 0x21,
 369         }, {
 370                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 371                 .addr           = 0xe6c40024,
 372                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 373                 .mid_rid        = 0x22,
 374         }, {
 375                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 376                 .addr           = 0xe6c50020,
 377                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 378                 .mid_rid        = 0x25,
 379         }, {
 380                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 381                 .addr           = 0xe6c50024,
 382                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 383                 .mid_rid        = 0x26,
 384         }, {
 385                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 386                 .addr           = 0xe6c60020,
 387                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 388                 .mid_rid        = 0x29,
 389         }, {
 390                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 391                 .addr           = 0xe6c60024,
 392                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 393                 .mid_rid        = 0x2a,
 394         }, {
 395                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 396                 .addr           = 0xe6c70020,
 397                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 398                 .mid_rid        = 0x2d,
 399         }, {
 400                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 401                 .addr           = 0xe6c70024,
 402                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 403                 .mid_rid        = 0x2e,
 404         }, {
 405                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 406                 .addr           = 0xe6c80020,
 407                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 408                 .mid_rid        = 0x39,
 409         }, {
 410                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 411                 .addr           = 0xe6c80024,
 412                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 413                 .mid_rid        = 0x3a,
 414         }, {
 415                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 416                 .addr           = 0xe6cb0020,
 417                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 418                 .mid_rid        = 0x35,
 419         }, {
 420                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 421                 .addr           = 0xe6cb0024,
 422                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 423                 .mid_rid        = 0x36,
 424         }, {
 425                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 426                 .addr           = 0xe6c30040,
 427                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 428                 .mid_rid        = 0x3d,
 429         }, {
 430                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 431                 .addr           = 0xe6c30060,
 432                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 433                 .mid_rid        = 0x3e,
 434         }, {
 435                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 436                 .addr           = 0xe6850030,
 437                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 438                 .mid_rid        = 0xc1,
 439         }, {
 440                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 441                 .addr           = 0xe6850030,
 442                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 443                 .mid_rid        = 0xc2,
 444         }, {
 445                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 446                 .addr           = 0xe6860030,
 447                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 448                 .mid_rid        = 0xc9,
 449         }, {
 450                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 451                 .addr           = 0xe6860030,
 452                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 453                 .mid_rid        = 0xca,
 454         }, {
 455                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 456                 .addr           = 0xe6870030,
 457                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 458                 .mid_rid        = 0xcd,
 459         }, {
 460                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 461                 .addr           = 0xe6870030,
 462                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 463                 .mid_rid        = 0xce,
 464         }, {
 465                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 466                 .addr           = 0xfe1f0024,
 467                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 468                 .mid_rid        = 0xb1,
 469         }, {
 470                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 471                 .addr           = 0xfe1f0020,
 472                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 473                 .mid_rid        = 0xb2,
 474         }, {
 475                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 476                 .addr           = 0xe6bd0034,
 477                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 478                 .mid_rid        = 0xd1,
 479         }, {
 480                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 481                 .addr           = 0xe6bd0034,
 482                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 483                 .mid_rid        = 0xd2,
 484         },
 485 };
 486
 487 #define SH7372_CHCLR 0x220
 488
 489 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 490         {
 491                 .offset = 0,
 492                 .dmars = 0,
 493                 .dmars_bit = 0,
 494                 .chclr_offset = SH7372_CHCLR + 0,
 495         }, {
 496                 .offset = 0x10,
 497                 .dmars = 0,
 498                 .dmars_bit = 8,
 499                 .chclr_offset = SH7372_CHCLR + 0x10,
 500         }, {
 501                 .offset = 0x20,
 502                 .dmars = 4,
 503                 .dmars_bit = 0,
 504                 .chclr_offset = SH7372_CHCLR + 0x20,
 505         }, {
 506                 .offset = 0x30,
 507                 .dmars = 4,
 508                 .dmars_bit = 8,
 509                 .chclr_offset = SH7372_CHCLR + 0x30,
 510         }, {
 511                 .offset = 0x50,
 512                 .dmars = 8,
 513                 .dmars_bit = 0,
 514                 .chclr_offset = SH7372_CHCLR + 0x50,
 515         }, {
 516                 .offset = 0x60,
 517                 .dmars = 8,
 518                 .dmars_bit = 8,
 519                 .chclr_offset = SH7372_CHCLR + 0x60,
 520         }
 521 };
 522
 523 static const unsigned int ts_shift[] = TS_SHIFT;
 524
 525 static struct sh_dmae_pdata dma_platform_data = {
 526         .slave          = sh7372_dmae_slaves,
 527         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 528         .channel        = sh7372_dmae_channels,
 529         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 530         .ts_low_shift   = 3,
 531         .ts_low_mask    = 0x18,
 532         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 533         .ts_high_mask   = 0x00300000,
 534         .ts_shift       = ts_shift,
 535         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 536         .dmaor_init     = DMAOR_DME,
 537         .chclr_present  = 1,
 538 };
 539
 540 /* Resource order important! */
 541 static struct resource sh7372_dmae0_resources[] = {
 542         {
 543                 /* Channel registers and DMAOR */
 544                 .start  = 0xfe008020,
 545                 .end    = 0xfe00828f,
 546                 .flags  = IORESOURCE_MEM,
 547         },
 548         {
 549                 /* DMARSx */
 550                 .start  = 0xfe009000,
 551                 .end    = 0xfe00900b,
 552                 .flags  = IORESOURCE_MEM,
 553         },
 554         {
 555                 .name   = "error_irq",
 556                 .start  = evt2irq(0x20c0),
 557                 .end    = evt2irq(0x20c0),
 558                 .flags  = IORESOURCE_IRQ,
 559         },
 560         {
 561                 /* IRQ for channels 0-5 */
 562                 .start  = evt2irq(0x2000),
 563                 .end    = evt2irq(0x20a0),
 564                 .flags  = IORESOURCE_IRQ,
 565         },
 566 };
 567
 568 /* Resource order important! */
 569 static struct resource sh7372_dmae1_resources[] = {
 570         {
 571                 /* Channel registers and DMAOR */
 572                 .start  = 0xfe018020,
 573                 .end    = 0xfe01828f,
 574                 .flags  = IORESOURCE_MEM,
 575         },
 576         {
 577                 /* DMARSx */
 578                 .start  = 0xfe019000,
 579                 .end    = 0xfe01900b,
 580                 .flags  = IORESOURCE_MEM,
 581         },
 582         {
 583                 .name   = "error_irq",
 584                 .start  = evt2irq(0x21c0),
 585                 .end    = evt2irq(0x21c0),
 586                 .flags  = IORESOURCE_IRQ,
 587         },
 588         {
 589                 /* IRQ for channels 0-5 */
 590                 .start  = evt2irq(0x2100),
 591                 .end    = evt2irq(0x21a0),
 592                 .flags  = IORESOURCE_IRQ,
 593         },
 594 };
 595
 596 /* Resource order important! */
 597 static struct resource sh7372_dmae2_resources[] = {
 598         {
 599                 /* Channel registers and DMAOR */
 600                 .start  = 0xfe028020,
 601                 .end    = 0xfe02828f,
 602                 .flags  = IORESOURCE_MEM,
 603         },
 604         {
 605                 /* DMARSx */
 606                 .start  = 0xfe029000,
 607                 .end    = 0xfe02900b,
 608                 .flags  = IORESOURCE_MEM,
 609         },
 610         {
 611                 .name   = "error_irq",
 612                 .start  = evt2irq(0x22c0),
 613                 .end    = evt2irq(0x22c0),
 614                 .flags  = IORESOURCE_IRQ,
 615         },
 616         {
 617                 /* IRQ for channels 0-5 */
 618                 .start  = evt2irq(0x2200),
 619                 .end    = evt2irq(0x22a0),
 620                 .flags  = IORESOURCE_IRQ,
 621         },
 622 };
 623
 624 static struct platform_device dma0_device = {
 625         .name           = "sh-dma-engine",
 626         .id             = 0,
 627         .resource       = sh7372_dmae0_resources,
 628         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 629         .dev            = {
 630                 .platform_data  = &dma_platform_data,
 631         },
 632 };
 633
 634 static struct platform_device dma1_device = {
 635         .name           = "sh-dma-engine",
 636         .id             = 1,
 637         .resource       = sh7372_dmae1_resources,
 638         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 639         .dev            = {
 640                 .platform_data  = &dma_platform_data,
 641         },
 642 };
 643
 644 static struct platform_device dma2_device = {
 645         .name           = "sh-dma-engine",
 646         .id             = 2,
 647         .resource       = sh7372_dmae2_resources,
 648         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 649         .dev            = {
 650                 .platform_data  = &dma_platform_data,
 651         },
 652 };
 653
 654 /*
 655  * USB-DMAC
 656  */
 657
 658 unsigned int usbts_shift[] = {3, 4, 5};
 659
 660 enum {
 661         XMIT_SZ_8BYTE           = 0,
 662         XMIT_SZ_16BYTE          = 1,
 663         XMIT_SZ_32BYTE          = 2,
 664 };
 665
 666 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
 667
 668 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 669         {
 670                 .offset = 0,
 671         }, {
 672                 .offset = 0x20,
 673         },
 674 };
 675
 676 /* USB DMAC0 */
 677 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 678         {
 679                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 680                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 681         }, {
 682                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 683                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 684         },
 685 };
 686
 687 static struct sh_dmae_pdata usb_dma0_platform_data = {
 688         .slave          = sh7372_usb_dmae0_slaves,
 689         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 690         .channel        = sh7372_usb_dmae_channels,
 691         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 692         .ts_low_shift   = 6,
 693         .ts_low_mask    = 0xc0,
 694         .ts_high_shift  = 0,
 695         .ts_high_mask   = 0,
 696         .ts_shift       = usbts_shift,
 697         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
 698         .dmaor_init     = DMAOR_DME,
 699         .chcr_offset    = 0x14,
 700         .chcr_ie_bit    = 1 << 5,
 701         .dmaor_is_32bit = 1,
 702         .needs_tend_set = 1,
 703         .no_dmars       = 1,
 704         .slave_only     = 1,
 705 };
 706
 707 static struct resource sh7372_usb_dmae0_resources[] = {
 708         {
 709                 /* Channel registers and DMAOR */
 710                 .start  = 0xe68a0020,
 711                 .end    = 0xe68a0064 - 1,
 712                 .flags  = IORESOURCE_MEM,
 713         },
 714         {
 715                 /* VCR/SWR/DMICR */
 716                 .start  = 0xe68a0000,
 717                 .end    = 0xe68a0014 - 1,
 718                 .flags  = IORESOURCE_MEM,
 719         },
 720         {
 721                 /* IRQ for channels */
 722                 .start  = evt2irq(0x0a00),
 723                 .end    = evt2irq(0x0a00),
 724                 .flags  = IORESOURCE_IRQ,
 725         },
 726 };
 727
 728 static struct platform_device usb_dma0_device = {
 729         .name           = "sh-dma-engine",
 730         .id             = 3,
 731         .resource       = sh7372_usb_dmae0_resources,
 732         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 733         .dev            = {
 734                 .platform_data  = &usb_dma0_platform_data,
 735         },
 736 };
 737
 738 /* USB DMAC1 */
 739 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 740         {
 741                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 742                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 743         }, {
 744                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 745                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 746         },
 747 };
 748
 749 static struct sh_dmae_pdata usb_dma1_platform_data = {
 750         .slave          = sh7372_usb_dmae1_slaves,
 751         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 752         .channel        = sh7372_usb_dmae_channels,
 753         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 754         .ts_low_shift   = 6,
 755         .ts_low_mask    = 0xc0,
 756         .ts_high_shift  = 0,
 757         .ts_high_mask   = 0,
 758         .ts_shift       = usbts_shift,
 759         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
 760         .dmaor_init     = DMAOR_DME,
 761         .chcr_offset    = 0x14,
 762         .chcr_ie_bit    = 1 << 5,
 763         .dmaor_is_32bit = 1,
 764         .needs_tend_set = 1,
 765         .no_dmars       = 1,
 766         .slave_only     = 1,
 767 };
 768
 769 static struct resource sh7372_usb_dmae1_resources[] = {
 770         {
 771                 /* Channel registers and DMAOR */
 772                 .start  = 0xe68c0020,
 773                 .end    = 0xe68c0064 - 1,
 774                 .flags  = IORESOURCE_MEM,
 775         },
 776         {
 777                 /* VCR/SWR/DMICR */
 778                 .start  = 0xe68c0000,
 779                 .end    = 0xe68c0014 - 1,
 780                 .flags  = IORESOURCE_MEM,
 781         },
 782         {
 783                 /* IRQ for channels */
 784                 .start  = evt2irq(0x1d00),
 785                 .end    = evt2irq(0x1d00),
 786                 .flags  = IORESOURCE_IRQ,
 787         },
 788 };
 789
 790 static struct platform_device usb_dma1_device = {
 791         .name           = "sh-dma-engine",
 792         .id             = 4,
 793         .resource       = sh7372_usb_dmae1_resources,
 794         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 795         .dev            = {
 796                 .platform_data  = &usb_dma1_platform_data,
 797         },
 798 };
 799
 800 /* VPU */
 801 static struct uio_info vpu_platform_data = {
 802         .name = "VPU5HG",
 803         .version = "0",
 804         .irq = intcs_evt2irq(0x980),
 805 };
 806
 807 static struct resource vpu_resources[] = {
 808         [0] = {
 809                 .name   = "VPU",
 810                 .start  = 0xfe900000,
 811                 .end    = 0xfe900157,
 812                 .flags  = IORESOURCE_MEM,
 813         },
 814 };
 815
 816 static struct platform_device vpu_device = {
 817         .name           = "uio_pdrv_genirq",
 818         .id             = 0,
 819         .dev = {
 820                 .platform_data  = &vpu_platform_data,
 821         },
 822         .resource       = vpu_resources,
 823         .num_resources  = ARRAY_SIZE(vpu_resources),
 824 };
 825
 826 /* VEU0 */
 827 static struct uio_info veu0_platform_data = {
 828         .name = "VEU0",
 829         .version = "0",
 830         .irq = intcs_evt2irq(0x700),
 831 };
 832
 833 static struct resource veu0_resources[] = {
 834         [0] = {
 835                 .name   = "VEU0",
 836                 .start  = 0xfe920000,
 837                 .end    = 0xfe9200cb,
 838                 .flags  = IORESOURCE_MEM,
 839         },
 840 };
 841
 842 static struct platform_device veu0_device = {
 843         .name           = "uio_pdrv_genirq",
 844         .id             = 1,
 845         .dev = {
 846                 .platform_data  = &veu0_platform_data,
 847         },
 848         .resource       = veu0_resources,
 849         .num_resources  = ARRAY_SIZE(veu0_resources),
 850 };
 851
 852 /* VEU1 */
 853 static struct uio_info veu1_platform_data = {
 854         .name = "VEU1",
 855         .version = "0",
 856         .irq = intcs_evt2irq(0x720),
 857 };
 858
 859 static struct resource veu1_resources[] = {
 860         [0] = {
 861                 .name   = "VEU1",
 862                 .start  = 0xfe924000,
 863                 .end    = 0xfe9240cb,
 864                 .flags  = IORESOURCE_MEM,
 865         },
 866 };
 867
 868 static struct platform_device veu1_device = {
 869         .name           = "uio_pdrv_genirq",
 870         .id             = 2,
 871         .dev = {
 872                 .platform_data  = &veu1_platform_data,
 873         },
 874         .resource       = veu1_resources,
 875         .num_resources  = ARRAY_SIZE(veu1_resources),
 876 };
 877
 878 /* VEU2 */
 879 static struct uio_info veu2_platform_data = {
 880         .name = "VEU2",
 881         .version = "0",
 882         .irq = intcs_evt2irq(0x740),
 883 };
 884
 885 static struct resource veu2_resources[] = {
 886         [0] = {
 887                 .name   = "VEU2",
 888                 .start  = 0xfe928000,
 889                 .end    = 0xfe928307,
 890                 .flags  = IORESOURCE_MEM,
 891         },
 892 };
 893
 894 static struct platform_device veu2_device = {
 895         .name           = "uio_pdrv_genirq",
 896         .id             = 3,
 897         .dev = {
 898                 .platform_data  = &veu2_platform_data,
 899         },
 900         .resource       = veu2_resources,
 901         .num_resources  = ARRAY_SIZE(veu2_resources),
 902 };
 903
 904 /* VEU3 */
 905 static struct uio_info veu3_platform_data = {
 906         .name = "VEU3",
 907         .version = "0",
 908         .irq = intcs_evt2irq(0x760),
 909 };
 910
 911 static struct resource veu3_resources[] = {
 912         [0] = {
 913                 .name   = "VEU3",
 914                 .start  = 0xfe92c000,
 915                 .end    = 0xfe92c307,
 916                 .flags  = IORESOURCE_MEM,
 917         },
 918 };
 919
 920 static struct platform_device veu3_device = {
 921         .name           = "uio_pdrv_genirq",
 922         .id             = 4,
 923         .dev = {
 924                 .platform_data  = &veu3_platform_data,
 925         },
 926         .resource       = veu3_resources,
 927         .num_resources  = ARRAY_SIZE(veu3_resources),
 928 };
 929
 930 /* JPU */
 931 static struct uio_info jpu_platform_data = {
 932         .name = "JPU",
 933         .version = "0",
 934         .irq = intcs_evt2irq(0x560),
 935 };
 936
 937 static struct resource jpu_resources[] = {
 938         [0] = {
 939                 .name   = "JPU",
 940                 .start  = 0xfe980000,
 941                 .end    = 0xfe9902d3,
 942                 .flags  = IORESOURCE_MEM,
 943         },
 944 };
 945
 946 static struct platform_device jpu_device = {
 947         .name           = "uio_pdrv_genirq",
 948         .id             = 5,
 949         .dev = {
 950                 .platform_data  = &jpu_platform_data,
 951         },
 952         .resource       = jpu_resources,
 953         .num_resources  = ARRAY_SIZE(jpu_resources),
 954 };
 955
 956 /* SPU2DSP0 */
 957 static struct uio_info spu0_platform_data = {
 958         .name = "SPU2DSP0",
 959         .version = "0",
 960         .irq = evt2irq(0x1800),
 961 };
 962
 963 static struct resource spu0_resources[] = {
 964         [0] = {
 965                 .name   = "SPU2DSP0",
 966                 .start  = 0xfe200000,
 967                 .end    = 0xfe2fffff,
 968                 .flags  = IORESOURCE_MEM,
 969         },
 970 };
 971
 972 static struct platform_device spu0_device = {
 973         .name           = "uio_pdrv_genirq",
 974         .id             = 6,
 975         .dev = {
 976                 .platform_data  = &spu0_platform_data,
 977         },
 978         .resource       = spu0_resources,
 979         .num_resources  = ARRAY_SIZE(spu0_resources),
 980 };
 981
 982 /* SPU2DSP1 */
 983 static struct uio_info spu1_platform_data = {
 984         .name = "SPU2DSP1",
 985         .version = "0",
 986         .irq = evt2irq(0x1820),
 987 };
 988
 989 static struct resource spu1_resources[] = {
 990         [0] = {
 991                 .name   = "SPU2DSP1",
 992                 .start  = 0xfe300000,
 993                 .end    = 0xfe3fffff,
 994                 .flags  = IORESOURCE_MEM,
 995         },
 996 };
 997
 998 static struct platform_device spu1_device = {
 999         .name           = "uio_pdrv_genirq",
1000         .id             = 7,
1001         .dev = {
1002                 .platform_data  = &spu1_platform_data,
1003         },
1004         .resource       = spu1_resources,
1005         .num_resources  = ARRAY_SIZE(spu1_resources),
1006 };
1007
1008 static struct platform_device *sh7372_early_devices[] __initdata = {
1009         &scif0_device,
1010         &scif1_device,
1011         &scif2_device,
1012         &scif3_device,
1013         &scif4_device,
1014         &scif5_device,
1015         &scif6_device,
1016         &cmt2_device,
1017         &tmu00_device,
1018         &tmu01_device,
1019 };
1020
1021 static struct platform_device *sh7372_late_devices[] __initdata = {
1022         &iic0_device,
1023         &iic1_device,
1024         &dma0_device,
1025         &dma1_device,
1026         &dma2_device,
1027         &usb_dma0_device,
1028         &usb_dma1_device,
1029         &vpu_device,
1030         &veu0_device,
1031         &veu1_device,
1032         &veu2_device,
1033         &veu3_device,
1034         &jpu_device,
1035         &spu0_device,
1036         &spu1_device,
1037 };
1038
1039 void __init sh7372_add_standard_devices(void)
1040 {
1041         sh7372_init_pm_domain(&sh7372_a4lc);
1042         sh7372_init_pm_domain(&sh7372_a4mp);
1043         sh7372_init_pm_domain(&sh7372_d4);
1044         sh7372_init_pm_domain(&sh7372_a4r);
1045         sh7372_init_pm_domain(&sh7372_a3rv);
1046         sh7372_init_pm_domain(&sh7372_a3ri);
1047         sh7372_init_pm_domain(&sh7372_a4s);
1048         sh7372_init_pm_domain(&sh7372_a3sp);
1049         sh7372_init_pm_domain(&sh7372_a3sg);
1050
1051         sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1052         sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1053
1054         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1055         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1056
1057         platform_add_devices(sh7372_early_devices,
1058                             ARRAY_SIZE(sh7372_early_devices));
1059
1060         platform_add_devices(sh7372_late_devices,
1061                             ARRAY_SIZE(sh7372_late_devices));
1062
1063         sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1064         sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1065         sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1066         sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1067         sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1068         sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1069         sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1070         sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1071         sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1072         sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1073         sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1074         sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1075         sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1076         sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1077         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1078         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1079         sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1080         sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1081         sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1082         sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1083         sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1084         sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1085         sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
1086         sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
1087 }
1088
1089 static void __init sh7372_earlytimer_init(void)
1090 {
1091         sh7372_clock_init();
1092         shmobile_earlytimer_init();
1093 }
1094
1095 void __init sh7372_add_early_devices(void)
1096 {
1097         early_platform_add_devices(sh7372_early_devices,
1098                                    ARRAY_SIZE(sh7372_early_devices));
1099
1100         /* setup early console here as well */
1101         shmobile_setup_console();
1102
1103         /* override timer setup with soc-specific code */
1104         shmobile_timer.init = sh7372_earlytimer_init;
1105 }
1106
1107 #ifdef CONFIG_USE_OF
1108
1109 void __init sh7372_add_early_devices_dt(void)
1110 {
1111         shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1112
1113         early_platform_add_devices(sh7372_early_devices,
1114                                    ARRAY_SIZE(sh7372_early_devices));
1115
1116         /* setup early console here as well */
1117         shmobile_setup_console();
1118 }
1119
1120 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1121         { }
1122 };
1123
1124 void __init sh7372_add_standard_devices_dt(void)
1125 {
1126         /* clocks are setup late during boot in the case of DT */
1127         sh7372_clock_init();
1128
1129         platform_add_devices(sh7372_early_devices,
1130                             ARRAY_SIZE(sh7372_early_devices));
1131
1132         of_platform_populate(NULL, of_default_bus_match_table,
1133                              sh7372_auxdata_lookup, NULL);
1134 }
1135
1136 static const char *sh7372_boards_compat_dt[] __initdata = {
1137         "renesas,sh7372",
1138         NULL,
1139 };
1140
1141 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1142         .map_io         = sh7372_map_io,
1143         .init_early     = sh7372_add_early_devices_dt,
1144         .nr_irqs        = NR_IRQS_LEGACY,
1145         .init_irq       = sh7372_init_irq,
1146         .handle_irq     = shmobile_handle_irq_intc,
1147         .init_machine   = sh7372_add_standard_devices_dt,
1148         .timer          = &shmobile_timer,
1149         .dt_compat      = sh7372_boards_compat_dt,
1150 MACHINE_END
1151
1152 #endif /* CONFIG_USE_OF */