arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_intc.h>
  33 #include <linux/sh_timer.h>
  34 #include <mach/dma-register.h>
  35 #include <mach/hardware.h>
  36 #include <mach/irqs.h>
  37 #include <mach/sh73a0.h>
  38 #include <mach/common.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/mach/map.h>
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/time.h>
  43
  44 static struct map_desc sh73a0_io_desc[] __initdata = {
  45         /* create a 1:1 entity map for 0xe6xxxxxx
  46          * used by CPGA, INTC and PFC.
  47          */
  48         {
  49                 .virtual        = 0xe6000000,
  50                 .pfn            = __phys_to_pfn(0xe6000000),
  51                 .length         = 256 << 20,
  52                 .type           = MT_DEVICE_NONSHARED
  53         },
  54 };
  55
  56 void __init sh73a0_map_io(void)
  57 {
  58         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  59 }
  60
  61 static struct resource sh73a0_pfc_resources[] = {
  62         [0] = {
  63                 .start  = 0xe6050000,
  64                 .end    = 0xe6057fff,
  65                 .flags  = IORESOURCE_MEM,
  66         },
  67         [1] = {
  68                 .start  = 0xe605801c,
  69                 .end    = 0xe6058027,
  70                 .flags  = IORESOURCE_MEM,
  71         }
  72 };
  73
  74 static struct platform_device sh73a0_pfc_device = {
  75         .name           = "pfc-sh73a0",
  76         .id             = -1,
  77         .resource       = sh73a0_pfc_resources,
  78         .num_resources  = ARRAY_SIZE(sh73a0_pfc_resources),
  79 };
  80
  81 void __init sh73a0_pinmux_init(void)
  82 {
  83         platform_device_register(&sh73a0_pfc_device);
  84 }
  85
  86 static struct plat_sci_port scif0_platform_data = {
  87         .mapbase        = 0xe6c40000,
  88         .flags          = UPF_BOOT_AUTOCONF,
  89         .scscr          = SCSCR_RE | SCSCR_TE,
  90         .scbrr_algo_id  = SCBRR_ALGO_4,
  91         .type           = PORT_SCIFA,
  92         .irqs           = { gic_spi(72), gic_spi(72),
  93                             gic_spi(72), gic_spi(72) },
  94 };
  95
  96 static struct platform_device scif0_device = {
  97         .name           = "sh-sci",
  98         .id             = 0,
  99         .dev            = {
 100                 .platform_data  = &scif0_platform_data,
 101         },
 102 };
 103
 104 static struct plat_sci_port scif1_platform_data = {
 105         .mapbase        = 0xe6c50000,
 106         .flags          = UPF_BOOT_AUTOCONF,
 107         .scscr          = SCSCR_RE | SCSCR_TE,
 108         .scbrr_algo_id  = SCBRR_ALGO_4,
 109         .type           = PORT_SCIFA,
 110         .irqs           = { gic_spi(73), gic_spi(73),
 111                             gic_spi(73), gic_spi(73) },
 112 };
 113
 114 static struct platform_device scif1_device = {
 115         .name           = "sh-sci",
 116         .id             = 1,
 117         .dev            = {
 118                 .platform_data  = &scif1_platform_data,
 119         },
 120 };
 121
 122 static struct plat_sci_port scif2_platform_data = {
 123         .mapbase        = 0xe6c60000,
 124         .flags          = UPF_BOOT_AUTOCONF,
 125         .scscr          = SCSCR_RE | SCSCR_TE,
 126         .scbrr_algo_id  = SCBRR_ALGO_4,
 127         .type           = PORT_SCIFA,
 128         .irqs           = { gic_spi(74), gic_spi(74),
 129                             gic_spi(74), gic_spi(74) },
 130 };
 131
 132 static struct platform_device scif2_device = {
 133         .name           = "sh-sci",
 134         .id             = 2,
 135         .dev            = {
 136                 .platform_data  = &scif2_platform_data,
 137         },
 138 };
 139
 140 static struct plat_sci_port scif3_platform_data = {
 141         .mapbase        = 0xe6c70000,
 142         .flags          = UPF_BOOT_AUTOCONF,
 143         .scscr          = SCSCR_RE | SCSCR_TE,
 144         .scbrr_algo_id  = SCBRR_ALGO_4,
 145         .type           = PORT_SCIFA,
 146         .irqs           = { gic_spi(75), gic_spi(75),
 147                             gic_spi(75), gic_spi(75) },
 148 };
 149
 150 static struct platform_device scif3_device = {
 151         .name           = "sh-sci",
 152         .id             = 3,
 153         .dev            = {
 154                 .platform_data  = &scif3_platform_data,
 155         },
 156 };
 157
 158 static struct plat_sci_port scif4_platform_data = {
 159         .mapbase        = 0xe6c80000,
 160         .flags          = UPF_BOOT_AUTOCONF,
 161         .scscr          = SCSCR_RE | SCSCR_TE,
 162         .scbrr_algo_id  = SCBRR_ALGO_4,
 163         .type           = PORT_SCIFA,
 164         .irqs           = { gic_spi(78), gic_spi(78),
 165                             gic_spi(78), gic_spi(78) },
 166 };
 167
 168 static struct platform_device scif4_device = {
 169         .name           = "sh-sci",
 170         .id             = 4,
 171         .dev            = {
 172                 .platform_data  = &scif4_platform_data,
 173         },
 174 };
 175
 176 static struct plat_sci_port scif5_platform_data = {
 177         .mapbase        = 0xe6cb0000,
 178         .flags          = UPF_BOOT_AUTOCONF,
 179         .scscr          = SCSCR_RE | SCSCR_TE,
 180         .scbrr_algo_id  = SCBRR_ALGO_4,
 181         .type           = PORT_SCIFA,
 182         .irqs           = { gic_spi(79), gic_spi(79),
 183                             gic_spi(79), gic_spi(79) },
 184 };
 185
 186 static struct platform_device scif5_device = {
 187         .name           = "sh-sci",
 188         .id             = 5,
 189         .dev            = {
 190                 .platform_data  = &scif5_platform_data,
 191         },
 192 };
 193
 194 static struct plat_sci_port scif6_platform_data = {
 195         .mapbase        = 0xe6cc0000,
 196         .flags          = UPF_BOOT_AUTOCONF,
 197         .scscr          = SCSCR_RE | SCSCR_TE,
 198         .scbrr_algo_id  = SCBRR_ALGO_4,
 199         .type           = PORT_SCIFA,
 200         .irqs           = { gic_spi(156), gic_spi(156),
 201                             gic_spi(156), gic_spi(156) },
 202 };
 203
 204 static struct platform_device scif6_device = {
 205         .name           = "sh-sci",
 206         .id             = 6,
 207         .dev            = {
 208                 .platform_data  = &scif6_platform_data,
 209         },
 210 };
 211
 212 static struct plat_sci_port scif7_platform_data = {
 213         .mapbase        = 0xe6cd0000,
 214         .flags          = UPF_BOOT_AUTOCONF,
 215         .scscr          = SCSCR_RE | SCSCR_TE,
 216         .scbrr_algo_id  = SCBRR_ALGO_4,
 217         .type           = PORT_SCIFA,
 218         .irqs           = { gic_spi(143), gic_spi(143),
 219                             gic_spi(143), gic_spi(143) },
 220 };
 221
 222 static struct platform_device scif7_device = {
 223         .name           = "sh-sci",
 224         .id             = 7,
 225         .dev            = {
 226                 .platform_data  = &scif7_platform_data,
 227         },
 228 };
 229
 230 static struct plat_sci_port scif8_platform_data = {
 231         .mapbase        = 0xe6c30000,
 232         .flags          = UPF_BOOT_AUTOCONF,
 233         .scscr          = SCSCR_RE | SCSCR_TE,
 234         .scbrr_algo_id  = SCBRR_ALGO_4,
 235         .type           = PORT_SCIFB,
 236         .irqs           = { gic_spi(80), gic_spi(80),
 237                             gic_spi(80), gic_spi(80) },
 238 };
 239
 240 static struct platform_device scif8_device = {
 241         .name           = "sh-sci",
 242         .id             = 8,
 243         .dev            = {
 244                 .platform_data  = &scif8_platform_data,
 245         },
 246 };
 247
 248 static struct sh_timer_config cmt10_platform_data = {
 249         .name = "CMT10",
 250         .channel_offset = 0x10,
 251         .timer_bit = 0,
 252         .clockevent_rating = 125,
 253         .clocksource_rating = 125,
 254 };
 255
 256 static struct resource cmt10_resources[] = {
 257         [0] = {
 258                 .name   = "CMT10",
 259                 .start  = 0xe6138010,
 260                 .end    = 0xe613801b,
 261                 .flags  = IORESOURCE_MEM,
 262         },
 263         [1] = {
 264                 .start  = gic_spi(65),
 265                 .flags  = IORESOURCE_IRQ,
 266         },
 267 };
 268
 269 static struct platform_device cmt10_device = {
 270         .name           = "sh_cmt",
 271         .id             = 10,
 272         .dev = {
 273                 .platform_data  = &cmt10_platform_data,
 274         },
 275         .resource       = cmt10_resources,
 276         .num_resources  = ARRAY_SIZE(cmt10_resources),
 277 };
 278
 279 /* TMU */
 280 static struct sh_timer_config tmu00_platform_data = {
 281         .name = "TMU00",
 282         .channel_offset = 0x4,
 283         .timer_bit = 0,
 284         .clockevent_rating = 200,
 285 };
 286
 287 static struct resource tmu00_resources[] = {
 288         [0] = {
 289                 .name   = "TMU00",
 290                 .start  = 0xfff60008,
 291                 .end    = 0xfff60013,
 292                 .flags  = IORESOURCE_MEM,
 293         },
 294         [1] = {
 295                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
 296                 .flags  = IORESOURCE_IRQ,
 297         },
 298 };
 299
 300 static struct platform_device tmu00_device = {
 301         .name           = "sh_tmu",
 302         .id             = 0,
 303         .dev = {
 304                 .platform_data  = &tmu00_platform_data,
 305         },
 306         .resource       = tmu00_resources,
 307         .num_resources  = ARRAY_SIZE(tmu00_resources),
 308 };
 309
 310 static struct sh_timer_config tmu01_platform_data = {
 311         .name = "TMU01",
 312         .channel_offset = 0x10,
 313         .timer_bit = 1,
 314         .clocksource_rating = 200,
 315 };
 316
 317 static struct resource tmu01_resources[] = {
 318         [0] = {
 319                 .name   = "TMU01",
 320                 .start  = 0xfff60014,
 321                 .end    = 0xfff6001f,
 322                 .flags  = IORESOURCE_MEM,
 323         },
 324         [1] = {
 325                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
 326                 .flags  = IORESOURCE_IRQ,
 327         },
 328 };
 329
 330 static struct platform_device tmu01_device = {
 331         .name           = "sh_tmu",
 332         .id             = 1,
 333         .dev = {
 334                 .platform_data  = &tmu01_platform_data,
 335         },
 336         .resource       = tmu01_resources,
 337         .num_resources  = ARRAY_SIZE(tmu01_resources),
 338 };
 339
 340 static struct resource i2c0_resources[] = {
 341         [0] = {
 342                 .name   = "IIC0",
 343                 .start  = 0xe6820000,
 344                 .end    = 0xe6820425 - 1,
 345                 .flags  = IORESOURCE_MEM,
 346         },
 347         [1] = {
 348                 .start  = gic_spi(167),
 349                 .end    = gic_spi(170),
 350                 .flags  = IORESOURCE_IRQ,
 351         },
 352 };
 353
 354 static struct resource i2c1_resources[] = {
 355         [0] = {
 356                 .name   = "IIC1",
 357                 .start  = 0xe6822000,
 358                 .end    = 0xe6822425 - 1,
 359                 .flags  = IORESOURCE_MEM,
 360         },
 361         [1] = {
 362                 .start  = gic_spi(51),
 363                 .end    = gic_spi(54),
 364                 .flags  = IORESOURCE_IRQ,
 365         },
 366 };
 367
 368 static struct resource i2c2_resources[] = {
 369         [0] = {
 370                 .name   = "IIC2",
 371                 .start  = 0xe6824000,
 372                 .end    = 0xe6824425 - 1,
 373                 .flags  = IORESOURCE_MEM,
 374         },
 375         [1] = {
 376                 .start  = gic_spi(171),
 377                 .end    = gic_spi(174),
 378                 .flags  = IORESOURCE_IRQ,
 379         },
 380 };
 381
 382 static struct resource i2c3_resources[] = {
 383         [0] = {
 384                 .name   = "IIC3",
 385                 .start  = 0xe6826000,
 386                 .end    = 0xe6826425 - 1,
 387                 .flags  = IORESOURCE_MEM,
 388         },
 389         [1] = {
 390                 .start  = gic_spi(183),
 391                 .end    = gic_spi(186),
 392                 .flags  = IORESOURCE_IRQ,
 393         },
 394 };
 395
 396 static struct resource i2c4_resources[] = {
 397         [0] = {
 398                 .name   = "IIC4",
 399                 .start  = 0xe6828000,
 400                 .end    = 0xe6828425 - 1,
 401                 .flags  = IORESOURCE_MEM,
 402         },
 403         [1] = {
 404                 .start  = gic_spi(187),
 405                 .end    = gic_spi(190),
 406                 .flags  = IORESOURCE_IRQ,
 407         },
 408 };
 409
 410 static struct platform_device i2c0_device = {
 411         .name           = "i2c-sh_mobile",
 412         .id             = 0,
 413         .resource       = i2c0_resources,
 414         .num_resources  = ARRAY_SIZE(i2c0_resources),
 415 };
 416
 417 static struct platform_device i2c1_device = {
 418         .name           = "i2c-sh_mobile",
 419         .id             = 1,
 420         .resource       = i2c1_resources,
 421         .num_resources  = ARRAY_SIZE(i2c1_resources),
 422 };
 423
 424 static struct platform_device i2c2_device = {
 425         .name           = "i2c-sh_mobile",
 426         .id             = 2,
 427         .resource       = i2c2_resources,
 428         .num_resources  = ARRAY_SIZE(i2c2_resources),
 429 };
 430
 431 static struct platform_device i2c3_device = {
 432         .name           = "i2c-sh_mobile",
 433         .id             = 3,
 434         .resource       = i2c3_resources,
 435         .num_resources  = ARRAY_SIZE(i2c3_resources),
 436 };
 437
 438 static struct platform_device i2c4_device = {
 439         .name           = "i2c-sh_mobile",
 440         .id             = 4,
 441         .resource       = i2c4_resources,
 442         .num_resources  = ARRAY_SIZE(i2c4_resources),
 443 };
 444
 445 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 446         {
 447                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 448                 .addr           = 0xe6c40020,
 449                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 450                 .mid_rid        = 0x21,
 451         }, {
 452                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 453                 .addr           = 0xe6c40024,
 454                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 455                 .mid_rid        = 0x22,
 456         }, {
 457                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 458                 .addr           = 0xe6c50020,
 459                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 460                 .mid_rid        = 0x25,
 461         }, {
 462                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 463                 .addr           = 0xe6c50024,
 464                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 465                 .mid_rid        = 0x26,
 466         }, {
 467                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 468                 .addr           = 0xe6c60020,
 469                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 470                 .mid_rid        = 0x29,
 471         }, {
 472                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 473                 .addr           = 0xe6c60024,
 474                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 475                 .mid_rid        = 0x2a,
 476         }, {
 477                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 478                 .addr           = 0xe6c70020,
 479                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 480                 .mid_rid        = 0x2d,
 481         }, {
 482                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 483                 .addr           = 0xe6c70024,
 484                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 485                 .mid_rid        = 0x2e,
 486         }, {
 487                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 488                 .addr           = 0xe6c80020,
 489                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 490                 .mid_rid        = 0x39,
 491         }, {
 492                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 493                 .addr           = 0xe6c80024,
 494                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 495                 .mid_rid        = 0x3a,
 496         }, {
 497                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 498                 .addr           = 0xe6cb0020,
 499                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 500                 .mid_rid        = 0x35,
 501         }, {
 502                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 503                 .addr           = 0xe6cb0024,
 504                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 505                 .mid_rid        = 0x36,
 506         }, {
 507                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 508                 .addr           = 0xe6cc0020,
 509                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 510                 .mid_rid        = 0x1d,
 511         }, {
 512                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 513                 .addr           = 0xe6cc0024,
 514                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 515                 .mid_rid        = 0x1e,
 516         }, {
 517                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 518                 .addr           = 0xe6cd0020,
 519                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 520                 .mid_rid        = 0x19,
 521         }, {
 522                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 523                 .addr           = 0xe6cd0024,
 524                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 525                 .mid_rid        = 0x1a,
 526         }, {
 527                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 528                 .addr           = 0xe6c30040,
 529                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 530                 .mid_rid        = 0x3d,
 531         }, {
 532                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 533                 .addr           = 0xe6c30060,
 534                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 535                 .mid_rid        = 0x3e,
 536         }, {
 537                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 538                 .addr           = 0xee100030,
 539                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 540                 .mid_rid        = 0xc1,
 541         }, {
 542                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 543                 .addr           = 0xee100030,
 544                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 545                 .mid_rid        = 0xc2,
 546         }, {
 547                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 548                 .addr           = 0xee120030,
 549                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 550                 .mid_rid        = 0xc9,
 551         }, {
 552                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 553                 .addr           = 0xee120030,
 554                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 555                 .mid_rid        = 0xca,
 556         }, {
 557                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 558                 .addr           = 0xee140030,
 559                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 560                 .mid_rid        = 0xcd,
 561         }, {
 562                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 563                 .addr           = 0xee140030,
 564                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 565                 .mid_rid        = 0xce,
 566         }, {
 567                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 568                 .addr           = 0xe6bd0034,
 569                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 570                 .mid_rid        = 0xd1,
 571         }, {
 572                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 573                 .addr           = 0xe6bd0034,
 574                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 575                 .mid_rid        = 0xd2,
 576         },
 577 };
 578
 579 #define DMAE_CHANNEL(_offset)                                   \
 580         {                                                       \
 581                 .offset         = _offset - 0x20,               \
 582                 .dmars          = _offset - 0x20 + 0x40,        \
 583         }
 584
 585 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 586         DMAE_CHANNEL(0x8000),
 587         DMAE_CHANNEL(0x8080),
 588         DMAE_CHANNEL(0x8100),
 589         DMAE_CHANNEL(0x8180),
 590         DMAE_CHANNEL(0x8200),
 591         DMAE_CHANNEL(0x8280),
 592         DMAE_CHANNEL(0x8300),
 593         DMAE_CHANNEL(0x8380),
 594         DMAE_CHANNEL(0x8400),
 595         DMAE_CHANNEL(0x8480),
 596         DMAE_CHANNEL(0x8500),
 597         DMAE_CHANNEL(0x8580),
 598         DMAE_CHANNEL(0x8600),
 599         DMAE_CHANNEL(0x8680),
 600         DMAE_CHANNEL(0x8700),
 601         DMAE_CHANNEL(0x8780),
 602         DMAE_CHANNEL(0x8800),
 603         DMAE_CHANNEL(0x8880),
 604         DMAE_CHANNEL(0x8900),
 605         DMAE_CHANNEL(0x8980),
 606 };
 607
 608 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 609         .slave          = sh73a0_dmae_slaves,
 610         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 611         .channel        = sh73a0_dmae_channels,
 612         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 613         .ts_low_shift   = TS_LOW_SHIFT,
 614         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 615         .ts_high_shift  = TS_HI_SHIFT,
 616         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 617         .ts_shift       = dma_ts_shift,
 618         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 619         .dmaor_init     = DMAOR_DME,
 620 };
 621
 622 static struct resource sh73a0_dmae_resources[] = {
 623         {
 624                 /* Registers including DMAOR and channels including DMARSx */
 625                 .start  = 0xfe000020,
 626                 .end    = 0xfe008a00 - 1,
 627                 .flags  = IORESOURCE_MEM,
 628         },
 629         {
 630                 .name   = "error_irq",
 631                 .start  = gic_spi(129),
 632                 .end    = gic_spi(129),
 633                 .flags  = IORESOURCE_IRQ,
 634         },
 635         {
 636                 /* IRQ for channels 0-19 */
 637                 .start  = gic_spi(109),
 638                 .end    = gic_spi(128),
 639                 .flags  = IORESOURCE_IRQ,
 640         },
 641 };
 642
 643 static struct platform_device dma0_device = {
 644         .name           = "sh-dma-engine",
 645         .id             = 0,
 646         .resource       = sh73a0_dmae_resources,
 647         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 648         .dev            = {
 649                 .platform_data  = &sh73a0_dmae_platform_data,
 650         },
 651 };
 652
 653 /* MPDMAC */
 654 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
 655         {
 656                 .slave_id       = SHDMA_SLAVE_FSI2A_RX,
 657                 .addr           = 0xec230020,
 658                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 659                 .mid_rid        = 0xd6, /* CHECK ME */
 660         }, {
 661                 .slave_id       = SHDMA_SLAVE_FSI2A_TX,
 662                 .addr           = 0xec230024,
 663                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 664                 .mid_rid        = 0xd5, /* CHECK ME */
 665         }, {
 666                 .slave_id       = SHDMA_SLAVE_FSI2C_RX,
 667                 .addr           = 0xec230060,
 668                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 669                 .mid_rid        = 0xda, /* CHECK ME */
 670         }, {
 671                 .slave_id       = SHDMA_SLAVE_FSI2C_TX,
 672                 .addr           = 0xec230064,
 673                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 674                 .mid_rid        = 0xd9, /* CHECK ME */
 675         }, {
 676                 .slave_id       = SHDMA_SLAVE_FSI2B_RX,
 677                 .addr           = 0xec240020,
 678                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 679                 .mid_rid        = 0x8e, /* CHECK ME */
 680         }, {
 681                 .slave_id       = SHDMA_SLAVE_FSI2B_TX,
 682                 .addr           = 0xec240024,
 683                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 684                 .mid_rid        = 0x8d, /* CHECK ME */
 685         }, {
 686                 .slave_id       = SHDMA_SLAVE_FSI2D_RX,
 687                 .addr           =  0xec240060,
 688                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 689                 .mid_rid        = 0x9a, /* CHECK ME */
 690         },
 691 };
 692
 693 #define MPDMA_CHANNEL(a, b, c)                  \
 694 {                                               \
 695         .offset         = a,                    \
 696         .dmars          = b,                    \
 697         .dmars_bit      = c,                    \
 698         .chclr_offset   = (0x220 - 0x20) + a    \
 699 }
 700
 701 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
 702         MPDMA_CHANNEL(0x00, 0, 0),
 703         MPDMA_CHANNEL(0x10, 0, 8),
 704         MPDMA_CHANNEL(0x20, 4, 0),
 705         MPDMA_CHANNEL(0x30, 4, 8),
 706         MPDMA_CHANNEL(0x50, 8, 0),
 707         MPDMA_CHANNEL(0x70, 8, 8),
 708 };
 709
 710 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 711         .slave          = sh73a0_mpdma_slaves,
 712         .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
 713         .channel        = sh73a0_mpdma_channels,
 714         .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
 715         .ts_low_shift   = TS_LOW_SHIFT,
 716         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 717         .ts_high_shift  = TS_HI_SHIFT,
 718         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 719         .ts_shift       = dma_ts_shift,
 720         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 721         .dmaor_init     = DMAOR_DME,
 722         .chclr_present  = 1,
 723 };
 724
 725 /* Resource order important! */
 726 static struct resource sh73a0_mpdma_resources[] = {
 727         {
 728                 /* Channel registers and DMAOR */
 729                 .start  = 0xec618020,
 730                 .end    = 0xec61828f,
 731                 .flags  = IORESOURCE_MEM,
 732         },
 733         {
 734                 /* DMARSx */
 735                 .start  = 0xec619000,
 736                 .end    = 0xec61900b,
 737                 .flags  = IORESOURCE_MEM,
 738         },
 739         {
 740                 .name   = "error_irq",
 741                 .start  = gic_spi(181),
 742                 .end    = gic_spi(181),
 743                 .flags  = IORESOURCE_IRQ,
 744         },
 745         {
 746                 /* IRQ for channels 0-5 */
 747                 .start  = gic_spi(175),
 748                 .end    = gic_spi(180),
 749                 .flags  = IORESOURCE_IRQ,
 750         },
 751 };
 752
 753 static struct platform_device mpdma0_device = {
 754         .name           = "sh-dma-engine",
 755         .id             = 1,
 756         .resource       = sh73a0_mpdma_resources,
 757         .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
 758         .dev            = {
 759                 .platform_data  = &sh73a0_mpdma_platform_data,
 760         },
 761 };
 762
 763 static struct resource pmu_resources[] = {
 764         [0] = {
 765                 .start  = gic_spi(55),
 766                 .end    = gic_spi(55),
 767                 .flags  = IORESOURCE_IRQ,
 768         },
 769         [1] = {
 770                 .start  = gic_spi(56),
 771                 .end    = gic_spi(56),
 772                 .flags  = IORESOURCE_IRQ,
 773         },
 774 };
 775
 776 static struct platform_device pmu_device = {
 777         .name           = "arm-pmu",
 778         .id             = -1,
 779         .num_resources  = ARRAY_SIZE(pmu_resources),
 780         .resource       = pmu_resources,
 781 };
 782
 783 static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
 784         &scif0_device,
 785         &scif1_device,
 786         &scif2_device,
 787         &scif3_device,
 788         &scif4_device,
 789         &scif5_device,
 790         &scif6_device,
 791         &scif7_device,
 792         &scif8_device,
 793         &cmt10_device,
 794 };
 795
 796 static struct platform_device *sh73a0_early_devices[] __initdata = {
 797         &tmu00_device,
 798         &tmu01_device,
 799 };
 800
 801 static struct platform_device *sh73a0_late_devices[] __initdata = {
 802         &i2c0_device,
 803         &i2c1_device,
 804         &i2c2_device,
 805         &i2c3_device,
 806         &i2c4_device,
 807         &dma0_device,
 808         &mpdma0_device,
 809         &pmu_device,
 810 };
 811
 812 #define SRCR2          IOMEM(0xe61580b0)
 813
 814 void __init sh73a0_add_standard_devices(void)
 815 {
 816         /* Clear software reset bit on SY-DMAC module */
 817         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 818
 819         platform_add_devices(sh73a0_early_devices_dt,
 820                             ARRAY_SIZE(sh73a0_early_devices_dt));
 821         platform_add_devices(sh73a0_early_devices,
 822                             ARRAY_SIZE(sh73a0_early_devices));
 823         platform_add_devices(sh73a0_late_devices,
 824                             ARRAY_SIZE(sh73a0_late_devices));
 825 }
 826
 827 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 828 void __init __weak sh73a0_register_twd(void) { }
 829
 830 void __init sh73a0_earlytimer_init(void)
 831 {
 832         sh73a0_clock_init();
 833         shmobile_earlytimer_init();
 834         sh73a0_register_twd();
 835 }
 836
 837 void __init sh73a0_add_early_devices(void)
 838 {
 839         early_platform_add_devices(sh73a0_early_devices_dt,
 840                                    ARRAY_SIZE(sh73a0_early_devices_dt));
 841         early_platform_add_devices(sh73a0_early_devices,
 842                                    ARRAY_SIZE(sh73a0_early_devices));
 843
 844         /* setup early console here as well */
 845         shmobile_setup_console();
 846 }
 847
 848 #ifdef CONFIG_USE_OF
 849
 850 /* Please note that the clock initialisation shcheme used in
 851  * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
 852  * does not work with SMP as there is a yet to be resolved lock-up in
 853  * workqueue initialisation.
 854  *
 855  * CONFIG_SMP should be disabled when using this code.
 856  */
 857
 858 void __init sh73a0_add_early_devices_dt(void)
 859 {
 860         shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
 861
 862         early_platform_add_devices(sh73a0_early_devices_dt,
 863                                    ARRAY_SIZE(sh73a0_early_devices_dt));
 864
 865         /* setup early console here as well */
 866         shmobile_setup_console();
 867 }
 868
 869 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
 870         {},
 871 };
 872
 873 void __init sh73a0_add_standard_devices_dt(void)
 874 {
 875         /* clocks are setup late during boot in the case of DT */
 876         sh73a0_clock_init();
 877
 878         platform_add_devices(sh73a0_early_devices_dt,
 879                              ARRAY_SIZE(sh73a0_early_devices_dt));
 880         of_platform_populate(NULL, of_default_bus_match_table,
 881                              sh73a0_auxdata_lookup, NULL);
 882 }
 883
 884 static const char *sh73a0_boards_compat_dt[] __initdata = {
 885         "renesas,sh73a0",
 886         NULL,
 887 };
 888
 889 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
 890         .map_io         = sh73a0_map_io,
 891         .init_early     = sh73a0_add_early_devices_dt,
 892         .nr_irqs        = NR_IRQS_LEGACY,
 893         .init_irq       = sh73a0_init_irq_dt,
 894         .init_machine   = sh73a0_add_standard_devices_dt,
 895         .init_time      = shmobile_timer_init,
 896         .dt_compat      = sh73a0_boards_compat_dt,
 897 MACHINE_END
 898 #endif /* CONFIG_USE_OF */