arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/platform_data/sh_ipmmu.h>
  34 #include <mach/dma-register.h>
  35 #include <mach/hardware.h>
  36 #include <mach/irqs.h>
  37 #include <mach/sh73a0.h>
  38 #include <mach/common.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/mach/map.h>
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/time.h>
  43
  44 static struct map_desc sh73a0_io_desc[] __initdata = {
  45         /* create a 1:1 entity map for 0xe6xxxxxx
  46          * used by CPGA, INTC and PFC.
  47          */
  48         {
  49                 .virtual        = 0xe6000000,
  50                 .pfn            = __phys_to_pfn(0xe6000000),
  51                 .length         = 256 << 20,
  52                 .type           = MT_DEVICE_NONSHARED
  53         },
  54 };
  55
  56 void __init sh73a0_map_io(void)
  57 {
  58         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  59 }
  60
  61 static struct plat_sci_port scif0_platform_data = {
  62         .mapbase        = 0xe6c40000,
  63         .flags          = UPF_BOOT_AUTOCONF,
  64         .scscr          = SCSCR_RE | SCSCR_TE,
  65         .scbrr_algo_id  = SCBRR_ALGO_4,
  66         .type           = PORT_SCIFA,
  67         .irqs           = { gic_spi(72), gic_spi(72),
  68                             gic_spi(72), gic_spi(72) },
  69 };
  70
  71 static struct platform_device scif0_device = {
  72         .name           = "sh-sci",
  73         .id             = 0,
  74         .dev            = {
  75                 .platform_data  = &scif0_platform_data,
  76         },
  77 };
  78
  79 static struct plat_sci_port scif1_platform_data = {
  80         .mapbase        = 0xe6c50000,
  81         .flags          = UPF_BOOT_AUTOCONF,
  82         .scscr          = SCSCR_RE | SCSCR_TE,
  83         .scbrr_algo_id  = SCBRR_ALGO_4,
  84         .type           = PORT_SCIFA,
  85         .irqs           = { gic_spi(73), gic_spi(73),
  86                             gic_spi(73), gic_spi(73) },
  87 };
  88
  89 static struct platform_device scif1_device = {
  90         .name           = "sh-sci",
  91         .id             = 1,
  92         .dev            = {
  93                 .platform_data  = &scif1_platform_data,
  94         },
  95 };
  96
  97 static struct plat_sci_port scif2_platform_data = {
  98         .mapbase        = 0xe6c60000,
  99         .flags          = UPF_BOOT_AUTOCONF,
 100         .scscr          = SCSCR_RE | SCSCR_TE,
 101         .scbrr_algo_id  = SCBRR_ALGO_4,
 102         .type           = PORT_SCIFA,
 103         .irqs           = { gic_spi(74), gic_spi(74),
 104                             gic_spi(74), gic_spi(74) },
 105 };
 106
 107 static struct platform_device scif2_device = {
 108         .name           = "sh-sci",
 109         .id             = 2,
 110         .dev            = {
 111                 .platform_data  = &scif2_platform_data,
 112         },
 113 };
 114
 115 static struct plat_sci_port scif3_platform_data = {
 116         .mapbase        = 0xe6c70000,
 117         .flags          = UPF_BOOT_AUTOCONF,
 118         .scscr          = SCSCR_RE | SCSCR_TE,
 119         .scbrr_algo_id  = SCBRR_ALGO_4,
 120         .type           = PORT_SCIFA,
 121         .irqs           = { gic_spi(75), gic_spi(75),
 122                             gic_spi(75), gic_spi(75) },
 123 };
 124
 125 static struct platform_device scif3_device = {
 126         .name           = "sh-sci",
 127         .id             = 3,
 128         .dev            = {
 129                 .platform_data  = &scif3_platform_data,
 130         },
 131 };
 132
 133 static struct plat_sci_port scif4_platform_data = {
 134         .mapbase        = 0xe6c80000,
 135         .flags          = UPF_BOOT_AUTOCONF,
 136         .scscr          = SCSCR_RE | SCSCR_TE,
 137         .scbrr_algo_id  = SCBRR_ALGO_4,
 138         .type           = PORT_SCIFA,
 139         .irqs           = { gic_spi(78), gic_spi(78),
 140                             gic_spi(78), gic_spi(78) },
 141 };
 142
 143 static struct platform_device scif4_device = {
 144         .name           = "sh-sci",
 145         .id             = 4,
 146         .dev            = {
 147                 .platform_data  = &scif4_platform_data,
 148         },
 149 };
 150
 151 static struct plat_sci_port scif5_platform_data = {
 152         .mapbase        = 0xe6cb0000,
 153         .flags          = UPF_BOOT_AUTOCONF,
 154         .scscr          = SCSCR_RE | SCSCR_TE,
 155         .scbrr_algo_id  = SCBRR_ALGO_4,
 156         .type           = PORT_SCIFA,
 157         .irqs           = { gic_spi(79), gic_spi(79),
 158                             gic_spi(79), gic_spi(79) },
 159 };
 160
 161 static struct platform_device scif5_device = {
 162         .name           = "sh-sci",
 163         .id             = 5,
 164         .dev            = {
 165                 .platform_data  = &scif5_platform_data,
 166         },
 167 };
 168
 169 static struct plat_sci_port scif6_platform_data = {
 170         .mapbase        = 0xe6cc0000,
 171         .flags          = UPF_BOOT_AUTOCONF,
 172         .scscr          = SCSCR_RE | SCSCR_TE,
 173         .scbrr_algo_id  = SCBRR_ALGO_4,
 174         .type           = PORT_SCIFA,
 175         .irqs           = { gic_spi(156), gic_spi(156),
 176                             gic_spi(156), gic_spi(156) },
 177 };
 178
 179 static struct platform_device scif6_device = {
 180         .name           = "sh-sci",
 181         .id             = 6,
 182         .dev            = {
 183                 .platform_data  = &scif6_platform_data,
 184         },
 185 };
 186
 187 static struct plat_sci_port scif7_platform_data = {
 188         .mapbase        = 0xe6cd0000,
 189         .flags          = UPF_BOOT_AUTOCONF,
 190         .scscr          = SCSCR_RE | SCSCR_TE,
 191         .scbrr_algo_id  = SCBRR_ALGO_4,
 192         .type           = PORT_SCIFA,
 193         .irqs           = { gic_spi(143), gic_spi(143),
 194                             gic_spi(143), gic_spi(143) },
 195 };
 196
 197 static struct platform_device scif7_device = {
 198         .name           = "sh-sci",
 199         .id             = 7,
 200         .dev            = {
 201                 .platform_data  = &scif7_platform_data,
 202         },
 203 };
 204
 205 static struct plat_sci_port scif8_platform_data = {
 206         .mapbase        = 0xe6c30000,
 207         .flags          = UPF_BOOT_AUTOCONF,
 208         .scscr          = SCSCR_RE | SCSCR_TE,
 209         .scbrr_algo_id  = SCBRR_ALGO_4,
 210         .type           = PORT_SCIFB,
 211         .irqs           = { gic_spi(80), gic_spi(80),
 212                             gic_spi(80), gic_spi(80) },
 213 };
 214
 215 static struct platform_device scif8_device = {
 216         .name           = "sh-sci",
 217         .id             = 8,
 218         .dev            = {
 219                 .platform_data  = &scif8_platform_data,
 220         },
 221 };
 222
 223 static struct sh_timer_config cmt10_platform_data = {
 224         .name = "CMT10",
 225         .channel_offset = 0x10,
 226         .timer_bit = 0,
 227         .clockevent_rating = 125,
 228         .clocksource_rating = 125,
 229 };
 230
 231 static struct resource cmt10_resources[] = {
 232         [0] = {
 233                 .name   = "CMT10",
 234                 .start  = 0xe6138010,
 235                 .end    = 0xe613801b,
 236                 .flags  = IORESOURCE_MEM,
 237         },
 238         [1] = {
 239                 .start  = gic_spi(65),
 240                 .flags  = IORESOURCE_IRQ,
 241         },
 242 };
 243
 244 static struct platform_device cmt10_device = {
 245         .name           = "sh_cmt",
 246         .id             = 10,
 247         .dev = {
 248                 .platform_data  = &cmt10_platform_data,
 249         },
 250         .resource       = cmt10_resources,
 251         .num_resources  = ARRAY_SIZE(cmt10_resources),
 252 };
 253
 254 /* TMU */
 255 static struct sh_timer_config tmu00_platform_data = {
 256         .name = "TMU00",
 257         .channel_offset = 0x4,
 258         .timer_bit = 0,
 259         .clockevent_rating = 200,
 260 };
 261
 262 static struct resource tmu00_resources[] = {
 263         [0] = {
 264                 .name   = "TMU00",
 265                 .start  = 0xfff60008,
 266                 .end    = 0xfff60013,
 267                 .flags  = IORESOURCE_MEM,
 268         },
 269         [1] = {
 270                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
 271                 .flags  = IORESOURCE_IRQ,
 272         },
 273 };
 274
 275 static struct platform_device tmu00_device = {
 276         .name           = "sh_tmu",
 277         .id             = 0,
 278         .dev = {
 279                 .platform_data  = &tmu00_platform_data,
 280         },
 281         .resource       = tmu00_resources,
 282         .num_resources  = ARRAY_SIZE(tmu00_resources),
 283 };
 284
 285 static struct sh_timer_config tmu01_platform_data = {
 286         .name = "TMU01",
 287         .channel_offset = 0x10,
 288         .timer_bit = 1,
 289         .clocksource_rating = 200,
 290 };
 291
 292 static struct resource tmu01_resources[] = {
 293         [0] = {
 294                 .name   = "TMU01",
 295                 .start  = 0xfff60014,
 296                 .end    = 0xfff6001f,
 297                 .flags  = IORESOURCE_MEM,
 298         },
 299         [1] = {
 300                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
 301                 .flags  = IORESOURCE_IRQ,
 302         },
 303 };
 304
 305 static struct platform_device tmu01_device = {
 306         .name           = "sh_tmu",
 307         .id             = 1,
 308         .dev = {
 309                 .platform_data  = &tmu01_platform_data,
 310         },
 311         .resource       = tmu01_resources,
 312         .num_resources  = ARRAY_SIZE(tmu01_resources),
 313 };
 314
 315 static struct resource i2c0_resources[] = {
 316         [0] = {
 317                 .name   = "IIC0",
 318                 .start  = 0xe6820000,
 319                 .end    = 0xe6820425 - 1,
 320                 .flags  = IORESOURCE_MEM,
 321         },
 322         [1] = {
 323                 .start  = gic_spi(167),
 324                 .end    = gic_spi(170),
 325                 .flags  = IORESOURCE_IRQ,
 326         },
 327 };
 328
 329 static struct resource i2c1_resources[] = {
 330         [0] = {
 331                 .name   = "IIC1",
 332                 .start  = 0xe6822000,
 333                 .end    = 0xe6822425 - 1,
 334                 .flags  = IORESOURCE_MEM,
 335         },
 336         [1] = {
 337                 .start  = gic_spi(51),
 338                 .end    = gic_spi(54),
 339                 .flags  = IORESOURCE_IRQ,
 340         },
 341 };
 342
 343 static struct resource i2c2_resources[] = {
 344         [0] = {
 345                 .name   = "IIC2",
 346                 .start  = 0xe6824000,
 347                 .end    = 0xe6824425 - 1,
 348                 .flags  = IORESOURCE_MEM,
 349         },
 350         [1] = {
 351                 .start  = gic_spi(171),
 352                 .end    = gic_spi(174),
 353                 .flags  = IORESOURCE_IRQ,
 354         },
 355 };
 356
 357 static struct resource i2c3_resources[] = {
 358         [0] = {
 359                 .name   = "IIC3",
 360                 .start  = 0xe6826000,
 361                 .end    = 0xe6826425 - 1,
 362                 .flags  = IORESOURCE_MEM,
 363         },
 364         [1] = {
 365                 .start  = gic_spi(183),
 366                 .end    = gic_spi(186),
 367                 .flags  = IORESOURCE_IRQ,
 368         },
 369 };
 370
 371 static struct resource i2c4_resources[] = {
 372         [0] = {
 373                 .name   = "IIC4",
 374                 .start  = 0xe6828000,
 375                 .end    = 0xe6828425 - 1,
 376                 .flags  = IORESOURCE_MEM,
 377         },
 378         [1] = {
 379                 .start  = gic_spi(187),
 380                 .end    = gic_spi(190),
 381                 .flags  = IORESOURCE_IRQ,
 382         },
 383 };
 384
 385 static struct platform_device i2c0_device = {
 386         .name           = "i2c-sh_mobile",
 387         .id             = 0,
 388         .resource       = i2c0_resources,
 389         .num_resources  = ARRAY_SIZE(i2c0_resources),
 390 };
 391
 392 static struct platform_device i2c1_device = {
 393         .name           = "i2c-sh_mobile",
 394         .id             = 1,
 395         .resource       = i2c1_resources,
 396         .num_resources  = ARRAY_SIZE(i2c1_resources),
 397 };
 398
 399 static struct platform_device i2c2_device = {
 400         .name           = "i2c-sh_mobile",
 401         .id             = 2,
 402         .resource       = i2c2_resources,
 403         .num_resources  = ARRAY_SIZE(i2c2_resources),
 404 };
 405
 406 static struct platform_device i2c3_device = {
 407         .name           = "i2c-sh_mobile",
 408         .id             = 3,
 409         .resource       = i2c3_resources,
 410         .num_resources  = ARRAY_SIZE(i2c3_resources),
 411 };
 412
 413 static struct platform_device i2c4_device = {
 414         .name           = "i2c-sh_mobile",
 415         .id             = 4,
 416         .resource       = i2c4_resources,
 417         .num_resources  = ARRAY_SIZE(i2c4_resources),
 418 };
 419
 420 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 421         {
 422                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 423                 .addr           = 0xe6c40020,
 424                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 425                 .mid_rid        = 0x21,
 426         }, {
 427                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 428                 .addr           = 0xe6c40024,
 429                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 430                 .mid_rid        = 0x22,
 431         }, {
 432                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 433                 .addr           = 0xe6c50020,
 434                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 435                 .mid_rid        = 0x25,
 436         }, {
 437                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 438                 .addr           = 0xe6c50024,
 439                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 440                 .mid_rid        = 0x26,
 441         }, {
 442                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 443                 .addr           = 0xe6c60020,
 444                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 445                 .mid_rid        = 0x29,
 446         }, {
 447                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 448                 .addr           = 0xe6c60024,
 449                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 450                 .mid_rid        = 0x2a,
 451         }, {
 452                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 453                 .addr           = 0xe6c70020,
 454                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 455                 .mid_rid        = 0x2d,
 456         }, {
 457                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 458                 .addr           = 0xe6c70024,
 459                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 460                 .mid_rid        = 0x2e,
 461         }, {
 462                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 463                 .addr           = 0xe6c80020,
 464                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 465                 .mid_rid        = 0x39,
 466         }, {
 467                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 468                 .addr           = 0xe6c80024,
 469                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 470                 .mid_rid        = 0x3a,
 471         }, {
 472                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 473                 .addr           = 0xe6cb0020,
 474                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 475                 .mid_rid        = 0x35,
 476         }, {
 477                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 478                 .addr           = 0xe6cb0024,
 479                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 480                 .mid_rid        = 0x36,
 481         }, {
 482                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 483                 .addr           = 0xe6cc0020,
 484                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 485                 .mid_rid        = 0x1d,
 486         }, {
 487                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 488                 .addr           = 0xe6cc0024,
 489                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 490                 .mid_rid        = 0x1e,
 491         }, {
 492                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 493                 .addr           = 0xe6cd0020,
 494                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 495                 .mid_rid        = 0x19,
 496         }, {
 497                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 498                 .addr           = 0xe6cd0024,
 499                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 500                 .mid_rid        = 0x1a,
 501         }, {
 502                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 503                 .addr           = 0xe6c30040,
 504                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 505                 .mid_rid        = 0x3d,
 506         }, {
 507                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 508                 .addr           = 0xe6c30060,
 509                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 510                 .mid_rid        = 0x3e,
 511         }, {
 512                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 513                 .addr           = 0xee100030,
 514                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 515                 .mid_rid        = 0xc1,
 516         }, {
 517                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 518                 .addr           = 0xee100030,
 519                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 520                 .mid_rid        = 0xc2,
 521         }, {
 522                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 523                 .addr           = 0xee120030,
 524                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 525                 .mid_rid        = 0xc9,
 526         }, {
 527                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 528                 .addr           = 0xee120030,
 529                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 530                 .mid_rid        = 0xca,
 531         }, {
 532                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 533                 .addr           = 0xee140030,
 534                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 535                 .mid_rid        = 0xcd,
 536         }, {
 537                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 538                 .addr           = 0xee140030,
 539                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 540                 .mid_rid        = 0xce,
 541         }, {
 542                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 543                 .addr           = 0xe6bd0034,
 544                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 545                 .mid_rid        = 0xd1,
 546         }, {
 547                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 548                 .addr           = 0xe6bd0034,
 549                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 550                 .mid_rid        = 0xd2,
 551         },
 552 };
 553
 554 #define DMAE_CHANNEL(_offset)                                   \
 555         {                                                       \
 556                 .offset         = _offset - 0x20,               \
 557                 .dmars          = _offset - 0x20 + 0x40,        \
 558         }
 559
 560 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 561         DMAE_CHANNEL(0x8000),
 562         DMAE_CHANNEL(0x8080),
 563         DMAE_CHANNEL(0x8100),
 564         DMAE_CHANNEL(0x8180),
 565         DMAE_CHANNEL(0x8200),
 566         DMAE_CHANNEL(0x8280),
 567         DMAE_CHANNEL(0x8300),
 568         DMAE_CHANNEL(0x8380),
 569         DMAE_CHANNEL(0x8400),
 570         DMAE_CHANNEL(0x8480),
 571         DMAE_CHANNEL(0x8500),
 572         DMAE_CHANNEL(0x8580),
 573         DMAE_CHANNEL(0x8600),
 574         DMAE_CHANNEL(0x8680),
 575         DMAE_CHANNEL(0x8700),
 576         DMAE_CHANNEL(0x8780),
 577         DMAE_CHANNEL(0x8800),
 578         DMAE_CHANNEL(0x8880),
 579         DMAE_CHANNEL(0x8900),
 580         DMAE_CHANNEL(0x8980),
 581 };
 582
 583 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 584         .slave          = sh73a0_dmae_slaves,
 585         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 586         .channel        = sh73a0_dmae_channels,
 587         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 588         .ts_low_shift   = TS_LOW_SHIFT,
 589         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 590         .ts_high_shift  = TS_HI_SHIFT,
 591         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 592         .ts_shift       = dma_ts_shift,
 593         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 594         .dmaor_init     = DMAOR_DME,
 595 };
 596
 597 static struct resource sh73a0_dmae_resources[] = {
 598         {
 599                 /* Registers including DMAOR and channels including DMARSx */
 600                 .start  = 0xfe000020,
 601                 .end    = 0xfe008a00 - 1,
 602                 .flags  = IORESOURCE_MEM,
 603         },
 604         {
 605                 .name   = "error_irq",
 606                 .start  = gic_spi(129),
 607                 .end    = gic_spi(129),
 608                 .flags  = IORESOURCE_IRQ,
 609         },
 610         {
 611                 /* IRQ for channels 0-19 */
 612                 .start  = gic_spi(109),
 613                 .end    = gic_spi(128),
 614                 .flags  = IORESOURCE_IRQ,
 615         },
 616 };
 617
 618 static struct platform_device dma0_device = {
 619         .name           = "sh-dma-engine",
 620         .id             = 0,
 621         .resource       = sh73a0_dmae_resources,
 622         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 623         .dev            = {
 624                 .platform_data  = &sh73a0_dmae_platform_data,
 625         },
 626 };
 627
 628 /* MPDMAC */
 629 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
 630         {
 631                 .slave_id       = SHDMA_SLAVE_FSI2A_RX,
 632                 .addr           = 0xec230020,
 633                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 634                 .mid_rid        = 0xd6, /* CHECK ME */
 635         }, {
 636                 .slave_id       = SHDMA_SLAVE_FSI2A_TX,
 637                 .addr           = 0xec230024,
 638                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 639                 .mid_rid        = 0xd5, /* CHECK ME */
 640         }, {
 641                 .slave_id       = SHDMA_SLAVE_FSI2C_RX,
 642                 .addr           = 0xec230060,
 643                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 644                 .mid_rid        = 0xda, /* CHECK ME */
 645         }, {
 646                 .slave_id       = SHDMA_SLAVE_FSI2C_TX,
 647                 .addr           = 0xec230064,
 648                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 649                 .mid_rid        = 0xd9, /* CHECK ME */
 650         }, {
 651                 .slave_id       = SHDMA_SLAVE_FSI2B_RX,
 652                 .addr           = 0xec240020,
 653                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 654                 .mid_rid        = 0x8e, /* CHECK ME */
 655         }, {
 656                 .slave_id       = SHDMA_SLAVE_FSI2B_TX,
 657                 .addr           = 0xec240024,
 658                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 659                 .mid_rid        = 0x8d, /* CHECK ME */
 660         }, {
 661                 .slave_id       = SHDMA_SLAVE_FSI2D_RX,
 662                 .addr           =  0xec240060,
 663                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 664                 .mid_rid        = 0x9a, /* CHECK ME */
 665         },
 666 };
 667
 668 #define MPDMA_CHANNEL(a, b, c)                  \
 669 {                                               \
 670         .offset         = a,                    \
 671         .dmars          = b,                    \
 672         .dmars_bit      = c,                    \
 673         .chclr_offset   = (0x220 - 0x20) + a    \
 674 }
 675
 676 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
 677         MPDMA_CHANNEL(0x00, 0, 0),
 678         MPDMA_CHANNEL(0x10, 0, 8),
 679         MPDMA_CHANNEL(0x20, 4, 0),
 680         MPDMA_CHANNEL(0x30, 4, 8),
 681         MPDMA_CHANNEL(0x50, 8, 0),
 682         MPDMA_CHANNEL(0x70, 8, 8),
 683 };
 684
 685 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 686         .slave          = sh73a0_mpdma_slaves,
 687         .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
 688         .channel        = sh73a0_mpdma_channels,
 689         .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
 690         .ts_low_shift   = TS_LOW_SHIFT,
 691         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 692         .ts_high_shift  = TS_HI_SHIFT,
 693         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 694         .ts_shift       = dma_ts_shift,
 695         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 696         .dmaor_init     = DMAOR_DME,
 697         .chclr_present  = 1,
 698 };
 699
 700 /* Resource order important! */
 701 static struct resource sh73a0_mpdma_resources[] = {
 702         {
 703                 /* Channel registers and DMAOR */
 704                 .start  = 0xec618020,
 705                 .end    = 0xec61828f,
 706                 .flags  = IORESOURCE_MEM,
 707         },
 708         {
 709                 /* DMARSx */
 710                 .start  = 0xec619000,
 711                 .end    = 0xec61900b,
 712                 .flags  = IORESOURCE_MEM,
 713         },
 714         {
 715                 .name   = "error_irq",
 716                 .start  = gic_spi(181),
 717                 .end    = gic_spi(181),
 718                 .flags  = IORESOURCE_IRQ,
 719         },
 720         {
 721                 /* IRQ for channels 0-5 */
 722                 .start  = gic_spi(175),
 723                 .end    = gic_spi(180),
 724                 .flags  = IORESOURCE_IRQ,
 725         },
 726 };
 727
 728 static struct platform_device mpdma0_device = {
 729         .name           = "sh-dma-engine",
 730         .id             = 1,
 731         .resource       = sh73a0_mpdma_resources,
 732         .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
 733         .dev            = {
 734                 .platform_data  = &sh73a0_mpdma_platform_data,
 735         },
 736 };
 737
 738 static struct resource pmu_resources[] = {
 739         [0] = {
 740                 .start  = gic_spi(55),
 741                 .end    = gic_spi(55),
 742                 .flags  = IORESOURCE_IRQ,
 743         },
 744         [1] = {
 745                 .start  = gic_spi(56),
 746                 .end    = gic_spi(56),
 747                 .flags  = IORESOURCE_IRQ,
 748         },
 749 };
 750
 751 static struct platform_device pmu_device = {
 752         .name           = "arm-pmu",
 753         .id             = -1,
 754         .num_resources  = ARRAY_SIZE(pmu_resources),
 755         .resource       = pmu_resources,
 756 };
 757
 758 /* an IPMMU module for ICB */
 759 static struct resource ipmmu_resources[] = {
 760         [0] = {
 761                 .name   = "IPMMU",
 762                 .start  = 0xfe951000,
 763                 .end    = 0xfe9510ff,
 764                 .flags  = IORESOURCE_MEM,
 765         },
 766 };
 767
 768 static const char * const ipmmu_dev_names[] = {
 769         "sh_mobile_lcdc_fb.0",
 770 };
 771
 772 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 773         .dev_names = ipmmu_dev_names,
 774         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 775 };
 776
 777 static struct platform_device ipmmu_device = {
 778         .name           = "ipmmu",
 779         .id             = -1,
 780         .dev = {
 781                 .platform_data = &ipmmu_platform_data,
 782         },
 783         .resource       = ipmmu_resources,
 784         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 785 };
 786
 787 static struct platform_device *sh73a0_early_devices[] __initdata = {
 788         &scif0_device,
 789         &scif1_device,
 790         &scif2_device,
 791         &scif3_device,
 792         &scif4_device,
 793         &scif5_device,
 794         &scif6_device,
 795         &scif7_device,
 796         &scif8_device,
 797         &cmt10_device,
 798         &tmu00_device,
 799         &tmu01_device,
 800         &ipmmu_device,
 801 };
 802
 803 static struct platform_device *sh73a0_late_devices[] __initdata = {
 804         &i2c0_device,
 805         &i2c1_device,
 806         &i2c2_device,
 807         &i2c3_device,
 808         &i2c4_device,
 809         &dma0_device,
 810         &mpdma0_device,
 811         &pmu_device,
 812 };
 813
 814 #define SRCR2          IOMEM(0xe61580b0)
 815
 816 void __init sh73a0_add_standard_devices(void)
 817 {
 818         /* Clear software reset bit on SY-DMAC module */
 819         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 820
 821         platform_add_devices(sh73a0_early_devices,
 822                             ARRAY_SIZE(sh73a0_early_devices));
 823         platform_add_devices(sh73a0_late_devices,
 824                             ARRAY_SIZE(sh73a0_late_devices));
 825 }
 826
 827 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 828 void __init __weak sh73a0_register_twd(void) { }
 829
 830 static void __init sh73a0_earlytimer_init(void)
 831 {
 832         sh73a0_clock_init();
 833         shmobile_earlytimer_init();
 834         sh73a0_register_twd();
 835 }
 836
 837 void __init sh73a0_add_early_devices(void)
 838 {
 839         early_platform_add_devices(sh73a0_early_devices,
 840                                    ARRAY_SIZE(sh73a0_early_devices));
 841
 842         /* setup early console here as well */
 843         shmobile_setup_console();
 844
 845         /* override timer setup with soc-specific code */
 846         shmobile_timer.init = sh73a0_earlytimer_init;
 847 }