2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
29 #include <linux/i2c/i2c-sh_mobile.h>
31 #include <linux/serial_sci.h>
32 #include <linux/sh_dma.h>
33 #include <linux/sh_timer.h>
34 #include <linux/platform_data/sh_ipmmu.h>
35 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
37 #include <asm/mach-types.h>
38 #include <asm/mach/map.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
43 #include "dma-register.h"
48 static struct map_desc sh73a0_io_desc[] __initdata = {
49 /* create a 1:1 entity map for 0xe6xxxxxx
50 * used by CPGA, INTC and PFC.
53 .virtual = 0xe6000000,
54 .pfn = __phys_to_pfn(0xe6000000),
56 .type = MT_DEVICE_NONSHARED
60 void __init sh73a0_map_io(void)
62 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
66 static struct resource pfc_resources[] __initdata = {
67 DEFINE_RES_MEM(0xe6050000, 0x8000),
68 DEFINE_RES_MEM(0xe605801c, 0x000c),
71 void __init sh73a0_pinmux_init(void)
73 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
74 ARRAY_SIZE(pfc_resources));
78 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
79 static struct plat_sci_port scif##index##_platform_data = { \
81 .flags = UPF_BOOT_AUTOCONF, \
82 .scscr = SCSCR_RE | SCSCR_TE, \
85 static struct resource scif##index##_resources[] = { \
86 DEFINE_RES_MEM(baseaddr, 0x100), \
87 DEFINE_RES_IRQ(irq), \
90 static struct platform_device scif##index##_device = { \
93 .resource = scif##index##_resources, \
94 .num_resources = ARRAY_SIZE(scif##index##_resources), \
96 .platform_data = &scif##index##_platform_data, \
100 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
101 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
102 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
103 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
104 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
105 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
106 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
107 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
108 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
110 static struct sh_timer_config cmt1_platform_data = {
111 .channels_mask = 0x3f,
114 static struct resource cmt1_resources[] = {
115 DEFINE_RES_MEM(0xe6138000, 0x200),
116 DEFINE_RES_IRQ(gic_spi(65)),
119 static struct platform_device cmt1_device = {
123 .platform_data = &cmt1_platform_data,
125 .resource = cmt1_resources,
126 .num_resources = ARRAY_SIZE(cmt1_resources),
130 static struct sh_timer_config tmu0_platform_data = {
134 static struct resource tmu0_resources[] = {
135 DEFINE_RES_MEM(0xfff60000, 0x2c),
136 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
137 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
138 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
141 static struct platform_device tmu0_device = {
145 .platform_data = &tmu0_platform_data,
147 .resource = tmu0_resources,
148 .num_resources = ARRAY_SIZE(tmu0_resources),
151 static struct resource i2c0_resources[] = {
152 [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
154 .start = gic_spi(167),
156 .flags = IORESOURCE_IRQ,
160 static struct resource i2c1_resources[] = {
161 [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
163 .start = gic_spi(51),
165 .flags = IORESOURCE_IRQ,
169 static struct resource i2c2_resources[] = {
170 [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
172 .start = gic_spi(171),
174 .flags = IORESOURCE_IRQ,
178 static struct resource i2c3_resources[] = {
179 [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
181 .start = gic_spi(183),
183 .flags = IORESOURCE_IRQ,
187 static struct resource i2c4_resources[] = {
188 [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
190 .start = gic_spi(187),
192 .flags = IORESOURCE_IRQ,
196 static struct i2c_sh_mobile_platform_data i2c_platform_data = {
200 static struct platform_device i2c0_device = {
201 .name = "i2c-sh_mobile",
203 .resource = i2c0_resources,
204 .num_resources = ARRAY_SIZE(i2c0_resources),
206 .platform_data = &i2c_platform_data,
210 static struct platform_device i2c1_device = {
211 .name = "i2c-sh_mobile",
213 .resource = i2c1_resources,
214 .num_resources = ARRAY_SIZE(i2c1_resources),
216 .platform_data = &i2c_platform_data,
220 static struct platform_device i2c2_device = {
221 .name = "i2c-sh_mobile",
223 .resource = i2c2_resources,
224 .num_resources = ARRAY_SIZE(i2c2_resources),
226 .platform_data = &i2c_platform_data,
230 static struct platform_device i2c3_device = {
231 .name = "i2c-sh_mobile",
233 .resource = i2c3_resources,
234 .num_resources = ARRAY_SIZE(i2c3_resources),
236 .platform_data = &i2c_platform_data,
240 static struct platform_device i2c4_device = {
241 .name = "i2c-sh_mobile",
243 .resource = i2c4_resources,
244 .num_resources = ARRAY_SIZE(i2c4_resources),
246 .platform_data = &i2c_platform_data,
250 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
252 .slave_id = SHDMA_SLAVE_SCIF0_TX,
254 .chcr = CHCR_TX(XMIT_SZ_8BIT),
257 .slave_id = SHDMA_SLAVE_SCIF0_RX,
259 .chcr = CHCR_RX(XMIT_SZ_8BIT),
262 .slave_id = SHDMA_SLAVE_SCIF1_TX,
264 .chcr = CHCR_TX(XMIT_SZ_8BIT),
267 .slave_id = SHDMA_SLAVE_SCIF1_RX,
269 .chcr = CHCR_RX(XMIT_SZ_8BIT),
272 .slave_id = SHDMA_SLAVE_SCIF2_TX,
274 .chcr = CHCR_TX(XMIT_SZ_8BIT),
277 .slave_id = SHDMA_SLAVE_SCIF2_RX,
279 .chcr = CHCR_RX(XMIT_SZ_8BIT),
282 .slave_id = SHDMA_SLAVE_SCIF3_TX,
284 .chcr = CHCR_TX(XMIT_SZ_8BIT),
287 .slave_id = SHDMA_SLAVE_SCIF3_RX,
289 .chcr = CHCR_RX(XMIT_SZ_8BIT),
292 .slave_id = SHDMA_SLAVE_SCIF4_TX,
294 .chcr = CHCR_TX(XMIT_SZ_8BIT),
297 .slave_id = SHDMA_SLAVE_SCIF4_RX,
299 .chcr = CHCR_RX(XMIT_SZ_8BIT),
302 .slave_id = SHDMA_SLAVE_SCIF5_TX,
304 .chcr = CHCR_TX(XMIT_SZ_8BIT),
307 .slave_id = SHDMA_SLAVE_SCIF5_RX,
309 .chcr = CHCR_RX(XMIT_SZ_8BIT),
312 .slave_id = SHDMA_SLAVE_SCIF6_TX,
314 .chcr = CHCR_TX(XMIT_SZ_8BIT),
317 .slave_id = SHDMA_SLAVE_SCIF6_RX,
319 .chcr = CHCR_RX(XMIT_SZ_8BIT),
322 .slave_id = SHDMA_SLAVE_SCIF7_TX,
324 .chcr = CHCR_TX(XMIT_SZ_8BIT),
327 .slave_id = SHDMA_SLAVE_SCIF7_RX,
329 .chcr = CHCR_RX(XMIT_SZ_8BIT),
332 .slave_id = SHDMA_SLAVE_SCIF8_TX,
334 .chcr = CHCR_TX(XMIT_SZ_8BIT),
337 .slave_id = SHDMA_SLAVE_SCIF8_RX,
339 .chcr = CHCR_RX(XMIT_SZ_8BIT),
342 .slave_id = SHDMA_SLAVE_SDHI0_TX,
344 .chcr = CHCR_TX(XMIT_SZ_16BIT),
347 .slave_id = SHDMA_SLAVE_SDHI0_RX,
349 .chcr = CHCR_RX(XMIT_SZ_16BIT),
352 .slave_id = SHDMA_SLAVE_SDHI1_TX,
354 .chcr = CHCR_TX(XMIT_SZ_16BIT),
357 .slave_id = SHDMA_SLAVE_SDHI1_RX,
359 .chcr = CHCR_RX(XMIT_SZ_16BIT),
362 .slave_id = SHDMA_SLAVE_SDHI2_TX,
364 .chcr = CHCR_TX(XMIT_SZ_16BIT),
367 .slave_id = SHDMA_SLAVE_SDHI2_RX,
369 .chcr = CHCR_RX(XMIT_SZ_16BIT),
372 .slave_id = SHDMA_SLAVE_MMCIF_TX,
374 .chcr = CHCR_TX(XMIT_SZ_32BIT),
377 .slave_id = SHDMA_SLAVE_MMCIF_RX,
379 .chcr = CHCR_RX(XMIT_SZ_32BIT),
384 #define DMAE_CHANNEL(_offset) \
386 .offset = _offset - 0x20, \
387 .dmars = _offset - 0x20 + 0x40, \
390 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
391 DMAE_CHANNEL(0x8000),
392 DMAE_CHANNEL(0x8080),
393 DMAE_CHANNEL(0x8100),
394 DMAE_CHANNEL(0x8180),
395 DMAE_CHANNEL(0x8200),
396 DMAE_CHANNEL(0x8280),
397 DMAE_CHANNEL(0x8300),
398 DMAE_CHANNEL(0x8380),
399 DMAE_CHANNEL(0x8400),
400 DMAE_CHANNEL(0x8480),
401 DMAE_CHANNEL(0x8500),
402 DMAE_CHANNEL(0x8580),
403 DMAE_CHANNEL(0x8600),
404 DMAE_CHANNEL(0x8680),
405 DMAE_CHANNEL(0x8700),
406 DMAE_CHANNEL(0x8780),
407 DMAE_CHANNEL(0x8800),
408 DMAE_CHANNEL(0x8880),
409 DMAE_CHANNEL(0x8900),
410 DMAE_CHANNEL(0x8980),
413 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
414 .slave = sh73a0_dmae_slaves,
415 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
416 .channel = sh73a0_dmae_channels,
417 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
418 .ts_low_shift = TS_LOW_SHIFT,
419 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
420 .ts_high_shift = TS_HI_SHIFT,
421 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
422 .ts_shift = dma_ts_shift,
423 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
424 .dmaor_init = DMAOR_DME,
427 static struct resource sh73a0_dmae_resources[] = {
428 DEFINE_RES_MEM(0xfe000020, 0x89e0),
431 .start = gic_spi(129),
433 .flags = IORESOURCE_IRQ,
436 /* IRQ for channels 0-19 */
437 .start = gic_spi(109),
439 .flags = IORESOURCE_IRQ,
443 static struct platform_device dma0_device = {
444 .name = "sh-dma-engine",
446 .resource = sh73a0_dmae_resources,
447 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
449 .platform_data = &sh73a0_dmae_platform_data,
454 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
456 .slave_id = SHDMA_SLAVE_FSI2A_RX,
458 .chcr = CHCR_RX(XMIT_SZ_32BIT),
459 .mid_rid = 0xd6, /* CHECK ME */
461 .slave_id = SHDMA_SLAVE_FSI2A_TX,
463 .chcr = CHCR_TX(XMIT_SZ_32BIT),
464 .mid_rid = 0xd5, /* CHECK ME */
466 .slave_id = SHDMA_SLAVE_FSI2C_RX,
468 .chcr = CHCR_RX(XMIT_SZ_32BIT),
469 .mid_rid = 0xda, /* CHECK ME */
471 .slave_id = SHDMA_SLAVE_FSI2C_TX,
473 .chcr = CHCR_TX(XMIT_SZ_32BIT),
474 .mid_rid = 0xd9, /* CHECK ME */
476 .slave_id = SHDMA_SLAVE_FSI2B_RX,
478 .chcr = CHCR_RX(XMIT_SZ_32BIT),
479 .mid_rid = 0x8e, /* CHECK ME */
481 .slave_id = SHDMA_SLAVE_FSI2B_TX,
483 .chcr = CHCR_RX(XMIT_SZ_32BIT),
484 .mid_rid = 0x8d, /* CHECK ME */
486 .slave_id = SHDMA_SLAVE_FSI2D_RX,
488 .chcr = CHCR_RX(XMIT_SZ_32BIT),
489 .mid_rid = 0x9a, /* CHECK ME */
493 #define MPDMA_CHANNEL(a, b, c) \
498 .chclr_offset = (0x220 - 0x20) + a \
501 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
502 MPDMA_CHANNEL(0x00, 0, 0),
503 MPDMA_CHANNEL(0x10, 0, 8),
504 MPDMA_CHANNEL(0x20, 4, 0),
505 MPDMA_CHANNEL(0x30, 4, 8),
506 MPDMA_CHANNEL(0x50, 8, 0),
507 MPDMA_CHANNEL(0x70, 8, 8),
510 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
511 .slave = sh73a0_mpdma_slaves,
512 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
513 .channel = sh73a0_mpdma_channels,
514 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
515 .ts_low_shift = TS_LOW_SHIFT,
516 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
517 .ts_high_shift = TS_HI_SHIFT,
518 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
519 .ts_shift = dma_ts_shift,
520 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
521 .dmaor_init = DMAOR_DME,
525 /* Resource order important! */
526 static struct resource sh73a0_mpdma_resources[] = {
527 /* Channel registers and DMAOR */
528 DEFINE_RES_MEM(0xec618020, 0x270),
530 DEFINE_RES_MEM(0xec619000, 0xc),
533 .start = gic_spi(181),
535 .flags = IORESOURCE_IRQ,
538 /* IRQ for channels 0-5 */
539 .start = gic_spi(175),
541 .flags = IORESOURCE_IRQ,
545 static struct platform_device mpdma0_device = {
546 .name = "sh-dma-engine",
548 .resource = sh73a0_mpdma_resources,
549 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
551 .platform_data = &sh73a0_mpdma_platform_data,
555 static struct resource pmu_resources[] = {
557 .start = gic_spi(55),
559 .flags = IORESOURCE_IRQ,
562 .start = gic_spi(56),
564 .flags = IORESOURCE_IRQ,
568 static struct platform_device pmu_device = {
571 .num_resources = ARRAY_SIZE(pmu_resources),
572 .resource = pmu_resources,
575 /* an IPMMU module for ICB */
576 static struct resource ipmmu_resources[] = {
577 DEFINE_RES_MEM(0xfe951000, 0x100),
580 static const char * const ipmmu_dev_names[] = {
581 "sh_mobile_lcdc_fb.0",
584 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
585 .dev_names = ipmmu_dev_names,
586 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
589 static struct platform_device ipmmu_device = {
593 .platform_data = &ipmmu_platform_data,
595 .resource = ipmmu_resources,
596 .num_resources = ARRAY_SIZE(ipmmu_resources),
599 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
600 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
603 static struct resource irqpin0_resources[] = {
604 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
605 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
606 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
607 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
608 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
609 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
610 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
611 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
612 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
613 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
614 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
615 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
616 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
619 static struct platform_device irqpin0_device = {
620 .name = "renesas_intc_irqpin",
622 .resource = irqpin0_resources,
623 .num_resources = ARRAY_SIZE(irqpin0_resources),
625 .platform_data = &irqpin0_platform_data,
629 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
630 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
631 .control_parent = true, /* Disable spurious IRQ10 */
634 static struct resource irqpin1_resources[] = {
635 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
636 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
637 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
638 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
639 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
640 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
641 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
642 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
643 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
644 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
645 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
646 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
647 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
650 static struct platform_device irqpin1_device = {
651 .name = "renesas_intc_irqpin",
653 .resource = irqpin1_resources,
654 .num_resources = ARRAY_SIZE(irqpin1_resources),
656 .platform_data = &irqpin1_platform_data,
660 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
661 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
664 static struct resource irqpin2_resources[] = {
665 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
666 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
667 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
668 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
669 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
670 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
671 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
672 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
673 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
674 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
675 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
676 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
677 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
680 static struct platform_device irqpin2_device = {
681 .name = "renesas_intc_irqpin",
683 .resource = irqpin2_resources,
684 .num_resources = ARRAY_SIZE(irqpin2_resources),
686 .platform_data = &irqpin2_platform_data,
690 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
691 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
694 static struct resource irqpin3_resources[] = {
695 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
696 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
697 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
698 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
699 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
700 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
701 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
702 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
703 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
704 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
705 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
706 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
707 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
710 static struct platform_device irqpin3_device = {
711 .name = "renesas_intc_irqpin",
713 .resource = irqpin3_resources,
714 .num_resources = ARRAY_SIZE(irqpin3_resources),
716 .platform_data = &irqpin3_platform_data,
720 static struct platform_device *sh73a0_early_devices[] __initdata = {
735 static struct platform_device *sh73a0_late_devices[] __initdata = {
750 #define SRCR2 IOMEM(0xe61580b0)
752 void __init sh73a0_add_standard_devices(void)
754 /* Clear software reset bit on SY-DMAC module */
755 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
757 platform_add_devices(sh73a0_early_devices,
758 ARRAY_SIZE(sh73a0_early_devices));
759 platform_add_devices(sh73a0_late_devices,
760 ARRAY_SIZE(sh73a0_late_devices));
763 void __init sh73a0_init_delay(void)
765 shmobile_init_delay();
768 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
769 void __init __weak sh73a0_register_twd(void) { }
771 void __init sh73a0_earlytimer_init(void)
775 shmobile_earlytimer_init();
776 sh73a0_register_twd();
779 void __init sh73a0_add_early_devices(void)
781 early_platform_add_devices(sh73a0_early_devices,
782 ARRAY_SIZE(sh73a0_early_devices));
784 /* setup early console here as well */
785 shmobile_setup_console();
790 void __init sh73a0_add_standard_devices_dt(void)
792 /* clocks are setup late during boot in the case of DT */
795 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
798 static const char *sh73a0_boards_compat_dt[] __initdata = {
803 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
804 .smp = smp_ops(sh73a0_smp_ops),
805 .map_io = sh73a0_map_io,
806 .init_early = sh73a0_init_delay,
807 .init_machine = sh73a0_add_standard_devices_dt,
808 .init_late = shmobile_init_late,
809 .dt_compat = sh73a0_boards_compat_dt,
811 #endif /* CONFIG_USE_OF */