arch/arm/mach-socfpga/socfpga.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include <linux/irqchip.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/reboot.h>
  22
  23 #include <asm/hardware/cache-l2x0.h>
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/map.h>
  26
  27 #include "core.h"
  28
  29 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
  30 void __iomem *sys_manager_base_addr;
  31 void __iomem *rst_manager_base_addr;
  32 unsigned long socfpga_cpu1start_addr;
  33
  34 static struct map_desc scu_io_desc __initdata = {
  35         .virtual        = SOCFPGA_SCU_VIRT_BASE,
  36         .pfn            = 0, /* run-time */
  37         .length         = SZ_8K,
  38         .type           = MT_DEVICE,
  39 };
  40
  41 static struct map_desc uart_io_desc __initdata = {
  42         .virtual        = 0xfec02000,
  43         .pfn            = __phys_to_pfn(0xffc02000),
  44         .length         = SZ_8K,
  45         .type           = MT_DEVICE,
  46 };
  47
  48 static void __init socfpga_scu_map_io(void)
  49 {
  50         unsigned long base;
  51
  52         /* Get SCU base */
  53         asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
  54
  55         scu_io_desc.pfn = __phys_to_pfn(base);
  56         iotable_init(&scu_io_desc, 1);
  57 }
  58
  59 static void __init socfpga_map_io(void)
  60 {
  61         socfpga_scu_map_io();
  62         iotable_init(&uart_io_desc, 1);
  63         early_printk("Early printk initialized\n");
  64 }
  65
  66 void __init socfpga_sysmgr_init(void)
  67 {
  68         struct device_node *np;
  69
  70         np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
  71
  72         if (of_property_read_u32(np, "cpu1-start-addr",
  73                         (u32 *) &socfpga_cpu1start_addr))
  74                 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
  75
  76         sys_manager_base_addr = of_iomap(np, 0);
  77
  78         np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
  79         rst_manager_base_addr = of_iomap(np, 0);
  80 }
  81
  82 static void __init socfpga_init_irq(void)
  83 {
  84         irqchip_init();
  85         socfpga_sysmgr_init();
  86 }
  87
  88 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
  89 {
  90         u32 temp;
  91
  92         temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
  93
  94         if (mode == REBOOT_HARD)
  95                 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
  96         else
  97                 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
  98         writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
  99 }
 100
 101 static const char *altera_dt_match[] = {
 102         "altr,socfpga",
 103         NULL
 104 };
 105
 106 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
 107         .l2c_aux_val    = 0,
 108         .l2c_aux_mask   = ~0,
 109         .smp            = smp_ops(socfpga_smp_ops),
 110         .map_io         = socfpga_map_io,
 111         .init_irq       = socfpga_init_irq,
 112         .restart        = socfpga_cyclone5_restart,
 113         .dt_compat      = altera_dt_match,
 114 MACHINE_END