arch/arm/mach-socfpga/socfpga.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/irqchip.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/reboot.h>
  24
  25 #include <asm/hardware/cache-l2x0.h>
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/map.h>
  28
  29 #include "core.h"
  30
  31 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
  32 void __iomem *sys_manager_base_addr;
  33 void __iomem *rst_manager_base_addr;
  34 void __iomem *clk_mgr_base_addr;
  35 unsigned long cpu1start_addr;
  36
  37 static struct map_desc scu_io_desc __initdata = {
  38         .virtual        = SOCFPGA_SCU_VIRT_BASE,
  39         .pfn            = 0, /* run-time */
  40         .length         = SZ_8K,
  41         .type           = MT_DEVICE,
  42 };
  43
  44 static struct map_desc uart_io_desc __initdata = {
  45         .virtual        = 0xfec02000,
  46         .pfn            = __phys_to_pfn(0xffc02000),
  47         .length         = SZ_8K,
  48         .type           = MT_DEVICE,
  49 };
  50
  51 static void __init socfpga_scu_map_io(void)
  52 {
  53         unsigned long base;
  54
  55         /* Get SCU base */
  56         asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
  57
  58         scu_io_desc.pfn = __phys_to_pfn(base);
  59         iotable_init(&scu_io_desc, 1);
  60 }
  61
  62 static void __init socfpga_map_io(void)
  63 {
  64         socfpga_scu_map_io();
  65         iotable_init(&uart_io_desc, 1);
  66         early_printk("Early printk initialized\n");
  67 }
  68
  69 void __init socfpga_sysmgr_init(void)
  70 {
  71         struct device_node *np;
  72
  73         np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
  74
  75         if (of_property_read_u32(np, "cpu1-start-addr",
  76                         (u32 *) &cpu1start_addr))
  77                 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
  78
  79         sys_manager_base_addr = of_iomap(np, 0);
  80
  81         np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
  82         rst_manager_base_addr = of_iomap(np, 0);
  83
  84         np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
  85         clk_mgr_base_addr = of_iomap(np, 0);
  86 }
  87
  88 static void __init socfpga_init_irq(void)
  89 {
  90         irqchip_init();
  91         socfpga_sysmgr_init();
  92 }
  93
  94 static void __init socfpga_init_time(void)
  95 {
  96         of_clk_init(NULL);
  97         clocksource_of_init();
  98 }
  99
 100 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 101 {
 102         u32 temp;
 103
 104         temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 105
 106         if (mode == REBOOT_HARD)
 107                 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
 108         else
 109                 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
 110         writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 111 }
 112
 113 static void __init socfpga_cyclone5_init(void)
 114 {
 115         l2x0_of_init(0, ~0UL);
 116         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 117         socfpga_init_clocks();
 118 }
 119
 120 static const char *altera_dt_match[] = {
 121         "altr,socfpga",
 122         NULL
 123 };
 124
 125 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
 126         .smp            = smp_ops(socfpga_smp_ops),
 127         .map_io         = socfpga_map_io,
 128         .init_irq       = socfpga_init_irq,
 129         .init_time      = socfpga_init_time,
 130         .init_machine   = socfpga_cyclone5_init,
 131         .restart        = socfpga_cyclone5_restart,
 132         .dt_compat      = altera_dt_match,
 133 MACHINE_END