arch/arm/mach-ux500/board-mop500-pins.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License terms: GNU General Public License (GPL) version 2
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/bug.h>
  10 #include <linux/string.h>
  11 #include <linux/pinctrl/machine.h>
  12 #include <linux/pinctrl/pinconf-generic.h>
  13 #include <linux/platform_data/pinctrl-nomadik.h>
  14
  15 #include <asm/mach-types.h>
  16
  17 #include "pins-db8500.h"
  18 #include "board-mop500.h"
  19
  20 enum custom_pin_cfg_t {
  21         PINS_FOR_DEFAULT,
  22         PINS_FOR_U9500,
  23 };
  24
  25 static enum custom_pin_cfg_t pinsfor;
  26
  27 /* These simply sets bias for pins */
  28 #define BIAS(a,b) static unsigned long a[] = { b }
  29
  30 BIAS(pd, PIN_PULL_DOWN);
  31 BIAS(in_nopull, PIN_INPUT_NOPULL);
  32 BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
  33 BIAS(in_pu, PIN_INPUT_PULLUP);
  34 BIAS(in_pd, PIN_INPUT_PULLDOWN);
  35 BIAS(out_hi, PIN_OUTPUT_HIGH);
  36 BIAS(out_lo, PIN_OUTPUT_LOW);
  37 BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
  38
  39 BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
  40 BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
  41 BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
  42
  43 /* These also force them into GPIO mode */
  44 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
  45 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
  46 BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  47 BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  48 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
  49 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
  50 /* Sleep modes */
  51 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  52         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  53 BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
  54         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
  55 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  56         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  57 BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
  58         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
  59 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
  60         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
  61 BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  62         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  63 BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
  64         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  65 BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  66         PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  67 BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
  68         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
  69 BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  70         PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  71 BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
  72         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  73 BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
  74         PIN_SLPM_PDIS_ENABLED);
  75 BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
  76         PIN_SLPM_PDIS_DISABLED);
  77 BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
  78         PIN_SLPM_PDIS_DISABLED);
  79
  80 /* We use these to define hog settings that are always done on boot */
  81 #define DB8500_MUX_HOG(group,func) \
  82         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
  83 #define DB8500_PIN_HOG(pin,conf) \
  84         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
  85
  86 /* These are default states associated with device and changed runtime */
  87 #define DB8500_MUX(group,func,dev) \
  88         PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
  89 #define DB8500_PIN(pin,conf,dev) \
  90         PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
  91 #define DB8500_PIN_IDLE(pin, conf, dev) \
  92         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500",  \
  93                             pin, conf)
  94 #define DB8500_PIN_SLEEP(pin, conf, dev) \
  95         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
  96                             pin, conf)
  97 #define DB8500_MUX_STATE(group, func, dev, state) \
  98         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
  99 #define DB8500_PIN_STATE(pin, conf, dev, state) \
 100         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
 101
 102 #define AB8500_MUX_HOG(group, func) \
 103         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
 104 #define AB8500_PIN_HOG(pin, conf) \
 105         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
 106
 107 #define AB8500_MUX_STATE(group, func, dev, state) \
 108         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
 109 #define AB8500_PIN_STATE(pin, conf, dev, state) \
 110         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
 111
 112 #define AB8505_MUX_HOG(group, func) \
 113         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
 114 #define AB8505_PIN_HOG(pin, conf) \
 115         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
 116
 117 #define AB8505_MUX_STATE(group, func, dev, state) \
 118         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
 119 #define AB8505_PIN_STATE(pin, conf, dev, state) \
 120         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
 121
 122 static struct pinctrl_map __initdata ab8500_pinmap[] = {
 123         /* Sysclkreq2 */
 124         AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
 125         AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
 126         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
 127         AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
 128         AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
 129
 130         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
 131         AB8500_MUX_HOG("gpio2_a_1", "gpio"),
 132         AB8500_PIN_HOG("GPIO2_T9", in_pd),
 133
 134         /* Sysclkreq4 */
 135         AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
 136         AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
 137         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
 138         AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
 139         AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
 140
 141         /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
 142         AB8500_MUX_HOG("gpio4_a_1", "gpio"),
 143         AB8500_PIN_HOG("GPIO4_W2", in_pd),
 144
 145         /*
 146          * pins 6,7,8 and 9 are muxed in YCBCR0123
 147          * configured in INPUT PULL UP
 148          */
 149         AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
 150         AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
 151         AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
 152         AB8500_PIN_HOG("GPIO8_W18", in_nopull),
 153         AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
 154
 155         /*
 156          * pins 10,11,12 and 13 are muxed in GPIO
 157          * configured in INPUT PULL DOWN
 158          */
 159         AB8500_MUX_HOG("gpio10_d_1", "gpio"),
 160         AB8500_PIN_HOG("GPIO10_U17", in_pd),
 161
 162         AB8500_MUX_HOG("gpio11_d_1", "gpio"),
 163         AB8500_PIN_HOG("GPIO11_AA18", in_pd),
 164
 165         AB8500_MUX_HOG("gpio12_d_1", "gpio"),
 166         AB8500_PIN_HOG("GPIO12_U16", in_pd),
 167
 168         AB8500_MUX_HOG("gpio13_d_1", "gpio"),
 169         AB8500_PIN_HOG("GPIO13_W17", in_pd),
 170
 171         /*
 172          * pins 14,15 are muxed in PWM1 and PWM2
 173          * configured in INPUT PULL DOWN
 174          */
 175         AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
 176         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 177
 178         AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
 179         AB8500_PIN_HOG("GPIO15_B17", in_pd),
 180
 181         /*
 182          * pins 16 is muxed in GPIO
 183          * configured in INPUT PULL DOWN
 184          */
 185         AB8500_MUX_HOG("gpio16_a_1", "gpio"),
 186         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 187
 188         /*
 189          * pins 17,18,19 and 20 are muxed in AUDIO interface 1
 190          * configured in INPUT PULL DOWN
 191          */
 192         AB8500_MUX_HOG("adi1_d_1", "adi1"),
 193         AB8500_PIN_HOG("GPIO17_P5", in_pd),
 194         AB8500_PIN_HOG("GPIO18_R5", in_pd),
 195         AB8500_PIN_HOG("GPIO19_U5", in_pd),
 196         AB8500_PIN_HOG("GPIO20_T5", in_pd),
 197
 198         /*
 199          * pins 21,22 and 23 are muxed in USB UICC
 200          * configured in INPUT PULL DOWN
 201          */
 202         AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
 203         AB8500_PIN_HOG("GPIO21_H19", in_pd),
 204         AB8500_PIN_HOG("GPIO22_G20", in_pd),
 205         AB8500_PIN_HOG("GPIO23_G19", in_pd),
 206
 207         /*
 208          * pins 24,25 are muxed in GPIO
 209          * configured in INPUT PULL DOWN
 210          */
 211         AB8500_MUX_HOG("gpio24_a_1", "gpio"),
 212         AB8500_PIN_HOG("GPIO24_T14", in_pd),
 213
 214         AB8500_MUX_HOG("gpio25_a_1", "gpio"),
 215         AB8500_PIN_HOG("GPIO25_R16", in_pd),
 216
 217         /*
 218          * pins 26 is muxed in GPIO
 219          * configured in OUTPUT LOW
 220          */
 221         AB8500_MUX_HOG("gpio26_d_1", "gpio"),
 222         AB8500_PIN_HOG("GPIO26_M16", out_lo),
 223
 224         /*
 225          * pins 27,28 are muxed in DMIC12
 226          * configured in INPUT PULL DOWN
 227          */
 228         AB8500_MUX_HOG("dmic12_d_1", "dmic"),
 229         AB8500_PIN_HOG("GPIO27_J6", in_pd),
 230         AB8500_PIN_HOG("GPIO28_K6", in_pd),
 231
 232         /*
 233          * pins 29,30 are muxed in DMIC34
 234          * configured in INPUT PULL DOWN
 235          */
 236         AB8500_MUX_HOG("dmic34_d_1", "dmic"),
 237         AB8500_PIN_HOG("GPIO29_G6", in_pd),
 238         AB8500_PIN_HOG("GPIO30_H6", in_pd),
 239
 240         /*
 241          * pins 31,32 are muxed in DMIC56
 242          * configured in INPUT PULL DOWN
 243          */
 244         AB8500_MUX_HOG("dmic56_d_1", "dmic"),
 245         AB8500_PIN_HOG("GPIO31_F5", in_pd),
 246         AB8500_PIN_HOG("GPIO32_G5", in_pd),
 247
 248         /*
 249          * pins 34 is muxed in EXTCPENA
 250          * configured INPUT PULL DOWN
 251          */
 252         AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
 253         AB8500_PIN_HOG("GPIO34_R17", in_pd),
 254
 255         /*
 256          * pins 35 is muxed in GPIO
 257          * configured in OUTPUT LOW
 258          */
 259         AB8500_MUX_HOG("gpio35_d_1", "gpio"),
 260         AB8500_PIN_HOG("GPIO35_W15", in_pd),
 261
 262         /*
 263          * pins 36,37,38 and 39 are muxed in GPIO
 264          * configured in INPUT PULL DOWN
 265          */
 266         AB8500_MUX_HOG("gpio36_a_1", "gpio"),
 267         AB8500_PIN_HOG("GPIO36_A17", in_pd),
 268
 269         AB8500_MUX_HOG("gpio37_a_1", "gpio"),
 270         AB8500_PIN_HOG("GPIO37_E15", in_pd),
 271
 272         AB8500_MUX_HOG("gpio38_a_1", "gpio"),
 273         AB8500_PIN_HOG("GPIO38_C17", in_pd),
 274
 275         AB8500_MUX_HOG("gpio39_a_1", "gpio"),
 276         AB8500_PIN_HOG("GPIO39_E16", in_pd),
 277
 278         /*
 279          * pins 40 and 41 are muxed in MODCSLSDA
 280          * configured INPUT PULL DOWN
 281          */
 282         AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
 283         AB8500_PIN_HOG("GPIO40_T19", in_pd),
 284         AB8500_PIN_HOG("GPIO41_U19", in_pd),
 285
 286         /*
 287          * pins 42 is muxed in GPIO
 288          * configured INPUT PULL DOWN
 289          */
 290         AB8500_MUX_HOG("gpio42_a_1", "gpio"),
 291         AB8500_PIN_HOG("GPIO42_U2", in_pd),
 292 };
 293
 294 static struct pinctrl_map __initdata ab8505_pinmap[] = {
 295         /* Sysclkreq2 */
 296         AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
 297         AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
 298         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
 299         AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
 300         AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
 301
 302         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
 303         AB8505_MUX_HOG("gpio2_a_1", "gpio"),
 304         AB8505_PIN_HOG("GPIO2_R5", in_pd),
 305
 306         /* Sysclkreq4 */
 307         AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
 308         AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
 309         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
 310         AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
 311         AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
 312
 313         AB8505_MUX_HOG("gpio10_d_1", "gpio"),
 314         AB8505_PIN_HOG("GPIO10_B16", in_pd),
 315
 316         AB8505_MUX_HOG("gpio11_d_1", "gpio"),
 317         AB8505_PIN_HOG("GPIO11_B17", in_pd),
 318
 319         AB8505_MUX_HOG("gpio13_d_1", "gpio"),
 320         AB8505_PIN_HOG("GPIO13_D17", in_nopull),
 321
 322         AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
 323         AB8505_PIN_HOG("GPIO14_C16", in_pd),
 324
 325         AB8505_MUX_HOG("adi2_d_1", "adi2"),
 326         AB8505_PIN_HOG("GPIO17_P2", in_pd),
 327         AB8505_PIN_HOG("GPIO18_N3", in_pd),
 328         AB8505_PIN_HOG("GPIO19_T1", in_pd),
 329         AB8505_PIN_HOG("GPIO20_P3", in_pd),
 330
 331         AB8505_MUX_HOG("gpio34_a_1", "gpio"),
 332         AB8505_PIN_HOG("GPIO34_H14", in_pd),
 333
 334         AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
 335         AB8505_PIN_HOG("GPIO40_J15", in_pd),
 336         AB8505_PIN_HOG("GPIO41_J14", in_pd),
 337
 338         AB8505_MUX_HOG("gpio50_d_1", "gpio"),
 339         AB8505_PIN_HOG("GPIO50_L4", in_nopull),
 340
 341         AB8505_MUX_HOG("resethw_d_1", "resethw"),
 342         AB8505_PIN_HOG("GPIO52_D16", in_pd),
 343
 344         AB8505_MUX_HOG("service_d_1", "service"),
 345         AB8505_PIN_HOG("GPIO53_D15", in_pd),
 346 };
 347
 348 /* Pin control settings */
 349 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
 350         /*
 351          * uMSP0, mux in 4 pins, regular placement of RX/TX
 352          * explicitly set the pins to no pull
 353          */
 354         DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
 355         DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
 356         DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
 357         DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
 358         DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
 359         DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
 360         /* MSP2 for HDMI, pull down TXD, TCK, TFS  */
 361         DB8500_MUX_HOG("msp2_a_1", "msp2"),
 362         DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
 363         DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
 364         DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
 365         DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
 366         /*
 367          * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
 368          * pull-up
 369          * TODO: is this really correct? Snowball doesn't have a LCD.
 370          */
 371         DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
 372         DB8500_PIN_HOG("GPIO68_E1", in_pu),
 373         DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
 374         /*
 375          * STMPE1601/tc35893 keypad IRQ GPIO 218
 376          * TODO: set for snowball and HREF really??
 377          */
 378         DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
 379         /*
 380          * UART0, we do not mux in u0 here.
 381          * uart-0 pins gpio configuration should be kept intact to prevent
 382          * a glitch in tx line when the tty dev is opened. Later these pins
 383          * are configured by uart driver
 384          */
 385         DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
 386         DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
 387         DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
 388         DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
 389         /*
 390          * Mux in UART2 on altfunction C and set pull-ups.
 391          * TODO: is this used on U8500 variants and Snowball really?
 392          * The setting on GPIO31 conflicts with magnetometer use on hrefv60
 393          */
 394         /* default state for UART2 */
 395         DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
 396         DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
 397         DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
 398         /* Sleep state for UART2 */
 399         DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
 400         DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
 401         /*
 402          * The following pin sets were known as "runtime pins" before being
 403          * converted to the pinctrl model. Here we model them as "default"
 404          * states.
 405          */
 406         /* Mux in UART0 after initialization */
 407         DB8500_MUX("u0_a_1", "u0", "uart0"),
 408         DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
 409         DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
 410         DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
 411         DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
 412         /* Sleep state for UART0 */
 413         DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
 414         DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
 415         DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
 416         DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
 417         /* Mux in UART1 after initialization */
 418         DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
 419         DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
 420         DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
 421         /* Sleep state for UART1 */
 422         DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
 423         DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
 424         /* MSP1 for ALSA codec */
 425         DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
 426         DB8500_MUX_HOG("msp1_a_1", "msp1"),
 427         DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
 428         DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
 429         DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
 430         DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
 431         /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
 432         DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
 433         DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
 434         /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
 435         DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
 436         DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
 437         /* LCD VSI1 sleep state */
 438         DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
 439         /* Mux in i2c0 block, default state */
 440         DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
 441         /* i2c0 sleep state */
 442         DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
 443         DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
 444         /* Mux in i2c1 block, default state  */
 445         DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
 446         /* i2c1 sleep state */
 447         DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
 448         DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
 449         /* Mux in i2c2 block, default state  */
 450         DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
 451         /* i2c2 sleep state */
 452         DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
 453         DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
 454         /* Mux in i2c3 block, default state  */
 455         DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
 456         /* i2c3 sleep state */
 457         DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
 458         DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
 459         /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
 460         DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
 461         DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
 462         DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
 463         DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
 464         DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
 465         DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
 466         DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
 467         DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
 468         DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
 469         DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
 470         DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
 471         /* SDI0 sleep state */
 472         DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
 473         DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
 474         DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
 475         DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
 476         DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
 477         DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
 478         DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
 479         DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
 480         DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
 481         DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
 482
 483         /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
 484         DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
 485         DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
 486         DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
 487         DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
 488         DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
 489         DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
 490         DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
 491         DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
 492         /* SDI1 sleep state */
 493         DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
 494         DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
 495         DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
 496         DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
 497         DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
 498         DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
 499         DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
 500
 501         /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
 502         DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
 503         DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
 504         DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
 505         DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
 506         DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
 507         DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
 508         DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
 509         DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
 510         DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
 511         DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
 512         DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
 513         DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
 514         /* SDI2 sleep state */
 515         DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
 516         DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
 517         DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
 518         DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
 519         DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
 520         DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
 521         DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
 522         DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
 523         DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
 524         DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
 525         DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
 526
 527         /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
 528         DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
 529         DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
 530         DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
 531         DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
 532         DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
 533         DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
 534         DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
 535         DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
 536         DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
 537         DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
 538         DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
 539         DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
 540         /*SDI4 sleep state */
 541         DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
 542         DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
 543         DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
 544         DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
 545         DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
 546         DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
 547         DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
 548         DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
 549         DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
 550         DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
 551         DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
 552
 553         /* Mux in USB pins, drive STP high */
 554         /* USB default state */
 555         DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
 556         DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
 557         /* USB sleep state */
 558         DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
 559         DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
 560         DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
 561         DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
 562         DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
 563         DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
 564         DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
 565         DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
 566         DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
 567         DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
 568         DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
 569         DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
 570
 571         /* Mux in SPI2 pins on the "other C1" altfunction */
 572         DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
 573         DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
 574         DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
 575         DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
 576         DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
 577         /* SPI2 idle state */
 578         DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
 579         DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
 580         DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
 581         /* SPI2 sleep state */
 582         DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
 583         DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
 584         DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
 585         DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
 586
 587         /* ske default state */
 588         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 589         DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
 590         DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
 591         DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
 592         DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
 593         DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
 594         DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
 595         DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
 596         DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
 597         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 598         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 599         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 600         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 601         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 602         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 603         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 604         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 605         /* ske sleep state */
 606         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 607         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 608         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 609         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 610         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 611         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 612         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 613         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 614         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 615         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 616         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 617         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 618         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 619         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 620         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 621         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 622
 623         /* STM APE pins states */
 624         DB8500_MUX_STATE("stmape_c_1", "stmape",
 625                 "stm", "ape_mipi34"),
 626         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 627                 "stm", "ape_mipi34"), /* clk */
 628         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 629                 "stm", "ape_mipi34"), /* dat3 */
 630         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 631                 "stm", "ape_mipi34"), /* dat2 */
 632         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 633                 "stm", "ape_mipi34"), /* dat1 */
 634         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 635                 "stm", "ape_mipi34"), /* dat0 */
 636
 637         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 638                 "stm", "ape_mipi34_sleep"), /* clk */
 639         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 640                 "stm", "ape_mipi34_sleep"), /* dat3 */
 641         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 642                 "stm", "ape_mipi34_sleep"), /* dat2 */
 643         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 644                 "stm", "ape_mipi34_sleep"), /* dat1 */
 645         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 646                 "stm", "ape_mipi34_sleep"), /* dat0 */
 647
 648         DB8500_MUX_STATE("stmape_oc1_1", "stmape",
 649                 "stm", "ape_microsd"),
 650         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 651                 "stm", "ape_microsd"), /* clk */
 652         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 653                 "stm", "ape_microsd"), /* dat0 */
 654         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 655                 "stm", "ape_microsd"), /* dat1 */
 656         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 657                 "stm", "ape_microsd"), /* dat2 */
 658         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 659                 "stm", "ape_microsd"), /* dat3 */
 660
 661         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 662                 "stm", "ape_microsd_sleep"), /* clk */
 663         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 664                 "stm", "ape_microsd_sleep"), /* dat0 */
 665         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 666                 "stm", "ape_microsd_sleep"), /* dat1 */
 667         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 668                 "stm", "ape_microsd_sleep"), /* dat2 */
 669         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 670                 "stm", "ape_microsd_sleep"), /* dat3 */
 671
 672         /*  STM Modem pins states */
 673         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 674                 "stm", "mod_mipi34"),
 675         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 676                 "stm", "mod_mipi34"),
 677         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 678                 "stm", "mod_mipi34"),
 679         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 680                 "stm", "mod_mipi34"), /* clk */
 681         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 682                 "stm", "mod_mipi34"), /* dat3 */
 683         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 684                 "stm", "mod_mipi34"), /* dat2 */
 685         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 686                 "stm", "mod_mipi34"), /* dat1 */
 687         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 688                 "stm", "mod_mipi34"), /* dat0 */
 689         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 690                 "stm", "mod_mipi34"), /* uartmod rx */
 691         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 692                 "stm", "mod_mipi34"), /* uartmod tx */
 693
 694         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 695                 "stm", "mod_mipi34_sleep"), /* clk */
 696         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 697                 "stm", "mod_mipi34_sleep"), /* dat3 */
 698         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 699                 "stm", "mod_mipi34_sleep"), /* dat2 */
 700         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 701                 "stm", "mod_mipi34_sleep"), /* dat1 */
 702         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 703                 "stm", "mod_mipi34_sleep"), /* dat0 */
 704         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 705                 "stm", "mod_mipi34_sleep"), /* uartmod rx */
 706         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 707                 "stm", "mod_mipi34_sleep"), /* uartmod tx */
 708
 709         DB8500_MUX_STATE("stmmod_b_1", "stmmod",
 710                 "stm", "mod_microsd"),
 711         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 712                 "stm", "mod_microsd"),
 713         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 714                 "stm", "mod_microsd"),
 715         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 716                 "stm", "mod_microsd"), /* clk */
 717         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 718                 "stm", "mod_microsd"), /* dat0 */
 719         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 720                 "stm", "mod_microsd"), /* dat1 */
 721         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 722                 "stm", "mod_microsd"), /* dat2 */
 723         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 724                 "stm", "mod_microsd"), /* dat3 */
 725         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 726                 "stm", "mod_microsd"), /* uartmod rx */
 727         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 728                 "stm", "mod_microsd"), /* uartmod tx */
 729
 730         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 731                 "stm", "mod_microsd_sleep"), /* clk */
 732         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 733                 "stm", "mod_microsd_sleep"), /* dat0 */
 734         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 735                 "stm", "mod_microsd_sleep"), /* dat1 */
 736         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 737                 "stm", "mod_microsd_sleep"), /* dat2 */
 738         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 739                 "stm", "mod_microsd_sleep"), /* dat3 */
 740         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 741                 "stm", "mod_microsd_sleep"), /* uartmod rx */
 742         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 743                 "stm", "mod_microsd_sleep"), /* uartmod tx */
 744
 745         /*  STM dual Modem/APE pins state */
 746         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 747                 "stm", "mod_mipi34_ape_mipi60"),
 748         DB8500_MUX_STATE("stmape_c_2", "stmape",
 749                 "stm", "mod_mipi34_ape_mipi60"),
 750         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 751                 "stm", "mod_mipi34_ape_mipi60"),
 752         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 753                 "stm", "mod_mipi34_ape_mipi60"),
 754         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 755                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 756         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 757                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 758         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 759                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 760         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 761                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 762         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 763                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 764         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 765                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
 766         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 767                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
 768         DB8500_PIN_STATE("GPIO155_C19", in_nopull,
 769                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 770         DB8500_PIN_STATE("GPIO156_C17", in_nopull,
 771                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 772         DB8500_PIN_STATE("GPIO157_A18", in_nopull,
 773                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 774         DB8500_PIN_STATE("GPIO158_C18", in_nopull,
 775                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 776         DB8500_PIN_STATE("GPIO159_B19", in_nopull,
 777                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 778
 779         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 780                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 781         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 782                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 783         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 784                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 785         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 786                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 787         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 788                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 789         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 790                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
 791         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 792                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
 793         DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
 794                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 795         DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
 796                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 797         DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
 798                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 799         DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
 800                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 801         DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
 802                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 803 };
 804
 805 /*
 806  * These are specifically for the MOP500 and HREFP (pre-v60) version of the
 807  * board, which utilized a TC35892 GPIO expander instead of using a lot of
 808  * on-chip pins as the HREFv60 and later does.
 809  */
 810 static struct pinctrl_map __initdata mop500_pinmap[] = {
 811         /* Mux in SSP0, pull down RXD pin */
 812         DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
 813         DB8500_PIN_HOG("GPIO145_C13", pd),
 814         /*
 815          * XENON Flashgun on image processor GPIO (controlled from image
 816          * processor firmware), mux in these image processor GPIO lines 0
 817          * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
 818          * the pins.
 819          */
 820         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 821         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 822         DB8500_PIN_HOG("GPIO6_AF6", in_pu),
 823         DB8500_PIN_HOG("GPIO7_AG5", in_pu),
 824         /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
 825         DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
 826         /* Mux in UART1 and set the pull-ups */
 827         DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
 828         DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
 829         DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
 830         /*
 831          * Runtime stuff: make it possible to mux in the SKE keypad
 832          * and bias the pins
 833          */
 834         /* ske default state */
 835         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 836         DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
 837         DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
 838         DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
 839         DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
 840         DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
 841         DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
 842         DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
 843         DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
 844         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 845         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 846         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 847         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 848         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 849         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 850         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 851         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 852         /* ske sleep state */
 853         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 854         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 855         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 856         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 857         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 858         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 859         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 860         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 861         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 862         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 863         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 864         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 865         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 866         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 867         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 868         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 869
 870         /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
 871         DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
 872         DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
 873 };
 874
 875 /*
 876  * The HREFv60 series of platforms is using available pins on the DB8500
 877  * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
 878  * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
 879  */
 880 static struct pinctrl_map __initdata hrefv60_pinmap[] = {
 881         /* Drive WLAN_ENA low */
 882         DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
 883         /*
 884          * XENON Flashgun on image processor GPIO (controlled from image
 885          * processor firmware), mux in these image processor GPIO lines 0
 886          * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
 887          * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
 888          * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
 889          */
 890         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 891         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 892         DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
 893         DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
 894         DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
 895         DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
 896         DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
 897         /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
 898         DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
 899         DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
 900         /*
 901          * Display Interface 1 uses GPIO 65 for RST (reset).
 902          * Display Interface 2 uses GPIO 66 for RST (reset).
 903          * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
 904          */
 905         DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
 906         DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
 907         /*
 908          * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
 909          * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
 910          * reset signals low.
 911          */
 912         DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
 913         DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
 914         DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
 915         /*
 916          * Drive D19-D23 for the ETM PTM trace interface low,
 917          * (presumably pins are unconnected therefore grounded here,
 918          * the "other alt C1" setting enables these pins)
 919          */
 920         DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
 921         DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
 922         DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
 923         DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
 924         DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
 925         /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
 926         DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
 927         DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
 928         /* NFC ENA and RESET to low, pulldown IRQ line */
 929         DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
 930         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
 931         DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
 932         /*
 933          * SKE keyboard partly on alt A and partly on "Other alt C1"
 934          * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
 935          * rows of 6 keys, then pull up force sensing interrup and
 936          * drive reset and force sensing WU low.
 937          */
 938         DB8500_MUX_HOG("kp_a_1", "kp"),
 939         DB8500_MUX_HOG("kp_oc1_1", "kp"),
 940         DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
 941         DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
 942         DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
 943         DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
 944         DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
 945         DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
 946         DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
 947         DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
 948         DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
 949         DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
 950         DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
 951         /* DiPro Sensor interrupt */
 952         DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
 953         /* Audio Amplifier HF enable */
 954         DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
 955         /* GBF interface, pull low to reset state */
 956         DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
 957         /* MSP : HDTV INTERFACE GPIO line */
 958         DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
 959         /* Accelerometer interrupt lines */
 960         DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
 961         DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
 962         /* SD card detect GPIO pin */
 963         DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
 964         /*
 965          * Runtime stuff
 966          * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
 967          * etc.
 968          */
 969         DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 970         DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
 971         DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 972 };
 973
 974 static struct pinctrl_map __initdata u9500_pinmap[] = {
 975         /* Mux in UART1 (just RX/TX) and set the pull-ups */
 976         DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
 977         DB8500_PIN_HOG("GPIO4_AH6", in_pu),
 978         DB8500_PIN_HOG("GPIO5_AG6", out_hi),
 979         /* WLAN_IRQ line */
 980         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
 981         /* HSI */
 982         DB8500_MUX_HOG("hsir_a_1", "hsi"),
 983         DB8500_MUX_HOG("hsit_a_2", "hsi"),
 984         DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
 985         DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
 986         DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
 987         DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
 988         DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
 989         DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
 990         DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
 991         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
 992 };
 993
 994 static struct pinctrl_map __initdata u8500_pinmap[] = {
 995         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
 996         DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
 997 };
 998
 999 static struct pinctrl_map __initdata snowball_pinmap[] = {
1000         /* Mux in SSP0 connected to AB8500, pull down RXD pin */
1001         DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
1002         DB8500_PIN_HOG("GPIO145_C13", pd),
1003         /* Always drive the MC0 DAT31DIR line high on these boards */
1004         DB8500_PIN_HOG("GPIO21_AB3", out_hi),
1005         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
1006         DB8500_MUX_HOG("sm_b_1", "sm"),
1007         /* User LED */
1008         DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
1009         /* Drive RSTn_LAN high */
1010         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
1011         /*  Accelerometer/Magnetometer */
1012         DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
1013         DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
1014         DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
1015         /* WLAN/GBF */
1016         DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
1017         DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
1018         DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
1019         DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
1020 };
1021
1022 /*
1023  * passing "pinsfor=" in kernel cmdline allows for custom
1024  * configuration of GPIOs on u8500 derived boards.
1025  */
1026 static int __init early_pinsfor(char *p)
1027 {
1028         pinsfor = PINS_FOR_DEFAULT;
1029
1030         if (strcmp(p, "u9500-21") == 0)
1031                 pinsfor = PINS_FOR_U9500;
1032
1033         return 0;
1034 }
1035 early_param("pinsfor", early_pinsfor);
1036
1037 int pins_for_u9500(void)
1038 {
1039         if (pinsfor == PINS_FOR_U9500)
1040                 return 1;
1041
1042         return 0;
1043 }
1044
1045 static void __init mop500_href_family_pinmaps_init(void)
1046 {
1047         switch (pinsfor) {
1048         case PINS_FOR_U9500:
1049                 pinctrl_register_mappings(u9500_pinmap,
1050                                           ARRAY_SIZE(u9500_pinmap));
1051                 break;
1052         case PINS_FOR_DEFAULT:
1053                 pinctrl_register_mappings(u8500_pinmap,
1054                                           ARRAY_SIZE(u8500_pinmap));
1055         default:
1056                 break;
1057         }
1058 }
1059
1060 void __init mop500_pinmaps_init(void)
1061 {
1062         pinctrl_register_mappings(mop500_family_pinmap,
1063                                   ARRAY_SIZE(mop500_family_pinmap));
1064         pinctrl_register_mappings(mop500_pinmap,
1065                                   ARRAY_SIZE(mop500_pinmap));
1066         mop500_href_family_pinmaps_init();
1067         if (machine_is_u8520())
1068                 pinctrl_register_mappings(ab8505_pinmap,
1069                                           ARRAY_SIZE(ab8505_pinmap));
1070         else
1071                 pinctrl_register_mappings(ab8500_pinmap,
1072                                           ARRAY_SIZE(ab8500_pinmap));
1073 }
1074
1075 void __init snowball_pinmaps_init(void)
1076 {
1077         pinctrl_register_mappings(mop500_family_pinmap,
1078                                   ARRAY_SIZE(mop500_family_pinmap));
1079         pinctrl_register_mappings(snowball_pinmap,
1080                                   ARRAY_SIZE(snowball_pinmap));
1081         pinctrl_register_mappings(u8500_pinmap,
1082                                   ARRAY_SIZE(u8500_pinmap));
1083         pinctrl_register_mappings(ab8500_pinmap,
1084                                   ARRAY_SIZE(ab8500_pinmap));
1085 }
1086
1087 void __init hrefv60_pinmaps_init(void)
1088 {
1089         pinctrl_register_mappings(mop500_family_pinmap,
1090                                   ARRAY_SIZE(mop500_family_pinmap));
1091         pinctrl_register_mappings(hrefv60_pinmap,
1092                                   ARRAY_SIZE(hrefv60_pinmap));
1093         mop500_href_family_pinmaps_init();
1094         pinctrl_register_mappings(ab8500_pinmap,
1095                                   ARRAY_SIZE(ab8500_pinmap));
1096 }