2 * Copyright (C) 2002 ARM Ltd.
3 * Copyright (C) 2008 STMicroelctronics.
4 * Copyright (C) 2009 ST-Ericsson.
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
7 * This file is based on arm realview platform
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/errno.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/smp.h>
20 #include <linux/of_address.h>
22 #include <asm/cacheflush.h>
23 #include <asm/smp_plat.h>
24 #include <asm/smp_scu.h>
28 #include "db8500-regs.h"
31 static void __iomem *scu_base;
32 static void __iomem *backupram;
34 /* This is called from headsmp.S to wakeup the secondary core */
35 extern void u8500_secondary_startup(void);
38 * Write pen_release in a way that is guaranteed to be visible to all
39 * observers, irrespective of whether they're taking part in coherency
40 * or not. This is necessary for the hotplug code to work reliably.
42 static void write_pen_release(int val)
46 sync_cache_w(&pen_release);
49 static DEFINE_SPINLOCK(boot_lock);
51 static void ux500_secondary_init(unsigned int cpu)
54 * let the primary processor know we're out of the
55 * pen, then head off into the C entry point
57 write_pen_release(-1);
60 * Synchronise with the boot thread.
62 spin_lock(&boot_lock);
63 spin_unlock(&boot_lock);
66 static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
68 unsigned long timeout;
71 * set synchronisation state between this boot processor
72 * and the secondary one
74 spin_lock(&boot_lock);
77 * The secondary processor is waiting to be released from
78 * the holding pen - release it, then wait for it to flag
79 * that it has been released by resetting pen_release.
81 write_pen_release(cpu_logical_map(cpu));
83 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
85 timeout = jiffies + (1 * HZ);
86 while (time_before(jiffies, timeout)) {
87 if (pen_release == -1)
92 * now the secondary core is starting up let it run its
93 * calibrations, then wait for it to finish
95 spin_unlock(&boot_lock);
97 return pen_release != -1 ? -ENOSYS : 0;
100 static void __init wakeup_secondary(void)
103 * write the address of secondary startup into the backup ram register
104 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
105 * backup ram register at offset 0x1FF0, which is what boot rom code
106 * is waiting for. This would wake up the secondary core from WFE
108 #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
109 __raw_writel(virt_to_phys(u8500_secondary_startup),
110 backupram + UX500_CPU1_JUMPADDR_OFFSET);
112 #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
113 __raw_writel(0xA1FEED01,
114 backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
116 /* make sure write buffer is drained */
121 * Initialise the CPU possible map early - this describes the CPUs
122 * which may be present or become present in the system.
124 static void __init ux500_smp_init_cpus(void)
126 unsigned int i, ncores;
127 struct device_node *np;
129 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
130 scu_base = of_iomap(np, 0);
134 backupram = ioremap(U8500_BACKUPRAM0_BASE, SZ_8K);
135 ncores = scu_get_core_count(scu_base);
138 if (ncores > nr_cpu_ids) {
139 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
144 for (i = 0; i < ncores; i++)
145 set_cpu_possible(i, true);
148 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
150 scu_enable(scu_base);
154 struct smp_operations ux500_smp_ops __initdata = {
155 .smp_init_cpus = ux500_smp_init_cpus,
156 .smp_prepare_cpus = ux500_smp_prepare_cpus,
157 .smp_secondary_init = ux500_secondary_init,
158 .smp_boot_secondary = ux500_boot_secondary,
159 #ifdef CONFIG_HOTPLUG_CPU
160 .cpu_die = ux500_cpu_die,