2 * linux/arch/arm/mach-vexpress/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/jiffies.h>
16 #include <linux/smp.h>
19 #include <asm/cacheflush.h>
20 #include <asm/smp_scu.h>
21 #include <asm/unified.h>
23 #include <mach/ct-ca9x4.h>
24 #include <mach/motherboard.h>
25 #define V2M_PA_CS7 0x10000000
29 extern void vexpress_secondary_startup(void);
32 * control for which core is the next to come out of the secondary
35 volatile int __cpuinitdata pen_release = -1;
37 static void __iomem *scu_base_addr(void)
39 return MMIO_P2V(A9_MPCORE_SCU);
42 static DEFINE_SPINLOCK(boot_lock);
44 void __cpuinit platform_secondary_init(unsigned int cpu)
49 * if any interrupts are already enabled for the primary
50 * core (e.g. timer irq), then they will not have been enabled
53 gic_cpu_init(0, gic_cpu_base_addr);
56 * let the primary processor know we're out of the
57 * pen, then head off into the C entry point
63 * Synchronise with the boot thread.
65 spin_lock(&boot_lock);
66 spin_unlock(&boot_lock);
69 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
71 unsigned long timeout;
74 * Set synchronisation state between this boot processor
75 * and the secondary one
77 spin_lock(&boot_lock);
80 * This is really belt and braces; we hold unintended secondary
81 * CPUs in the holding pen until we're ready for them. However,
82 * since we haven't sent them a soft interrupt, they shouldn't
86 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
87 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
90 * Send the secondary CPU a soft interrupt, thereby causing
91 * the boot monitor to read the system wide flags register,
92 * and branch to the address found there.
94 smp_cross_call(cpumask_of(cpu), 1);
96 timeout = jiffies + (1 * HZ);
97 while (time_before(jiffies, timeout)) {
99 if (pen_release == -1)
106 * now the secondary core is starting up let it run its
107 * calibrations, then wait for it to finish
109 spin_unlock(&boot_lock);
111 return pen_release != -1 ? -ENOSYS : 0;
115 * Initialise the CPU possible map early - this describes the CPUs
116 * which may be present or become present in the system.
118 void __init smp_init_cpus(void)
120 void __iomem *scu_base = scu_base_addr();
121 unsigned int i, ncores;
123 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
126 if (ncores > NR_CPUS) {
128 "vexpress: no. of cores (%d) greater than configured "
129 "maximum of %d - clipping\n",
134 for (i = 0; i < ncores; i++)
135 set_cpu_possible(i, true);
138 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
143 * Initialise the present map, which describes the set of CPUs
144 * actually populated at the present time.
146 for (i = 0; i < max_cpus; i++)
147 set_cpu_present(i, true);
149 scu_enable(scu_base_addr());
152 * Write the address of secondary startup into the
153 * system-wide flags register. The boot monitor waits
154 * until it receives a soft interrupt, and then the
155 * secondary CPU branches to this address.
157 writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
158 writel(BSYM(virt_to_phys(vexpress_secondary_startup)),
159 MMIO_P2V(V2M_SYS_FLAGSSET));