arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  19  * Converted DMA library into DMA platform driver.
  20  *      - G, Manjunath Kondaiah <manjugk@ti.com>
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License version 2 as
  24  * published by the Free Software Foundation.
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/sched.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/errno.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/irq.h>
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38
  39 #include <linux/omap-dma.h>
  40
  41 /*
  42  * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
  43  * channels that an instance of the SDMA IP block can support.  Used
  44  * to size arrays.  (The actual maximum on a particular SoC may be less
  45  * than this -- for example, OMAP1 SDMA instances only support 17 logical
  46  * DMA channels.)
  47  */
  48 #define MAX_LOGICAL_DMA_CH_COUNT                32
  49
  50 #undef DEBUG
  51
  52 #ifndef CONFIG_ARCH_OMAP1
  53 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  54         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  55 };
  56
  57 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  58 #endif
  59
  60 #define OMAP_DMA_ACTIVE                 0x01
  61 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
  62
  63 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  64
  65 static struct omap_system_dma_plat_info *p;
  66 static struct omap_dma_dev_attr *d;
  67
  68 static int enable_1510_mode;
  69 static u32 errata;
  70
  71 static struct omap_dma_global_context_registers {
  72         u32 dma_irqenable_l0;
  73         u32 dma_irqenable_l1;
  74         u32 dma_ocp_sysconfig;
  75         u32 dma_gcr;
  76 } omap_dma_global_context;
  77
  78 struct dma_link_info {
  79         int *linked_dmach_q;
  80         int no_of_lchs_linked;
  81
  82         int q_count;
  83         int q_tail;
  84         int q_head;
  85
  86         int chain_state;
  87         int chain_mode;
  88
  89 };
  90
  91 static struct dma_link_info *dma_linked_lch;
  92
  93 #ifndef CONFIG_ARCH_OMAP1
  94
  95 /* Chain handling macros */
  96 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  97         do {                                                            \
  98                 dma_linked_lch[chain_id].q_head =                       \
  99                 dma_linked_lch[chain_id].q_tail =                       \
 100                 dma_linked_lch[chain_id].q_count = 0;                   \
 101         } while (0)
 102 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 103                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 104                 dma_linked_lch[chain_id].q_count)
 105 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 106         do {                                                            \
 107                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 108                 dma_linked_lch[chain_id].q_count)                       \
 109         } while (0)
 110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 111                 (0 == dma_linked_lch[chain_id].q_count)
 112 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 113         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 115         do {                                                            \
 116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 117                 dma_linked_lch[chain_id].q_count--;                     \
 118         } while (0)
 119
 120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 121         do {                                                            \
 122                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 123                 dma_linked_lch[chain_id].q_count++; \
 124         } while (0)
 125 #endif
 126
 127 static int dma_lch_count;
 128 static int dma_chan_count;
 129 static int omap_dma_reserve_channels;
 130
 131 static spinlock_t dma_chan_lock;
 132 static struct omap_dma_lch *dma_chan;
 133
 134 static inline void disable_lnk(int lch);
 135 static void omap_disable_channel_irq(int lch);
 136 static inline void omap_enable_channel_irq(int lch);
 137
 138 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 139                                                 __func__);
 140
 141 #ifdef CONFIG_ARCH_OMAP15XX
 142 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 143 static int omap_dma_in_1510_mode(void)
 144 {
 145         return enable_1510_mode;
 146 }
 147 #else
 148 #define omap_dma_in_1510_mode()         0
 149 #endif
 150
 151 #ifdef CONFIG_ARCH_OMAP1
 152 static inline int get_gdma_dev(int req)
 153 {
 154         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 155         int shift = ((req - 1) % 5) * 6;
 156
 157         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 158 }
 159
 160 static inline void set_gdma_dev(int req, int dev)
 161 {
 162         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 163         int shift = ((req - 1) % 5) * 6;
 164         u32 l;
 165
 166         l = omap_readl(reg);
 167         l &= ~(0x3f << shift);
 168         l |= (dev - 1) << shift;
 169         omap_writel(l, reg);
 170 }
 171 #else
 172 #define set_gdma_dev(req, dev)  do {} while (0)
 173 #define omap_readl(reg)         0
 174 #define omap_writel(val, reg)   do {} while (0)
 175 #endif
 176
 177 #ifdef CONFIG_ARCH_OMAP1
 178 void omap_set_dma_priority(int lch, int dst_port, int priority)
 179 {
 180         unsigned long reg;
 181         u32 l;
 182
 183         if (dma_omap1()) {
 184                 switch (dst_port) {
 185                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 186                         reg = OMAP_TC_OCPT1_PRIOR;
 187                         break;
 188                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 189                         reg = OMAP_TC_OCPT2_PRIOR;
 190                         break;
 191                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 192                         reg = OMAP_TC_EMIFF_PRIOR;
 193                         break;
 194                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 195                         reg = OMAP_TC_EMIFS_PRIOR;
 196                         break;
 197                 default:
 198                         BUG();
 199                         return;
 200                 }
 201                 l = omap_readl(reg);
 202                 l &= ~(0xf << 8);
 203                 l |= (priority & 0xf) << 8;
 204                 omap_writel(l, reg);
 205         }
 206 }
 207 #endif
 208
 209 #ifdef CONFIG_ARCH_OMAP2PLUS
 210 void omap_set_dma_priority(int lch, int dst_port, int priority)
 211 {
 212         u32 ccr;
 213
 214         ccr = p->dma_read(CCR, lch);
 215         if (priority)
 216                 ccr |= (1 << 6);
 217         else
 218                 ccr &= ~(1 << 6);
 219         p->dma_write(ccr, CCR, lch);
 220 }
 221 #endif
 222 EXPORT_SYMBOL(omap_set_dma_priority);
 223
 224 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 225                                   int frame_count, int sync_mode,
 226                                   int dma_trigger, int src_or_dst_synch)
 227 {
 228         u32 l;
 229
 230         l = p->dma_read(CSDP, lch);
 231         l &= ~0x03;
 232         l |= data_type;
 233         p->dma_write(l, CSDP, lch);
 234
 235         if (dma_omap1()) {
 236                 u16 ccr;
 237
 238                 ccr = p->dma_read(CCR, lch);
 239                 ccr &= ~(1 << 5);
 240                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 241                         ccr |= 1 << 5;
 242                 p->dma_write(ccr, CCR, lch);
 243
 244                 ccr = p->dma_read(CCR2, lch);
 245                 ccr &= ~(1 << 2);
 246                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 247                         ccr |= 1 << 2;
 248                 p->dma_write(ccr, CCR2, lch);
 249         }
 250
 251         if (dma_omap2plus() && dma_trigger) {
 252                 u32 val;
 253
 254                 val = p->dma_read(CCR, lch);
 255
 256                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 257                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
 258                 val |= (dma_trigger & ~0x1f) << 14;
 259                 val |= dma_trigger & 0x1f;
 260
 261                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 262                         val |= 1 << 5;
 263                 else
 264                         val &= ~(1 << 5);
 265
 266                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 267                         val |= 1 << 18;
 268                 else
 269                         val &= ~(1 << 18);
 270
 271                 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
 272                         val &= ~(1 << 24);      /* dest synch */
 273                         val |= (1 << 23);       /* Prefetch */
 274                 } else if (src_or_dst_synch) {
 275                         val |= 1 << 24;         /* source synch */
 276                 } else {
 277                         val &= ~(1 << 24);      /* dest synch */
 278                 }
 279                 p->dma_write(val, CCR, lch);
 280         }
 281
 282         p->dma_write(elem_count, CEN, lch);
 283         p->dma_write(frame_count, CFN, lch);
 284 }
 285 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 286
 287 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 288 {
 289         BUG_ON(omap_dma_in_1510_mode());
 290
 291         if (dma_omap1()) {
 292                 u16 w;
 293
 294                 w = p->dma_read(CCR2, lch);
 295                 w &= ~0x03;
 296
 297                 switch (mode) {
 298                 case OMAP_DMA_CONSTANT_FILL:
 299                         w |= 0x01;
 300                         break;
 301                 case OMAP_DMA_TRANSPARENT_COPY:
 302                         w |= 0x02;
 303                         break;
 304                 case OMAP_DMA_COLOR_DIS:
 305                         break;
 306                 default:
 307                         BUG();
 308                 }
 309                 p->dma_write(w, CCR2, lch);
 310
 311                 w = p->dma_read(LCH_CTRL, lch);
 312                 w &= ~0x0f;
 313                 /* Default is channel type 2D */
 314                 if (mode) {
 315                         p->dma_write(color, COLOR, lch);
 316                         w |= 1;         /* Channel type G */
 317                 }
 318                 p->dma_write(w, LCH_CTRL, lch);
 319         }
 320
 321         if (dma_omap2plus()) {
 322                 u32 val;
 323
 324                 val = p->dma_read(CCR, lch);
 325                 val &= ~((1 << 17) | (1 << 16));
 326
 327                 switch (mode) {
 328                 case OMAP_DMA_CONSTANT_FILL:
 329                         val |= 1 << 16;
 330                         break;
 331                 case OMAP_DMA_TRANSPARENT_COPY:
 332                         val |= 1 << 17;
 333                         break;
 334                 case OMAP_DMA_COLOR_DIS:
 335                         break;
 336                 default:
 337                         BUG();
 338                 }
 339                 p->dma_write(val, CCR, lch);
 340
 341                 color &= 0xffffff;
 342                 p->dma_write(color, COLOR, lch);
 343         }
 344 }
 345 EXPORT_SYMBOL(omap_set_dma_color_mode);
 346
 347 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 348 {
 349         if (dma_omap2plus()) {
 350                 u32 csdp;
 351
 352                 csdp = p->dma_read(CSDP, lch);
 353                 csdp &= ~(0x3 << 16);
 354                 csdp |= (mode << 16);
 355                 p->dma_write(csdp, CSDP, lch);
 356         }
 357 }
 358 EXPORT_SYMBOL(omap_set_dma_write_mode);
 359
 360 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 361 {
 362         if (dma_omap1() && !dma_omap15xx()) {
 363                 u32 l;
 364
 365                 l = p->dma_read(LCH_CTRL, lch);
 366                 l &= ~0x7;
 367                 l |= mode;
 368                 p->dma_write(l, LCH_CTRL, lch);
 369         }
 370 }
 371 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 372
 373 /* Note that src_port is only for omap1 */
 374 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 375                              unsigned long src_start,
 376                              int src_ei, int src_fi)
 377 {
 378         u32 l;
 379
 380         if (dma_omap1()) {
 381                 u16 w;
 382
 383                 w = p->dma_read(CSDP, lch);
 384                 w &= ~(0x1f << 2);
 385                 w |= src_port << 2;
 386                 p->dma_write(w, CSDP, lch);
 387         }
 388
 389         l = p->dma_read(CCR, lch);
 390         l &= ~(0x03 << 12);
 391         l |= src_amode << 12;
 392         p->dma_write(l, CCR, lch);
 393
 394         p->dma_write(src_start, CSSA, lch);
 395
 396         p->dma_write(src_ei, CSEI, lch);
 397         p->dma_write(src_fi, CSFI, lch);
 398 }
 399 EXPORT_SYMBOL(omap_set_dma_src_params);
 400
 401 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 402 {
 403         omap_set_dma_transfer_params(lch, params->data_type,
 404                                      params->elem_count, params->frame_count,
 405                                      params->sync_mode, params->trigger,
 406                                      params->src_or_dst_synch);
 407         omap_set_dma_src_params(lch, params->src_port,
 408                                 params->src_amode, params->src_start,
 409                                 params->src_ei, params->src_fi);
 410
 411         omap_set_dma_dest_params(lch, params->dst_port,
 412                                  params->dst_amode, params->dst_start,
 413                                  params->dst_ei, params->dst_fi);
 414         if (params->read_prio || params->write_prio)
 415                 omap_dma_set_prio_lch(lch, params->read_prio,
 416                                       params->write_prio);
 417 }
 418 EXPORT_SYMBOL(omap_set_dma_params);
 419
 420 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 421 {
 422         if (dma_omap2plus())
 423                 return;
 424
 425         p->dma_write(eidx, CSEI, lch);
 426         p->dma_write(fidx, CSFI, lch);
 427 }
 428 EXPORT_SYMBOL(omap_set_dma_src_index);
 429
 430 void omap_set_dma_src_data_pack(int lch, int enable)
 431 {
 432         u32 l;
 433
 434         l = p->dma_read(CSDP, lch);
 435         l &= ~(1 << 6);
 436         if (enable)
 437                 l |= (1 << 6);
 438         p->dma_write(l, CSDP, lch);
 439 }
 440 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 441
 442 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 443 {
 444         unsigned int burst = 0;
 445         u32 l;
 446
 447         l = p->dma_read(CSDP, lch);
 448         l &= ~(0x03 << 7);
 449
 450         switch (burst_mode) {
 451         case OMAP_DMA_DATA_BURST_DIS:
 452                 break;
 453         case OMAP_DMA_DATA_BURST_4:
 454                 if (dma_omap2plus())
 455                         burst = 0x1;
 456                 else
 457                         burst = 0x2;
 458                 break;
 459         case OMAP_DMA_DATA_BURST_8:
 460                 if (dma_omap2plus()) {
 461                         burst = 0x2;
 462                         break;
 463                 }
 464                 /*
 465                  * not supported by current hardware on OMAP1
 466                  * w |= (0x03 << 7);
 467                  * fall through
 468                  */
 469         case OMAP_DMA_DATA_BURST_16:
 470                 if (dma_omap2plus()) {
 471                         burst = 0x3;
 472                         break;
 473                 }
 474                 /*
 475                  * OMAP1 don't support burst 16
 476                  * fall through
 477                  */
 478         default:
 479                 BUG();
 480         }
 481
 482         l |= (burst << 7);
 483         p->dma_write(l, CSDP, lch);
 484 }
 485 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 486
 487 /* Note that dest_port is only for OMAP1 */
 488 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 489                               unsigned long dest_start,
 490                               int dst_ei, int dst_fi)
 491 {
 492         u32 l;
 493
 494         if (dma_omap1()) {
 495                 l = p->dma_read(CSDP, lch);
 496                 l &= ~(0x1f << 9);
 497                 l |= dest_port << 9;
 498                 p->dma_write(l, CSDP, lch);
 499         }
 500
 501         l = p->dma_read(CCR, lch);
 502         l &= ~(0x03 << 14);
 503         l |= dest_amode << 14;
 504         p->dma_write(l, CCR, lch);
 505
 506         p->dma_write(dest_start, CDSA, lch);
 507
 508         p->dma_write(dst_ei, CDEI, lch);
 509         p->dma_write(dst_fi, CDFI, lch);
 510 }
 511 EXPORT_SYMBOL(omap_set_dma_dest_params);
 512
 513 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 514 {
 515         if (dma_omap2plus())
 516                 return;
 517
 518         p->dma_write(eidx, CDEI, lch);
 519         p->dma_write(fidx, CDFI, lch);
 520 }
 521 EXPORT_SYMBOL(omap_set_dma_dest_index);
 522
 523 void omap_set_dma_dest_data_pack(int lch, int enable)
 524 {
 525         u32 l;
 526
 527         l = p->dma_read(CSDP, lch);
 528         l &= ~(1 << 13);
 529         if (enable)
 530                 l |= 1 << 13;
 531         p->dma_write(l, CSDP, lch);
 532 }
 533 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 534
 535 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 536 {
 537         unsigned int burst = 0;
 538         u32 l;
 539
 540         l = p->dma_read(CSDP, lch);
 541         l &= ~(0x03 << 14);
 542
 543         switch (burst_mode) {
 544         case OMAP_DMA_DATA_BURST_DIS:
 545                 break;
 546         case OMAP_DMA_DATA_BURST_4:
 547                 if (dma_omap2plus())
 548                         burst = 0x1;
 549                 else
 550                         burst = 0x2;
 551                 break;
 552         case OMAP_DMA_DATA_BURST_8:
 553                 if (dma_omap2plus())
 554                         burst = 0x2;
 555                 else
 556                         burst = 0x3;
 557                 break;
 558         case OMAP_DMA_DATA_BURST_16:
 559                 if (dma_omap2plus()) {
 560                         burst = 0x3;
 561                         break;
 562                 }
 563                 /*
 564                  * OMAP1 don't support burst 16
 565                  * fall through
 566                  */
 567         default:
 568                 printk(KERN_ERR "Invalid DMA burst mode\n");
 569                 BUG();
 570                 return;
 571         }
 572         l |= (burst << 14);
 573         p->dma_write(l, CSDP, lch);
 574 }
 575 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 576
 577 static inline void omap_enable_channel_irq(int lch)
 578 {
 579         /* Clear CSR */
 580         if (dma_omap1())
 581                 p->dma_read(CSR, lch);
 582         else
 583                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 584
 585         /* Enable some nice interrupts. */
 586         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 587 }
 588
 589 static inline void omap_disable_channel_irq(int lch)
 590 {
 591         /* disable channel interrupts */
 592         p->dma_write(0, CICR, lch);
 593         /* Clear CSR */
 594         if (dma_omap1())
 595                 p->dma_read(CSR, lch);
 596         else
 597                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 598 }
 599
 600 void omap_enable_dma_irq(int lch, u16 bits)
 601 {
 602         dma_chan[lch].enabled_irqs |= bits;
 603 }
 604 EXPORT_SYMBOL(omap_enable_dma_irq);
 605
 606 void omap_disable_dma_irq(int lch, u16 bits)
 607 {
 608         dma_chan[lch].enabled_irqs &= ~bits;
 609 }
 610 EXPORT_SYMBOL(omap_disable_dma_irq);
 611
 612 static inline void enable_lnk(int lch)
 613 {
 614         u32 l;
 615
 616         l = p->dma_read(CLNK_CTRL, lch);
 617
 618         if (dma_omap1())
 619                 l &= ~(1 << 14);
 620
 621         /* Set the ENABLE_LNK bits */
 622         if (dma_chan[lch].next_lch != -1)
 623                 l = dma_chan[lch].next_lch | (1 << 15);
 624
 625 #ifndef CONFIG_ARCH_OMAP1
 626         if (dma_omap2plus())
 627                 if (dma_chan[lch].next_linked_ch != -1)
 628                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 629 #endif
 630
 631         p->dma_write(l, CLNK_CTRL, lch);
 632 }
 633
 634 static inline void disable_lnk(int lch)
 635 {
 636         u32 l;
 637
 638         l = p->dma_read(CLNK_CTRL, lch);
 639
 640         /* Disable interrupts */
 641         omap_disable_channel_irq(lch);
 642
 643         if (dma_omap1()) {
 644                 /* Set the STOP_LNK bit */
 645                 l |= 1 << 14;
 646         }
 647
 648         if (dma_omap2plus()) {
 649                 /* Clear the ENABLE_LNK bit */
 650                 l &= ~(1 << 15);
 651         }
 652
 653         p->dma_write(l, CLNK_CTRL, lch);
 654         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 655 }
 656
 657 static inline void omap2_enable_irq_lch(int lch)
 658 {
 659         u32 val;
 660         unsigned long flags;
 661
 662         if (dma_omap1())
 663                 return;
 664
 665         spin_lock_irqsave(&dma_chan_lock, flags);
 666         /* clear IRQ STATUS */
 667         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 668         /* Enable interrupt */
 669         val = p->dma_read(IRQENABLE_L0, lch);
 670         val |= 1 << lch;
 671         p->dma_write(val, IRQENABLE_L0, lch);
 672         spin_unlock_irqrestore(&dma_chan_lock, flags);
 673 }
 674
 675 static inline void omap2_disable_irq_lch(int lch)
 676 {
 677         u32 val;
 678         unsigned long flags;
 679
 680         if (dma_omap1())
 681                 return;
 682
 683         spin_lock_irqsave(&dma_chan_lock, flags);
 684         /* Disable interrupt */
 685         val = p->dma_read(IRQENABLE_L0, lch);
 686         val &= ~(1 << lch);
 687         p->dma_write(val, IRQENABLE_L0, lch);
 688         /* clear IRQ STATUS */
 689         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 690         spin_unlock_irqrestore(&dma_chan_lock, flags);
 691 }
 692
 693 int omap_request_dma(int dev_id, const char *dev_name,
 694                      void (*callback)(int lch, u16 ch_status, void *data),
 695                      void *data, int *dma_ch_out)
 696 {
 697         int ch, free_ch = -1;
 698         unsigned long flags;
 699         struct omap_dma_lch *chan;
 700
 701         WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine");
 702
 703         spin_lock_irqsave(&dma_chan_lock, flags);
 704         for (ch = 0; ch < dma_chan_count; ch++) {
 705                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 706                         free_ch = ch;
 707                         /* Exit after first free channel found */
 708                         break;
 709                 }
 710         }
 711         if (free_ch == -1) {
 712                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 713                 return -EBUSY;
 714         }
 715         chan = dma_chan + free_ch;
 716         chan->dev_id = dev_id;
 717
 718         if (p->clear_lch_regs)
 719                 p->clear_lch_regs(free_ch);
 720
 721         if (dma_omap2plus())
 722                 omap_clear_dma(free_ch);
 723
 724         spin_unlock_irqrestore(&dma_chan_lock, flags);
 725
 726         chan->dev_name = dev_name;
 727         chan->callback = callback;
 728         chan->data = data;
 729         chan->flags = 0;
 730
 731 #ifndef CONFIG_ARCH_OMAP1
 732         if (dma_omap2plus()) {
 733                 chan->chain_id = -1;
 734                 chan->next_linked_ch = -1;
 735         }
 736 #endif
 737
 738         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 739
 740         if (dma_omap1())
 741                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 742         else if (dma_omap2plus())
 743                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 744                         OMAP2_DMA_TRANS_ERR_IRQ;
 745
 746         if (dma_omap16xx()) {
 747                 /* If the sync device is set, configure it dynamically. */
 748                 if (dev_id != 0) {
 749                         set_gdma_dev(free_ch + 1, dev_id);
 750                         dev_id = free_ch + 1;
 751                 }
 752                 /*
 753                  * Disable the 1510 compatibility mode and set the sync device
 754                  * id.
 755                  */
 756                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
 757         } else if (dma_omap1()) {
 758                 p->dma_write(dev_id, CCR, free_ch);
 759         }
 760
 761         if (dma_omap2plus()) {
 762                 omap_enable_channel_irq(free_ch);
 763                 omap2_enable_irq_lch(free_ch);
 764         }
 765
 766         *dma_ch_out = free_ch;
 767
 768         return 0;
 769 }
 770 EXPORT_SYMBOL(omap_request_dma);
 771
 772 void omap_free_dma(int lch)
 773 {
 774         unsigned long flags;
 775
 776         if (dma_chan[lch].dev_id == -1) {
 777                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 778                        lch);
 779                 return;
 780         }
 781
 782         /* Disable interrupt for logical channel */
 783         if (dma_omap2plus())
 784                 omap2_disable_irq_lch(lch);
 785
 786         /* Disable all DMA interrupts for the channel. */
 787         omap_disable_channel_irq(lch);
 788
 789         /* Make sure the DMA transfer is stopped. */
 790         p->dma_write(0, CCR, lch);
 791
 792         /* Clear registers */
 793         if (dma_omap2plus())
 794                 omap_clear_dma(lch);
 795
 796         spin_lock_irqsave(&dma_chan_lock, flags);
 797         dma_chan[lch].dev_id = -1;
 798         dma_chan[lch].next_lch = -1;
 799         dma_chan[lch].callback = NULL;
 800         spin_unlock_irqrestore(&dma_chan_lock, flags);
 801 }
 802 EXPORT_SYMBOL(omap_free_dma);
 803
 804 /**
 805  * @brief omap_dma_set_global_params : Set global priority settings for dma
 806  *
 807  * @param arb_rate
 808  * @param max_fifo_depth
 809  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 810  *                                                 DMA_THREAD_RESERVE_ONET
 811  *                                                 DMA_THREAD_RESERVE_TWOT
 812  *                                                 DMA_THREAD_RESERVE_THREET
 813  */
 814 void
 815 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 816 {
 817         u32 reg;
 818
 819         if (dma_omap1()) {
 820                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 821                 return;
 822         }
 823
 824         if (max_fifo_depth == 0)
 825                 max_fifo_depth = 1;
 826         if (arb_rate == 0)
 827                 arb_rate = 1;
 828
 829         reg = 0xff & max_fifo_depth;
 830         reg |= (0x3 & tparams) << 12;
 831         reg |= (arb_rate & 0xff) << 16;
 832
 833         p->dma_write(reg, GCR, 0);
 834 }
 835 EXPORT_SYMBOL(omap_dma_set_global_params);
 836
 837 /**
 838  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 839  *
 840  * @param lch
 841  * @param read_prio - Read priority
 842  * @param write_prio - Write priority
 843  * Both of the above can be set with one of the following values :
 844  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 845  */
 846 int
 847 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 848                       unsigned char write_prio)
 849 {
 850         u32 l;
 851
 852         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 853                 printk(KERN_ERR "Invalid channel id\n");
 854                 return -EINVAL;
 855         }
 856         l = p->dma_read(CCR, lch);
 857         l &= ~((1 << 6) | (1 << 26));
 858         if (d->dev_caps & IS_RW_PRIORITY)
 859                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 860         else
 861                 l |= ((read_prio & 0x1) << 6);
 862
 863         p->dma_write(l, CCR, lch);
 864
 865         return 0;
 866 }
 867 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 868
 869 /*
 870  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 871  * through omap_start_dma(). Any buffers in flight are discarded.
 872  */
 873 void omap_clear_dma(int lch)
 874 {
 875         unsigned long flags;
 876
 877         local_irq_save(flags);
 878         p->clear_dma(lch);
 879         local_irq_restore(flags);
 880 }
 881 EXPORT_SYMBOL(omap_clear_dma);
 882
 883 void omap_start_dma(int lch)
 884 {
 885         u32 l;
 886
 887         /*
 888          * The CPC/CDAC register needs to be initialized to zero
 889          * before starting dma transfer.
 890          */
 891         if (dma_omap15xx())
 892                 p->dma_write(0, CPC, lch);
 893         else
 894                 p->dma_write(0, CDAC, lch);
 895
 896         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 897                 int next_lch, cur_lch;
 898                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 899
 900                 /* Set the link register of the first channel */
 901                 enable_lnk(lch);
 902
 903                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 904                 dma_chan_link_map[lch] = 1;
 905
 906                 cur_lch = dma_chan[lch].next_lch;
 907                 do {
 908                         next_lch = dma_chan[cur_lch].next_lch;
 909
 910                         /* The loop case: we've been here already */
 911                         if (dma_chan_link_map[cur_lch])
 912                                 break;
 913                         /* Mark the current channel */
 914                         dma_chan_link_map[cur_lch] = 1;
 915
 916                         enable_lnk(cur_lch);
 917                         omap_enable_channel_irq(cur_lch);
 918
 919                         cur_lch = next_lch;
 920                 } while (next_lch != -1);
 921         } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
 922                 p->dma_write(lch, CLNK_CTRL, lch);
 923
 924         omap_enable_channel_irq(lch);
 925
 926         l = p->dma_read(CCR, lch);
 927
 928         if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
 929                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
 930         l |= OMAP_DMA_CCR_EN;
 931
 932         /*
 933          * As dma_write() uses IO accessors which are weakly ordered, there
 934          * is no guarantee that data in coherent DMA memory will be visible
 935          * to the DMA device.  Add a memory barrier here to ensure that any
 936          * such data is visible prior to enabling DMA.
 937          */
 938         mb();
 939         p->dma_write(l, CCR, lch);
 940
 941         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 942 }
 943 EXPORT_SYMBOL(omap_start_dma);
 944
 945 void omap_stop_dma(int lch)
 946 {
 947         u32 l;
 948
 949         /* Disable all interrupts on the channel */
 950         omap_disable_channel_irq(lch);
 951
 952         l = p->dma_read(CCR, lch);
 953         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
 954                         (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
 955                 int i = 0;
 956                 u32 sys_cf;
 957
 958                 /* Configure No-Standby */
 959                 l = p->dma_read(OCP_SYSCONFIG, lch);
 960                 sys_cf = l;
 961                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 962                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
 963                 p->dma_write(l , OCP_SYSCONFIG, 0);
 964
 965                 l = p->dma_read(CCR, lch);
 966                 l &= ~OMAP_DMA_CCR_EN;
 967                 p->dma_write(l, CCR, lch);
 968
 969                 /* Wait for sDMA FIFO drain */
 970                 l = p->dma_read(CCR, lch);
 971                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
 972                                         OMAP_DMA_CCR_WR_ACTIVE))) {
 973                         udelay(5);
 974                         i++;
 975                         l = p->dma_read(CCR, lch);
 976                 }
 977                 if (i >= 100)
 978                         pr_err("DMA drain did not complete on lch %d\n", lch);
 979                 /* Restore OCP_SYSCONFIG */
 980                 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
 981         } else {
 982                 l &= ~OMAP_DMA_CCR_EN;
 983                 p->dma_write(l, CCR, lch);
 984         }
 985
 986         /*
 987          * Ensure that data transferred by DMA is visible to any access
 988          * after DMA has been disabled.  This is important for coherent
 989          * DMA regions.
 990          */
 991         mb();
 992
 993         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 994                 int next_lch, cur_lch = lch;
 995                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 996
 997                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 998                 do {
 999                         /* The loop case: we've been here already */
1000                         if (dma_chan_link_map[cur_lch])
1001                                 break;
1002                         /* Mark the current channel */
1003                         dma_chan_link_map[cur_lch] = 1;
1004
1005                         disable_lnk(cur_lch);
1006
1007                         next_lch = dma_chan[cur_lch].next_lch;
1008                         cur_lch = next_lch;
1009                 } while (next_lch != -1);
1010         }
1011
1012         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1013 }
1014 EXPORT_SYMBOL(omap_stop_dma);
1015
1016 /*
1017  * Allows changing the DMA callback function or data. This may be needed if
1018  * the driver shares a single DMA channel for multiple dma triggers.
1019  */
1020 int omap_set_dma_callback(int lch,
1021                           void (*callback)(int lch, u16 ch_status, void *data),
1022                           void *data)
1023 {
1024         unsigned long flags;
1025
1026         if (lch < 0)
1027                 return -ENODEV;
1028
1029         spin_lock_irqsave(&dma_chan_lock, flags);
1030         if (dma_chan[lch].dev_id == -1) {
1031                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1032                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1033                 return -EINVAL;
1034         }
1035         dma_chan[lch].callback = callback;
1036         dma_chan[lch].data = data;
1037         spin_unlock_irqrestore(&dma_chan_lock, flags);
1038
1039         return 0;
1040 }
1041 EXPORT_SYMBOL(omap_set_dma_callback);
1042
1043 /*
1044  * Returns current physical source address for the given DMA channel.
1045  * If the channel is running the caller must disable interrupts prior calling
1046  * this function and process the returned value before re-enabling interrupt to
1047  * prevent races with the interrupt handler. Note that in continuous mode there
1048  * is a chance for CSSA_L register overflow between the two reads resulting
1049  * in incorrect return value.
1050  */
1051 dma_addr_t omap_get_dma_src_pos(int lch)
1052 {
1053         dma_addr_t offset = 0;
1054
1055         if (dma_omap15xx())
1056                 offset = p->dma_read(CPC, lch);
1057         else
1058                 offset = p->dma_read(CSAC, lch);
1059
1060         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1061                 offset = p->dma_read(CSAC, lch);
1062
1063         if (!dma_omap15xx()) {
1064                 /*
1065                  * CDAC == 0 indicates that the DMA transfer on the channel has
1066                  * not been started (no data has been transferred so far).
1067                  * Return the programmed source start address in this case.
1068                  */
1069                 if (likely(p->dma_read(CDAC, lch)))
1070                         offset = p->dma_read(CSAC, lch);
1071                 else
1072                         offset = p->dma_read(CSSA, lch);
1073         }
1074
1075         if (dma_omap1())
1076                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1077
1078         return offset;
1079 }
1080 EXPORT_SYMBOL(omap_get_dma_src_pos);
1081
1082 /*
1083  * Returns current physical destination address for the given DMA channel.
1084  * If the channel is running the caller must disable interrupts prior calling
1085  * this function and process the returned value before re-enabling interrupt to
1086  * prevent races with the interrupt handler. Note that in continuous mode there
1087  * is a chance for CDSA_L register overflow between the two reads resulting
1088  * in incorrect return value.
1089  */
1090 dma_addr_t omap_get_dma_dst_pos(int lch)
1091 {
1092         dma_addr_t offset = 0;
1093
1094         if (dma_omap15xx())
1095                 offset = p->dma_read(CPC, lch);
1096         else
1097                 offset = p->dma_read(CDAC, lch);
1098
1099         /*
1100          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1101          * read before the DMA controller finished disabling the channel.
1102          */
1103         if (!dma_omap15xx() && offset == 0) {
1104                 offset = p->dma_read(CDAC, lch);
1105                 /*
1106                  * CDAC == 0 indicates that the DMA transfer on the channel has
1107                  * not been started (no data has been transferred so far).
1108                  * Return the programmed destination start address in this case.
1109                  */
1110                 if (unlikely(!offset))
1111                         offset = p->dma_read(CDSA, lch);
1112         }
1113
1114         if (dma_omap1())
1115                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1116
1117         return offset;
1118 }
1119 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1120
1121 int omap_get_dma_active_status(int lch)
1122 {
1123         return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1124 }
1125 EXPORT_SYMBOL(omap_get_dma_active_status);
1126
1127 int omap_dma_running(void)
1128 {
1129         int lch;
1130
1131         if (dma_omap1())
1132                 if (omap_lcd_dma_running())
1133                         return 1;
1134
1135         for (lch = 0; lch < dma_chan_count; lch++)
1136                 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1137                         return 1;
1138
1139         return 0;
1140 }
1141
1142 /*
1143  * lch_queue DMA will start right after lch_head one is finished.
1144  * For this DMA link to start, you still need to start (see omap_start_dma)
1145  * the first one. That will fire up the entire queue.
1146  */
1147 void omap_dma_link_lch(int lch_head, int lch_queue)
1148 {
1149         if (omap_dma_in_1510_mode()) {
1150                 if (lch_head == lch_queue) {
1151                         p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1152                                                                 CCR, lch_head);
1153                         return;
1154                 }
1155                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1156                 BUG();
1157                 return;
1158         }
1159
1160         if ((dma_chan[lch_head].dev_id == -1) ||
1161             (dma_chan[lch_queue].dev_id == -1)) {
1162                 pr_err("omap_dma: trying to link non requested channels\n");
1163                 dump_stack();
1164         }
1165
1166         dma_chan[lch_head].next_lch = lch_queue;
1167 }
1168 EXPORT_SYMBOL(omap_dma_link_lch);
1169
1170 /*
1171  * Once the DMA queue is stopped, we can destroy it.
1172  */
1173 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1174 {
1175         if (omap_dma_in_1510_mode()) {
1176                 if (lch_head == lch_queue) {
1177                         p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1178                                                                 CCR, lch_head);
1179                         return;
1180                 }
1181                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1182                 BUG();
1183                 return;
1184         }
1185
1186         if (dma_chan[lch_head].next_lch != lch_queue ||
1187             dma_chan[lch_head].next_lch == -1) {
1188                 pr_err("omap_dma: trying to unlink non linked channels\n");
1189                 dump_stack();
1190         }
1191
1192         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1193             (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1194                 pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
1195                 dump_stack();
1196         }
1197
1198         dma_chan[lch_head].next_lch = -1;
1199 }
1200 EXPORT_SYMBOL(omap_dma_unlink_lch);
1201
1202 #ifndef CONFIG_ARCH_OMAP1
1203 /* Create chain of DMA channesls */
1204 static void create_dma_lch_chain(int lch_head, int lch_queue)
1205 {
1206         u32 l;
1207
1208         /* Check if this is the first link in chain */
1209         if (dma_chan[lch_head].next_linked_ch == -1) {
1210                 dma_chan[lch_head].next_linked_ch = lch_queue;
1211                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1212                 dma_chan[lch_queue].next_linked_ch = lch_head;
1213                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1214         }
1215
1216         /* a link exists, link the new channel in circular chain */
1217         else {
1218                 dma_chan[lch_queue].next_linked_ch =
1219                                         dma_chan[lch_head].next_linked_ch;
1220                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1221                 dma_chan[lch_head].next_linked_ch = lch_queue;
1222                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1223                                         lch_queue;
1224         }
1225
1226         l = p->dma_read(CLNK_CTRL, lch_head);
1227         l &= ~(0x1f);
1228         l |= lch_queue;
1229         p->dma_write(l, CLNK_CTRL, lch_head);
1230
1231         l = p->dma_read(CLNK_CTRL, lch_queue);
1232         l &= ~(0x1f);
1233         l |= (dma_chan[lch_queue].next_linked_ch);
1234         p->dma_write(l, CLNK_CTRL, lch_queue);
1235 }
1236
1237 /**
1238  * @brief omap_request_dma_chain : Request a chain of DMA channels
1239  *
1240  * @param dev_id - Device id using the dma channel
1241  * @param dev_name - Device name
1242  * @param callback - Call back function
1243  * @chain_id -
1244  * @no_of_chans - Number of channels requested
1245  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1246  *                                            OMAP_DMA_DYNAMIC_CHAIN
1247  * @params - Channel parameters
1248  *
1249  * @return - Success : 0
1250  *           Failure: -EINVAL/-ENOMEM
1251  */
1252 int omap_request_dma_chain(int dev_id, const char *dev_name,
1253                            void (*callback) (int lch, u16 ch_status,
1254                                              void *data),
1255                            int *chain_id, int no_of_chans, int chain_mode,
1256                            struct omap_dma_channel_params params)
1257 {
1258         int *channels;
1259         int i, err;
1260
1261         /* Is the chain mode valid ? */
1262         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1263                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1264                 printk(KERN_ERR "Invalid chain mode requested\n");
1265                 return -EINVAL;
1266         }
1267
1268         if (unlikely((no_of_chans < 1
1269                         || no_of_chans > dma_lch_count))) {
1270                 printk(KERN_ERR "Invalid Number of channels requested\n");
1271                 return -EINVAL;
1272         }
1273
1274         /*
1275          * Allocate a queue to maintain the status of the channels
1276          * in the chain
1277          */
1278         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1279         if (channels == NULL) {
1280                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1281                 return -ENOMEM;
1282         }
1283
1284         /* request and reserve DMA channels for the chain */
1285         for (i = 0; i < no_of_chans; i++) {
1286                 err = omap_request_dma(dev_id, dev_name,
1287                                         callback, NULL, &channels[i]);
1288                 if (err < 0) {
1289                         int j;
1290                         for (j = 0; j < i; j++)
1291                                 omap_free_dma(channels[j]);
1292                         kfree(channels);
1293                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1294                         return err;
1295                 }
1296                 dma_chan[channels[i]].prev_linked_ch = -1;
1297                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1298
1299                 /*
1300                  * Allowing client drivers to set common parameters now,
1301                  * so that later only relevant (src_start, dest_start
1302                  * and element count) can be set
1303                  */
1304                 omap_set_dma_params(channels[i], &params);
1305         }
1306
1307         *chain_id = channels[0];
1308         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1309         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1310         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1311         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1312
1313         for (i = 0; i < no_of_chans; i++)
1314                 dma_chan[channels[i]].chain_id = *chain_id;
1315
1316         /* Reset the Queue pointers */
1317         OMAP_DMA_CHAIN_QINIT(*chain_id);
1318
1319         /* Set up the chain */
1320         if (no_of_chans == 1)
1321                 create_dma_lch_chain(channels[0], channels[0]);
1322         else {
1323                 for (i = 0; i < (no_of_chans - 1); i++)
1324                         create_dma_lch_chain(channels[i], channels[i + 1]);
1325         }
1326
1327         return 0;
1328 }
1329 EXPORT_SYMBOL(omap_request_dma_chain);
1330
1331 /**
1332  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1333  * params after setting it. Dont do this while dma is running!!
1334  *
1335  * @param chain_id - Chained logical channel id.
1336  * @param params
1337  *
1338  * @return - Success : 0
1339  *           Failure : -EINVAL
1340  */
1341 int omap_modify_dma_chain_params(int chain_id,
1342                                 struct omap_dma_channel_params params)
1343 {
1344         int *channels;
1345         u32 i;
1346
1347         /* Check for input params */
1348         if (unlikely((chain_id < 0
1349                         || chain_id >= dma_lch_count))) {
1350                 printk(KERN_ERR "Invalid chain id\n");
1351                 return -EINVAL;
1352         }
1353
1354         /* Check if the chain exists */
1355         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1356                 printk(KERN_ERR "Chain doesn't exists\n");
1357                 return -EINVAL;
1358         }
1359         channels = dma_linked_lch[chain_id].linked_dmach_q;
1360
1361         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1362                 /*
1363                  * Allowing client drivers to set common parameters now,
1364                  * so that later only relevant (src_start, dest_start
1365                  * and element count) can be set
1366                  */
1367                 omap_set_dma_params(channels[i], &params);
1368         }
1369
1370         return 0;
1371 }
1372 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1373
1374 /**
1375  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1376  *
1377  * @param chain_id
1378  *
1379  * @return - Success : 0
1380  *           Failure : -EINVAL
1381  */
1382 int omap_free_dma_chain(int chain_id)
1383 {
1384         int *channels;
1385         u32 i;
1386
1387         /* Check for input params */
1388         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1389                 printk(KERN_ERR "Invalid chain id\n");
1390                 return -EINVAL;
1391         }
1392
1393         /* Check if the chain exists */
1394         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1395                 printk(KERN_ERR "Chain doesn't exists\n");
1396                 return -EINVAL;
1397         }
1398
1399         channels = dma_linked_lch[chain_id].linked_dmach_q;
1400         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1401                 dma_chan[channels[i]].next_linked_ch = -1;
1402                 dma_chan[channels[i]].prev_linked_ch = -1;
1403                 dma_chan[channels[i]].chain_id = -1;
1404                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1405                 omap_free_dma(channels[i]);
1406         }
1407
1408         kfree(channels);
1409
1410         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1411         dma_linked_lch[chain_id].chain_mode = -1;
1412         dma_linked_lch[chain_id].chain_state = -1;
1413
1414         return (0);
1415 }
1416 EXPORT_SYMBOL(omap_free_dma_chain);
1417
1418 /**
1419  * @brief omap_dma_chain_status - Check if the chain is in
1420  * active / inactive state.
1421  * @param chain_id
1422  *
1423  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1424  *           Failure : -EINVAL
1425  */
1426 int omap_dma_chain_status(int chain_id)
1427 {
1428         /* Check for input params */
1429         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1430                 printk(KERN_ERR "Invalid chain id\n");
1431                 return -EINVAL;
1432         }
1433
1434         /* Check if the chain exists */
1435         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1436                 printk(KERN_ERR "Chain doesn't exists\n");
1437                 return -EINVAL;
1438         }
1439         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1440                         dma_linked_lch[chain_id].q_count);
1441
1442         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1443                 return OMAP_DMA_CHAIN_INACTIVE;
1444
1445         return OMAP_DMA_CHAIN_ACTIVE;
1446 }
1447 EXPORT_SYMBOL(omap_dma_chain_status);
1448
1449 /**
1450  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1451  * set the params and start the transfer.
1452  *
1453  * @param chain_id
1454  * @param src_start - buffer start address
1455  * @param dest_start - Dest address
1456  * @param elem_count
1457  * @param frame_count
1458  * @param callbk_data - channel callback parameter data.
1459  *
1460  * @return  - Success : 0
1461  *            Failure: -EINVAL/-EBUSY
1462  */
1463 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1464                         int elem_count, int frame_count, void *callbk_data)
1465 {
1466         int *channels;
1467         u32 l, lch;
1468         int start_dma = 0;
1469
1470         /*
1471          * if buffer size is less than 1 then there is
1472          * no use of starting the chain
1473          */
1474         if (elem_count < 1) {
1475                 printk(KERN_ERR "Invalid buffer size\n");
1476                 return -EINVAL;
1477         }
1478
1479         /* Check for input params */
1480         if (unlikely((chain_id < 0
1481                         || chain_id >= dma_lch_count))) {
1482                 printk(KERN_ERR "Invalid chain id\n");
1483                 return -EINVAL;
1484         }
1485
1486         /* Check if the chain exists */
1487         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1488                 printk(KERN_ERR "Chain doesn't exist\n");
1489                 return -EINVAL;
1490         }
1491
1492         /* Check if all the channels in chain are in use */
1493         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1494                 return -EBUSY;
1495
1496         /* Frame count may be negative in case of indexed transfers */
1497         channels = dma_linked_lch[chain_id].linked_dmach_q;
1498
1499         /* Get a free channel */
1500         lch = channels[dma_linked_lch[chain_id].q_tail];
1501
1502         /* Store the callback data */
1503         dma_chan[lch].data = callbk_data;
1504
1505         /* Increment the q_tail */
1506         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1507
1508         /* Set the params to the free channel */
1509         if (src_start != 0)
1510                 p->dma_write(src_start, CSSA, lch);
1511         if (dest_start != 0)
1512                 p->dma_write(dest_start, CDSA, lch);
1513
1514         /* Write the buffer size */
1515         p->dma_write(elem_count, CEN, lch);
1516         p->dma_write(frame_count, CFN, lch);
1517
1518         /*
1519          * If the chain is dynamically linked,
1520          * then we may have to start the chain if its not active
1521          */
1522         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1523
1524                 /*
1525                  * In Dynamic chain, if the chain is not started,
1526                  * queue the channel
1527                  */
1528                 if (dma_linked_lch[chain_id].chain_state ==
1529                                                 DMA_CHAIN_NOTSTARTED) {
1530                         /* Enable the link in previous channel */
1531                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1532                                                                 DMA_CH_QUEUED)
1533                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1534                         dma_chan[lch].state = DMA_CH_QUEUED;
1535                 }
1536
1537                 /*
1538                  * Chain is already started, make sure its active,
1539                  * if not then start the chain
1540                  */
1541                 else {
1542                         start_dma = 1;
1543
1544                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1545                                                         DMA_CH_STARTED) {
1546                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1547                                 dma_chan[lch].state = DMA_CH_QUEUED;
1548                                 start_dma = 0;
1549                                 if (0 == ((1 << 7) & p->dma_read(
1550                                         CCR, dma_chan[lch].prev_linked_ch))) {
1551                                         disable_lnk(dma_chan[lch].
1552                                                     prev_linked_ch);
1553                                         pr_debug("\n prev ch is stopped\n");
1554                                         start_dma = 1;
1555                                 }
1556                         }
1557
1558                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1559                                                         == DMA_CH_QUEUED) {
1560                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1561                                 dma_chan[lch].state = DMA_CH_QUEUED;
1562                                 start_dma = 0;
1563                         }
1564                         omap_enable_channel_irq(lch);
1565
1566                         l = p->dma_read(CCR, lch);
1567
1568                         if ((0 == (l & (1 << 24))))
1569                                 l &= ~(1 << 25);
1570                         else
1571                                 l |= (1 << 25);
1572                         if (start_dma == 1) {
1573                                 if (0 == (l & (1 << 7))) {
1574                                         l |= (1 << 7);
1575                                         dma_chan[lch].state = DMA_CH_STARTED;
1576                                         pr_debug("starting %d\n", lch);
1577                                         p->dma_write(l, CCR, lch);
1578                                 } else
1579                                         start_dma = 0;
1580                         } else {
1581                                 if (0 == (l & (1 << 7)))
1582                                         p->dma_write(l, CCR, lch);
1583                         }
1584                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1585                 }
1586         }
1587
1588         return 0;
1589 }
1590 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1591
1592 /**
1593  * @brief omap_start_dma_chain_transfers - Start the chain
1594  *
1595  * @param chain_id
1596  *
1597  * @return - Success : 0
1598  *           Failure : -EINVAL/-EBUSY
1599  */
1600 int omap_start_dma_chain_transfers(int chain_id)
1601 {
1602         int *channels;
1603         u32 l, i;
1604
1605         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1606                 printk(KERN_ERR "Invalid chain id\n");
1607                 return -EINVAL;
1608         }
1609
1610         channels = dma_linked_lch[chain_id].linked_dmach_q;
1611
1612         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1613                 printk(KERN_ERR "Chain is already started\n");
1614                 return -EBUSY;
1615         }
1616
1617         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1618                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1619                                                                         i++) {
1620                         enable_lnk(channels[i]);
1621                         omap_enable_channel_irq(channels[i]);
1622                 }
1623         } else {
1624                 omap_enable_channel_irq(channels[0]);
1625         }
1626
1627         l = p->dma_read(CCR, channels[0]);
1628         l |= (1 << 7);
1629         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1630         dma_chan[channels[0]].state = DMA_CH_STARTED;
1631
1632         if ((0 == (l & (1 << 24))))
1633                 l &= ~(1 << 25);
1634         else
1635                 l |= (1 << 25);
1636         p->dma_write(l, CCR, channels[0]);
1637
1638         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1639
1640         return 0;
1641 }
1642 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1643
1644 /**
1645  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1646  *
1647  * @param chain_id
1648  *
1649  * @return - Success : 0
1650  *           Failure : EINVAL
1651  */
1652 int omap_stop_dma_chain_transfers(int chain_id)
1653 {
1654         int *channels;
1655         u32 l, i;
1656         u32 sys_cf = 0;
1657
1658         /* Check for input params */
1659         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1660                 printk(KERN_ERR "Invalid chain id\n");
1661                 return -EINVAL;
1662         }
1663
1664         /* Check if the chain exists */
1665         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1666                 printk(KERN_ERR "Chain doesn't exists\n");
1667                 return -EINVAL;
1668         }
1669         channels = dma_linked_lch[chain_id].linked_dmach_q;
1670
1671         if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1672                 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1673                 l = sys_cf;
1674                 /* Middle mode reg set no Standby */
1675                 l &= ~((1 << 12)|(1 << 13));
1676                 p->dma_write(l, OCP_SYSCONFIG, 0);
1677         }
1678
1679         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1680
1681                 /* Stop the Channel transmission */
1682                 l = p->dma_read(CCR, channels[i]);
1683                 l &= ~(1 << 7);
1684                 p->dma_write(l, CCR, channels[i]);
1685
1686                 /* Disable the link in all the channels */
1687                 disable_lnk(channels[i]);
1688                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1689
1690         }
1691         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1692
1693         /* Reset the Queue pointers */
1694         OMAP_DMA_CHAIN_QINIT(chain_id);
1695
1696         if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1697                 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1698
1699         return 0;
1700 }
1701 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1702
1703 /* Get the index of the ongoing DMA in chain */
1704 /**
1705  * @brief omap_get_dma_chain_index - Get the element and frame index
1706  * of the ongoing DMA in chain
1707  *
1708  * @param chain_id
1709  * @param ei - Element index
1710  * @param fi - Frame index
1711  *
1712  * @return - Success : 0
1713  *           Failure : -EINVAL
1714  */
1715 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1716 {
1717         int lch;
1718         int *channels;
1719
1720         /* Check for input params */
1721         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1722                 printk(KERN_ERR "Invalid chain id\n");
1723                 return -EINVAL;
1724         }
1725
1726         /* Check if the chain exists */
1727         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1728                 printk(KERN_ERR "Chain doesn't exists\n");
1729                 return -EINVAL;
1730         }
1731         if ((!ei) || (!fi))
1732                 return -EINVAL;
1733
1734         channels = dma_linked_lch[chain_id].linked_dmach_q;
1735
1736         /* Get the current channel */
1737         lch = channels[dma_linked_lch[chain_id].q_head];
1738
1739         *ei = p->dma_read(CCEN, lch);
1740         *fi = p->dma_read(CCFN, lch);
1741
1742         return 0;
1743 }
1744 EXPORT_SYMBOL(omap_get_dma_chain_index);
1745
1746 /**
1747  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1748  * ongoing DMA in chain
1749  *
1750  * @param chain_id
1751  *
1752  * @return - Success : Destination position
1753  *           Failure : -EINVAL
1754  */
1755 int omap_get_dma_chain_dst_pos(int chain_id)
1756 {
1757         int lch;
1758         int *channels;
1759
1760         /* Check for input params */
1761         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1762                 printk(KERN_ERR "Invalid chain id\n");
1763                 return -EINVAL;
1764         }
1765
1766         /* Check if the chain exists */
1767         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1768                 printk(KERN_ERR "Chain doesn't exists\n");
1769                 return -EINVAL;
1770         }
1771
1772         channels = dma_linked_lch[chain_id].linked_dmach_q;
1773
1774         /* Get the current channel */
1775         lch = channels[dma_linked_lch[chain_id].q_head];
1776
1777         return p->dma_read(CDAC, lch);
1778 }
1779 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1780
1781 /**
1782  * @brief omap_get_dma_chain_src_pos - Get the source position
1783  * of the ongoing DMA in chain
1784  * @param chain_id
1785  *
1786  * @return - Success : Destination position
1787  *           Failure : -EINVAL
1788  */
1789 int omap_get_dma_chain_src_pos(int chain_id)
1790 {
1791         int lch;
1792         int *channels;
1793
1794         /* Check for input params */
1795         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1796                 printk(KERN_ERR "Invalid chain id\n");
1797                 return -EINVAL;
1798         }
1799
1800         /* Check if the chain exists */
1801         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1802                 printk(KERN_ERR "Chain doesn't exists\n");
1803                 return -EINVAL;
1804         }
1805
1806         channels = dma_linked_lch[chain_id].linked_dmach_q;
1807
1808         /* Get the current channel */
1809         lch = channels[dma_linked_lch[chain_id].q_head];
1810
1811         return p->dma_read(CSAC, lch);
1812 }
1813 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1814 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1815
1816 /*----------------------------------------------------------------------------*/
1817
1818 #ifdef CONFIG_ARCH_OMAP1
1819
1820 static int omap1_dma_handle_ch(int ch)
1821 {
1822         u32 csr;
1823
1824         if (enable_1510_mode && ch >= 6) {
1825                 csr = dma_chan[ch].saved_csr;
1826                 dma_chan[ch].saved_csr = 0;
1827         } else
1828                 csr = p->dma_read(CSR, ch);
1829         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1830                 dma_chan[ch + 6].saved_csr = csr >> 7;
1831                 csr &= 0x7f;
1832         }
1833         if ((csr & 0x3f) == 0)
1834                 return 0;
1835         if (unlikely(dma_chan[ch].dev_id == -1)) {
1836                 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1837                         ch, csr);
1838                 return 0;
1839         }
1840         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1841                 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
1842         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1843                 pr_warn("DMA synchronization event drop occurred with device %d\n",
1844                         dma_chan[ch].dev_id);
1845         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1846                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1847         if (likely(dma_chan[ch].callback != NULL))
1848                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1849
1850         return 1;
1851 }
1852
1853 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1854 {
1855         int ch = ((int) dev_id) - 1;
1856         int handled = 0;
1857
1858         for (;;) {
1859                 int handled_now = 0;
1860
1861                 handled_now += omap1_dma_handle_ch(ch);
1862                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1863                         handled_now += omap1_dma_handle_ch(ch + 6);
1864                 if (!handled_now)
1865                         break;
1866                 handled += handled_now;
1867         }
1868
1869         return handled ? IRQ_HANDLED : IRQ_NONE;
1870 }
1871
1872 #else
1873 #define omap1_dma_irq_handler   NULL
1874 #endif
1875
1876 #ifdef CONFIG_ARCH_OMAP2PLUS
1877
1878 static int omap2_dma_handle_ch(int ch)
1879 {
1880         u32 status = p->dma_read(CSR, ch);
1881
1882         if (!status) {
1883                 if (printk_ratelimit())
1884                         pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1885                 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1886                 return 0;
1887         }
1888         if (unlikely(dma_chan[ch].dev_id == -1)) {
1889                 if (printk_ratelimit())
1890                         pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1891                                 status, ch);
1892                 return 0;
1893         }
1894         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1895                 pr_info("DMA synchronization event drop occurred with device %d\n",
1896                         dma_chan[ch].dev_id);
1897         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1898                 printk(KERN_INFO "DMA transaction error with device %d\n",
1899                        dma_chan[ch].dev_id);
1900                 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1901                         u32 ccr;
1902
1903                         ccr = p->dma_read(CCR, ch);
1904                         ccr &= ~OMAP_DMA_CCR_EN;
1905                         p->dma_write(ccr, CCR, ch);
1906                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1907                 }
1908         }
1909         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1910                 printk(KERN_INFO "DMA secure error with device %d\n",
1911                        dma_chan[ch].dev_id);
1912         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1913                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1914                        dma_chan[ch].dev_id);
1915
1916         p->dma_write(status, CSR, ch);
1917         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1918         /* read back the register to flush the write */
1919         p->dma_read(IRQSTATUS_L0, ch);
1920
1921         /* If the ch is not chained then chain_id will be -1 */
1922         if (dma_chan[ch].chain_id != -1) {
1923                 int chain_id = dma_chan[ch].chain_id;
1924                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1925                 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1926                         dma_chan[dma_chan[ch].next_linked_ch].state =
1927                                                         DMA_CH_STARTED;
1928                 if (dma_linked_lch[chain_id].chain_mode ==
1929                                                 OMAP_DMA_DYNAMIC_CHAIN)
1930                         disable_lnk(ch);
1931
1932                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1933                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1934
1935                 status = p->dma_read(CSR, ch);
1936                 p->dma_write(status, CSR, ch);
1937         }
1938
1939         if (likely(dma_chan[ch].callback != NULL))
1940                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1941
1942         return 0;
1943 }
1944
1945 /* STATUS register count is from 1-32 while our is 0-31 */
1946 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1947 {
1948         u32 val, enable_reg;
1949         int i;
1950
1951         val = p->dma_read(IRQSTATUS_L0, 0);
1952         if (val == 0) {
1953                 if (printk_ratelimit())
1954                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1955                 return IRQ_HANDLED;
1956         }
1957         enable_reg = p->dma_read(IRQENABLE_L0, 0);
1958         val &= enable_reg; /* Dispatch only relevant interrupts */
1959         for (i = 0; i < dma_lch_count && val != 0; i++) {
1960                 if (val & 1)
1961                         omap2_dma_handle_ch(i);
1962                 val >>= 1;
1963         }
1964
1965         return IRQ_HANDLED;
1966 }
1967
1968 static struct irqaction omap24xx_dma_irq = {
1969         .name = "DMA",
1970         .handler = omap2_dma_irq_handler,
1971 };
1972
1973 #else
1974 static struct irqaction omap24xx_dma_irq;
1975 #endif
1976
1977 /*----------------------------------------------------------------------------*/
1978
1979 /*
1980  * Note that we are currently using only IRQENABLE_L0 and L1.
1981  * As the DSP may be using IRQENABLE_L2 and L3, let's not
1982  * touch those for now.
1983  */
1984 void omap_dma_global_context_save(void)
1985 {
1986         omap_dma_global_context.dma_irqenable_l0 =
1987                 p->dma_read(IRQENABLE_L0, 0);
1988         omap_dma_global_context.dma_irqenable_l1 =
1989                 p->dma_read(IRQENABLE_L1, 0);
1990         omap_dma_global_context.dma_ocp_sysconfig =
1991                 p->dma_read(OCP_SYSCONFIG, 0);
1992         omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1993 }
1994
1995 void omap_dma_global_context_restore(void)
1996 {
1997         int ch;
1998
1999         p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
2000         p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
2001                 OCP_SYSCONFIG, 0);
2002         p->dma_write(omap_dma_global_context.dma_irqenable_l0,
2003                 IRQENABLE_L0, 0);
2004         p->dma_write(omap_dma_global_context.dma_irqenable_l1,
2005                 IRQENABLE_L1, 0);
2006
2007         if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
2008                 p->dma_write(0x3 , IRQSTATUS_L0, 0);
2009
2010         for (ch = 0; ch < dma_chan_count; ch++)
2011                 if (dma_chan[ch].dev_id != -1)
2012                         omap_clear_dma(ch);
2013 }
2014
2015 struct omap_system_dma_plat_info *omap_get_plat_info(void)
2016 {
2017         return p;
2018 }
2019 EXPORT_SYMBOL_GPL(omap_get_plat_info);
2020
2021 static int omap_system_dma_probe(struct platform_device *pdev)
2022 {
2023         int ch, ret = 0;
2024         int dma_irq;
2025         char irq_name[4];
2026         int irq_rel;
2027
2028         p = pdev->dev.platform_data;
2029         if (!p) {
2030                 dev_err(&pdev->dev,
2031                         "%s: System DMA initialized without platform data\n",
2032                         __func__);
2033                 return -EINVAL;
2034         }
2035
2036         d                       = p->dma_attr;
2037         errata                  = p->errata;
2038
2039         if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2040                         && (omap_dma_reserve_channels < d->lch_count))
2041                 d->lch_count    = omap_dma_reserve_channels;
2042
2043         dma_lch_count           = d->lch_count;
2044         dma_chan_count          = dma_lch_count;
2045         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
2046
2047         dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
2048                                 sizeof(struct omap_dma_lch), GFP_KERNEL);
2049         if (!dma_chan) {
2050                 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
2051                 return -ENOMEM;
2052         }
2053
2054
2055         if (dma_omap2plus()) {
2056                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2057                                                 dma_lch_count, GFP_KERNEL);
2058                 if (!dma_linked_lch) {
2059                         ret = -ENOMEM;
2060                         goto exit_dma_lch_fail;
2061                 }
2062         }
2063
2064         spin_lock_init(&dma_chan_lock);
2065         for (ch = 0; ch < dma_chan_count; ch++) {
2066                 omap_clear_dma(ch);
2067                 if (dma_omap2plus())
2068                         omap2_disable_irq_lch(ch);
2069
2070                 dma_chan[ch].dev_id = -1;
2071                 dma_chan[ch].next_lch = -1;
2072
2073                 if (ch >= 6 && enable_1510_mode)
2074                         continue;
2075
2076                 if (dma_omap1()) {
2077                         /*
2078                          * request_irq() doesn't like dev_id (ie. ch) being
2079                          * zero, so we have to kludge around this.
2080                          */
2081                         sprintf(&irq_name[0], "%d", ch);
2082                         dma_irq = platform_get_irq_byname(pdev, irq_name);
2083
2084                         if (dma_irq < 0) {
2085                                 ret = dma_irq;
2086                                 goto exit_dma_irq_fail;
2087                         }
2088
2089                         /* INT_DMA_LCD is handled in lcd_dma.c */
2090                         if (dma_irq == INT_DMA_LCD)
2091                                 continue;
2092
2093                         ret = request_irq(dma_irq,
2094                                         omap1_dma_irq_handler, 0, "DMA",
2095                                         (void *) (ch + 1));
2096                         if (ret != 0)
2097                                 goto exit_dma_irq_fail;
2098                 }
2099         }
2100
2101         if (d->dev_caps & IS_RW_PRIORITY)
2102                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2103                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2104
2105         if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
2106                 strcpy(irq_name, "0");
2107                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2108                 if (dma_irq < 0) {
2109                         dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2110                         ret = dma_irq;
2111                         goto exit_dma_lch_fail;
2112                 }
2113                 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2114                 if (ret) {
2115                         dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
2116                                 dma_irq, ret);
2117                         goto exit_dma_lch_fail;
2118                 }
2119         }
2120
2121         /* reserve dma channels 0 and 1 in high security devices on 34xx */
2122         if (d->dev_caps & HS_CHANNELS_RESERVED) {
2123                 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
2124                 dma_chan[0].dev_id = 0;
2125                 dma_chan[1].dev_id = 1;
2126         }
2127         p->show_dma_caps();
2128         return 0;
2129
2130 exit_dma_irq_fail:
2131         dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
2132                 dma_irq, ret);
2133         for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2134                 dma_irq = platform_get_irq(pdev, irq_rel);
2135                 free_irq(dma_irq, (void *)(irq_rel + 1));
2136         }
2137
2138 exit_dma_lch_fail:
2139         return ret;
2140 }
2141
2142 static int omap_system_dma_remove(struct platform_device *pdev)
2143 {
2144         int dma_irq;
2145
2146         if (dma_omap2plus()) {
2147                 char irq_name[4];
2148                 strcpy(irq_name, "0");
2149                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2150                 if (dma_irq >= 0)
2151                         remove_irq(dma_irq, &omap24xx_dma_irq);
2152         } else {
2153                 int irq_rel = 0;
2154                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2155                         dma_irq = platform_get_irq(pdev, irq_rel);
2156                         free_irq(dma_irq, (void *)(irq_rel + 1));
2157                 }
2158         }
2159         return 0;
2160 }
2161
2162 static struct platform_driver omap_system_dma_driver = {
2163         .probe          = omap_system_dma_probe,
2164         .remove         = omap_system_dma_remove,
2165         .driver         = {
2166                 .name   = "omap_dma_system"
2167         },
2168 };
2169
2170 static int __init omap_system_dma_init(void)
2171 {
2172         return platform_driver_register(&omap_system_dma_driver);
2173 }
2174 arch_initcall(omap_system_dma_init);
2175
2176 static void __exit omap_system_dma_exit(void)
2177 {
2178         platform_driver_unregister(&omap_system_dma_driver);
2179 }
2180
2181 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2182 MODULE_LICENSE("GPL");
2183 MODULE_ALIAS("platform:" DRIVER_NAME);
2184 MODULE_AUTHOR("Texas Instruments Inc");
2185
2186 /*
2187  * Reserve the omap SDMA channels using cmdline bootarg
2188  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2189  */
2190 static int __init omap_dma_cmdline_reserve_ch(char *str)
2191 {
2192         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2193                 omap_dma_reserve_channels = 0;
2194         return 1;
2195 }
2196
2197 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2198
2199