3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
8 select ARCH_HAS_ELF_RANDOMIZE
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_HAS_SG_CHAIN
11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_SUPPORTS_ATOMIC_RMW
14 select ARCH_SUPPORTS_NUMA_BALANCING
15 select ARCH_WANT_OPTIONAL_GPIOLIB
16 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
17 select ARCH_WANT_FRAME_POINTERS
18 select ARCH_HAS_UBSAN_SANITIZE_ALL
22 select AUDIT_ARCH_COMPAT_GENERIC
23 select ARM_GIC_V2M if PCI_MSI
25 select ARM_GIC_V3_ITS if PCI_MSI
27 select BUILDTIME_EXTABLE_SORT
28 select CLONE_BACKWARDS
30 select CPU_PM if (SUSPEND || CPU_IDLE)
31 select DCACHE_WORD_ACCESS
34 select GENERIC_ALLOCATOR
35 select GENERIC_CLOCKEVENTS
36 select GENERIC_CLOCKEVENTS_BROADCAST
37 select GENERIC_CPU_AUTOPROBE
38 select GENERIC_EARLY_IOREMAP
39 select GENERIC_IDLE_POLL_SETUP
40 select GENERIC_IRQ_PROBE
41 select GENERIC_IRQ_SHOW
42 select GENERIC_IRQ_SHOW_LEVEL
43 select GENERIC_PCI_IOMAP
44 select GENERIC_SCHED_CLOCK
45 select GENERIC_SMP_IDLE_THREAD
46 select GENERIC_STRNCPY_FROM_USER
47 select GENERIC_STRNLEN_USER
48 select GENERIC_TIME_VSYSCALL
49 select HANDLE_DOMAIN_IRQ
50 select HARDIRQS_SW_RESEND
51 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
52 select HAVE_ARCH_AUDITSYSCALL
53 select HAVE_ARCH_BITREVERSE
54 select HAVE_ARCH_HUGE_VMAP
55 select HAVE_ARCH_JUMP_LABEL
56 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
58 select HAVE_ARCH_MMAP_RND_BITS
59 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
60 select HAVE_ARCH_SECCOMP_FILTER
61 select HAVE_ARCH_TRACEHOOK
62 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
65 select HAVE_C_RECORDMCOUNT
66 select HAVE_CC_STACKPROTECTOR
67 select HAVE_CMPXCHG_DOUBLE
68 select HAVE_CMPXCHG_LOCAL
69 select HAVE_CONTEXT_TRACKING
70 select HAVE_DEBUG_BUGVERBOSE
71 select HAVE_DEBUG_KMEMLEAK
72 select HAVE_DMA_API_DEBUG
73 select HAVE_DMA_CONTIGUOUS
74 select HAVE_DYNAMIC_FTRACE
75 select HAVE_EFFICIENT_UNALIGNED_ACCESS
76 select HAVE_FTRACE_MCOUNT_RECORD
77 select HAVE_FUNCTION_TRACER
78 select HAVE_FUNCTION_GRAPH_TRACER
79 select HAVE_GENERIC_DMA_COHERENT
80 select HAVE_HW_BREAKPOINT if PERF_EVENTS
81 select HAVE_IRQ_TIME_ACCOUNTING
83 select HAVE_MEMBLOCK_NODE_MAP if NUMA
84 select HAVE_PATA_PLATFORM
85 select HAVE_PERF_EVENTS
87 select HAVE_PERF_USER_STACK_DUMP
88 select HAVE_RCU_TABLE_FREE
89 select HAVE_SYSCALL_TRACEPOINTS
90 select IOMMU_DMA if IOMMU_SUPPORT
92 select IRQ_FORCED_THREADING
93 select MODULES_USE_ELF_RELA
96 select OF_EARLY_FLATTREE
97 select OF_NUMA if NUMA && OF
98 select OF_RESERVED_MEM
99 select PERF_USE_VMALLOC
103 select SYSCTL_EXCEPTION_TRACE
105 ARM 64-bit (AArch64) Linux support.
110 config ARCH_PHYS_ADDR_T_64BIT
116 config ARM64_PAGE_SHIFT
118 default 16 if ARM64_64K_PAGES
119 default 14 if ARM64_16K_PAGES
122 config ARM64_CONT_SHIFT
124 default 5 if ARM64_64K_PAGES
125 default 7 if ARM64_16K_PAGES
128 config ARCH_MMAP_RND_BITS_MIN
129 default 14 if ARM64_64K_PAGES
130 default 16 if ARM64_16K_PAGES
133 # max bits determined by the following formula:
134 # VA_BITS - PAGE_SHIFT - 3
135 config ARCH_MMAP_RND_BITS_MAX
136 default 19 if ARM64_VA_BITS=36
137 default 24 if ARM64_VA_BITS=39
138 default 27 if ARM64_VA_BITS=42
139 default 30 if ARM64_VA_BITS=47
140 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
141 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
142 default 33 if ARM64_VA_BITS=48
143 default 14 if ARM64_64K_PAGES
144 default 16 if ARM64_16K_PAGES
147 config ARCH_MMAP_RND_COMPAT_BITS_MIN
148 default 7 if ARM64_64K_PAGES
149 default 9 if ARM64_16K_PAGES
152 config ARCH_MMAP_RND_COMPAT_BITS_MAX
158 config STACKTRACE_SUPPORT
161 config ILLEGAL_POINTER_VALUE
163 default 0xdead000000000000
165 config LOCKDEP_SUPPORT
168 config TRACE_IRQFLAGS_SUPPORT
171 config RWSEM_XCHGADD_ALGORITHM
178 config GENERIC_BUG_RELATIVE_POINTERS
180 depends on GENERIC_BUG
182 config GENERIC_HWEIGHT
188 config GENERIC_CALIBRATE_DELAY
194 config HAVE_GENERIC_RCU_GUP
197 config ARCH_DMA_ADDR_T_64BIT
200 config NEED_DMA_MAP_STATE
203 config NEED_SG_DMA_LENGTH
215 config KERNEL_MODE_NEON
218 config FIX_EARLYCON_MEM
221 config PGTABLE_LEVELS
223 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
224 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
225 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
226 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
227 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
228 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
230 source "init/Kconfig"
232 source "kernel/Kconfig.freezer"
234 source "arch/arm64/Kconfig.platforms"
241 This feature enables support for PCI bus system. If you say Y
242 here, the kernel will include drivers and infrastructure code
243 to support PCI bus devices.
248 config PCI_DOMAINS_GENERIC
254 source "drivers/pci/Kconfig"
258 menu "Kernel Features"
260 menu "ARM errata workarounds via the alternatives framework"
262 config ARM64_ERRATUM_826319
263 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
266 This option adds an alternative code sequence to work around ARM
267 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
268 AXI master interface and an L2 cache.
270 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
271 and is unable to accept a certain write via this interface, it will
272 not progress on read data presented on the read data channel and the
275 The workaround promotes data cache clean instructions to
276 data cache clean-and-invalidate.
277 Please note that this does not necessarily enable the workaround,
278 as it depends on the alternative framework, which will only patch
279 the kernel if an affected CPU is detected.
283 config ARM64_ERRATUM_827319
284 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
287 This option adds an alternative code sequence to work around ARM
288 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
289 master interface and an L2 cache.
291 Under certain conditions this erratum can cause a clean line eviction
292 to occur at the same time as another transaction to the same address
293 on the AMBA 5 CHI interface, which can cause data corruption if the
294 interconnect reorders the two transactions.
296 The workaround promotes data cache clean instructions to
297 data cache clean-and-invalidate.
298 Please note that this does not necessarily enable the workaround,
299 as it depends on the alternative framework, which will only patch
300 the kernel if an affected CPU is detected.
304 config ARM64_ERRATUM_824069
305 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
308 This option adds an alternative code sequence to work around ARM
309 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
310 to a coherent interconnect.
312 If a Cortex-A53 processor is executing a store or prefetch for
313 write instruction at the same time as a processor in another
314 cluster is executing a cache maintenance operation to the same
315 address, then this erratum might cause a clean cache line to be
316 incorrectly marked as dirty.
318 The workaround promotes data cache clean instructions to
319 data cache clean-and-invalidate.
320 Please note that this option does not necessarily enable the
321 workaround, as it depends on the alternative framework, which will
322 only patch the kernel if an affected CPU is detected.
326 config ARM64_ERRATUM_819472
327 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
330 This option adds an alternative code sequence to work around ARM
331 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
332 present when it is connected to a coherent interconnect.
334 If the processor is executing a load and store exclusive sequence at
335 the same time as a processor in another cluster is executing a cache
336 maintenance operation to the same address, then this erratum might
337 cause data corruption.
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_832075
348 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
351 This option adds an alternative code sequence to work around ARM
352 erratum 832075 on Cortex-A57 parts up to r1p2.
354 Affected Cortex-A57 parts might deadlock when exclusive load/store
355 instructions to Write-Back memory are mixed with Device loads.
357 The workaround is to promote device loads to use Load-Acquire
359 Please note that this does not necessarily enable the workaround,
360 as it depends on the alternative framework, which will only patch
361 the kernel if an affected CPU is detected.
365 config ARM64_ERRATUM_834220
366 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
370 This option adds an alternative code sequence to work around ARM
371 erratum 834220 on Cortex-A57 parts up to r1p2.
373 Affected Cortex-A57 parts might report a Stage 2 translation
374 fault as the result of a Stage 1 fault for load crossing a
375 page boundary when there is a permission or device memory
376 alignment fault at Stage 1 and a translation fault at Stage 2.
378 The workaround is to verify that the Stage 1 translation
379 doesn't generate a fault before handling the Stage 2 fault.
380 Please note that this does not necessarily enable the workaround,
381 as it depends on the alternative framework, which will only patch
382 the kernel if an affected CPU is detected.
386 config ARM64_ERRATUM_845719
387 bool "Cortex-A53: 845719: a load might read incorrect data"
391 This option adds an alternative code sequence to work around ARM
392 erratum 845719 on Cortex-A53 parts up to r0p4.
394 When running a compat (AArch32) userspace on an affected Cortex-A53
395 part, a load at EL0 from a virtual address that matches the bottom 32
396 bits of the virtual address used by a recent load at (AArch64) EL1
397 might return incorrect data.
399 The workaround is to write the contextidr_el1 register on exception
400 return to a 32-bit task.
401 Please note that this does not necessarily enable the workaround,
402 as it depends on the alternative framework, which will only patch
403 the kernel if an affected CPU is detected.
407 config ARM64_ERRATUM_843419
408 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
411 select ARM64_MODULE_CMODEL_LARGE
413 This option builds kernel modules using the large memory model in
414 order to avoid the use of the ADRP instruction, which can cause
415 a subsequent memory access to use an incorrect address on Cortex-A53
418 Note that the kernel itself must be linked with a version of ld
419 which fixes potentially affected ADRP instructions through the
424 config CAVIUM_ERRATUM_22375
425 bool "Cavium erratum 22375, 24313"
428 Enable workaround for erratum 22375, 24313.
430 This implements two gicv3-its errata workarounds for ThunderX. Both
431 with small impact affecting only ITS table allocation.
433 erratum 22375: only alloc 8MB table size
434 erratum 24313: ignore memory access type
436 The fixes are in ITS initialization and basically ignore memory access
437 type and table size provided by the TYPER and BASER registers.
441 config CAVIUM_ERRATUM_23154
442 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
445 The gicv3 of ThunderX requires a modified version for
446 reading the IAR status to ensure data synchronization
447 (access to icc_iar1_el1 is not sync'ed before and after).
451 config CAVIUM_ERRATUM_27456
452 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
455 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
456 instructions may cause the icache to become corrupted if it
457 contains data for a non-current ASID. The fix is to
458 invalidate the icache when changing the mm context.
467 default ARM64_4K_PAGES
469 Page size (translation granule) configuration.
471 config ARM64_4K_PAGES
474 This feature enables 4KB pages support.
476 config ARM64_16K_PAGES
479 The system will use 16KB pages support. AArch32 emulation
480 requires applications compiled with 16K (or a multiple of 16K)
483 config ARM64_64K_PAGES
486 This feature enables 64KB pages support (4KB by default)
487 allowing only two levels of page tables and faster TLB
488 look-up. AArch32 emulation requires applications compiled
489 with 64K aligned segments.
494 prompt "Virtual address space size"
495 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
496 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
497 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
499 Allows choosing one of multiple possible virtual address
500 space sizes. The level of translation table is determined by
501 a combination of page size and virtual address space size.
503 config ARM64_VA_BITS_36
504 bool "36-bit" if EXPERT
505 depends on ARM64_16K_PAGES
507 config ARM64_VA_BITS_39
509 depends on ARM64_4K_PAGES
511 config ARM64_VA_BITS_42
513 depends on ARM64_64K_PAGES
515 config ARM64_VA_BITS_47
517 depends on ARM64_16K_PAGES
519 config ARM64_VA_BITS_48
526 default 36 if ARM64_VA_BITS_36
527 default 39 if ARM64_VA_BITS_39
528 default 42 if ARM64_VA_BITS_42
529 default 47 if ARM64_VA_BITS_47
530 default 48 if ARM64_VA_BITS_48
532 config CPU_BIG_ENDIAN
533 bool "Build big-endian kernel"
535 Say Y if you plan on running a kernel in big-endian mode.
538 bool "Multi-core scheduler support"
540 Multi-core scheduler support improves the CPU scheduler's decision
541 making when dealing with multi-core CPU chips at a cost of slightly
542 increased overhead in some places. If unsure say N here.
545 bool "SMT scheduler support"
547 Improves the CPU scheduler's decision making when dealing with
548 MultiThreading at a cost of slightly increased overhead in some
549 places. If unsure say N here.
552 int "Maximum number of CPUs (2-4096)"
554 # These have to remain sorted largest to smallest
558 bool "Support for hot-pluggable CPUs"
559 select GENERIC_IRQ_MIGRATION
561 Say Y here to experiment with turning CPUs off and on. CPUs
562 can be controlled through /sys/devices/system/cpu.
564 # Common NUMA Features
566 bool "Numa Memory Allocation and Scheduler Support"
569 Enable NUMA (Non Uniform Memory Access) support.
571 The kernel will try to allocate memory used by a CPU on the
572 local memory of the CPU and add some more
573 NUMA awareness to the kernel.
576 int "Maximum NUMA Nodes (as a power of 2)"
579 depends on NEED_MULTIPLE_NODES
581 Specify the maximum number of NUMA Nodes available on the target
582 system. Increases memory reserved to accommodate various tables.
584 config USE_PERCPU_NUMA_NODE_ID
588 source kernel/Kconfig.preempt
589 source kernel/Kconfig.hz
591 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
592 depends on !HIBERNATION
595 config ARCH_HAS_HOLES_MEMORYMODEL
596 def_bool y if SPARSEMEM
598 config ARCH_SPARSEMEM_ENABLE
600 select SPARSEMEM_VMEMMAP_ENABLE
602 config ARCH_SPARSEMEM_DEFAULT
603 def_bool ARCH_SPARSEMEM_ENABLE
605 config ARCH_SELECT_MEMORY_MODEL
606 def_bool ARCH_SPARSEMEM_ENABLE
608 config HAVE_ARCH_PFN_VALID
609 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
611 config HW_PERF_EVENTS
615 config SYS_SUPPORTS_HUGETLBFS
618 config ARCH_WANT_HUGE_PMD_SHARE
619 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
621 config ARCH_HAS_CACHE_LINE_SIZE
627 bool "Enable seccomp to safely compute untrusted bytecode"
629 This kernel feature is useful for number crunching applications
630 that may need to compute untrusted bytecode during their
631 execution. By using pipes or other transports made available to
632 the process as file descriptors supporting the read/write
633 syscalls, it's possible to isolate those applications in
634 their own address space using seccomp. Once seccomp is
635 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
636 and the task is only allowed to execute a few safe syscalls
637 defined by each seccomp mode.
640 bool "Enable paravirtualization code"
642 This changes the kernel so it can modify itself when it is run
643 under a hypervisor, potentially improving performance significantly
644 over full virtualization.
646 config PARAVIRT_TIME_ACCOUNTING
647 bool "Paravirtual steal time accounting"
651 Select this option to enable fine granularity task steal time
652 accounting. Time spent executing other tasks in parallel with
653 the current vCPU is discounted from the vCPU power. To account for
654 that, there can be a small performance impact.
656 If in doubt, say N here.
663 bool "Xen guest support on ARM64"
664 depends on ARM64 && OF
668 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
670 config FORCE_MAX_ZONEORDER
672 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
673 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
676 The kernel memory allocator divides physically contiguous memory
677 blocks into "zones", where each zone is a power of two number of
678 pages. This option selects the largest power of two that the kernel
679 keeps in the memory allocator. If you need to allocate very large
680 blocks of physically contiguous memory, then you may need to
683 This config option is actually maximum order plus one. For example,
684 a value of 11 means that the largest free memory block is 2^10 pages.
686 We make sure that we can allocate upto a HugePage size for each configuration.
688 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
690 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
691 4M allocations matching the default size used by generic code.
693 menuconfig ARMV8_DEPRECATED
694 bool "Emulate deprecated/obsolete ARMv8 instructions"
697 Legacy software support may require certain instructions
698 that have been deprecated or obsoleted in the architecture.
700 Enable this config to enable selective emulation of these
708 bool "Emulate SWP/SWPB instructions"
710 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
711 they are always undefined. Say Y here to enable software
712 emulation of these instructions for userspace using LDXR/STXR.
714 In some older versions of glibc [<=2.8] SWP is used during futex
715 trylock() operations with the assumption that the code will not
716 be preempted. This invalid assumption may be more likely to fail
717 with SWP emulation enabled, leading to deadlock of the user
720 NOTE: when accessing uncached shared regions, LDXR/STXR rely
721 on an external transaction monitoring block called a global
722 monitor to maintain update atomicity. If your system does not
723 implement a global monitor, this option can cause programs that
724 perform SWP operations to uncached memory to deadlock.
728 config CP15_BARRIER_EMULATION
729 bool "Emulate CP15 Barrier instructions"
731 The CP15 barrier instructions - CP15ISB, CP15DSB, and
732 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
733 strongly recommended to use the ISB, DSB, and DMB
734 instructions instead.
736 Say Y here to enable software emulation of these
737 instructions for AArch32 userspace code. When this option is
738 enabled, CP15 barrier usage is traced which can help
739 identify software that needs updating.
743 config SETEND_EMULATION
744 bool "Emulate SETEND instruction"
746 The SETEND instruction alters the data-endianness of the
747 AArch32 EL0, and is deprecated in ARMv8.
749 Say Y here to enable software emulation of the instruction
750 for AArch32 userspace code.
752 Note: All the cpus on the system must have mixed endian support at EL0
753 for this feature to be enabled. If a new CPU - which doesn't support mixed
754 endian - is hotplugged in after this feature has been enabled, there could
755 be unexpected results in the applications.
760 menu "ARMv8.1 architectural features"
762 config ARM64_HW_AFDBM
763 bool "Support for hardware updates of the Access and Dirty page flags"
766 The ARMv8.1 architecture extensions introduce support for
767 hardware updates of the access and dirty information in page
768 table entries. When enabled in TCR_EL1 (HA and HD bits) on
769 capable processors, accesses to pages with PTE_AF cleared will
770 set this bit instead of raising an access flag fault.
771 Similarly, writes to read-only pages with the DBM bit set will
772 clear the read-only bit (AP[2]) instead of raising a
775 Kernels built with this configuration option enabled continue
776 to work on pre-ARMv8.1 hardware and the performance impact is
777 minimal. If unsure, say Y.
780 bool "Enable support for Privileged Access Never (PAN)"
783 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
784 prevents the kernel or hypervisor from accessing user-space (EL0)
787 Choosing this option will cause any unprotected (not using
788 copy_to_user et al) memory access to fail with a permission fault.
790 The feature is detected at runtime, and will remain as a 'nop'
791 instruction if the cpu does not implement the feature.
793 config ARM64_LSE_ATOMICS
794 bool "Atomic instructions"
796 As part of the Large System Extensions, ARMv8.1 introduces new
797 atomic instructions that are designed specifically to scale in
800 Say Y here to make use of these instructions for the in-kernel
801 atomic routines. This incurs a small overhead on CPUs that do
802 not support these instructions and requires the kernel to be
803 built with binutils >= 2.25.
806 bool "Enable support for Virtualization Host Extensions (VHE)"
809 Virtualization Host Extensions (VHE) allow the kernel to run
810 directly at EL2 (instead of EL1) on processors that support
811 it. This leads to better performance for KVM, as they reduce
812 the cost of the world switch.
814 Selecting this option allows the VHE feature to be detected
815 at runtime, and does not affect processors that do not
816 implement this feature.
820 menu "ARMv8.2 architectural features"
823 bool "Enable support for User Access Override (UAO)"
826 User Access Override (UAO; part of the ARMv8.2 Extensions)
827 causes the 'unprivileged' variant of the load/store instructions to
828 be overriden to be privileged.
830 This option changes get_user() and friends to use the 'unprivileged'
831 variant of the load/store instructions. This ensures that user-space
832 really did have access to the supplied memory. When addr_limit is
833 set to kernel memory the UAO bit will be set, allowing privileged
834 access to kernel memory.
836 Choosing this option will cause copy_to_user() et al to use user-space
839 The feature is detected at runtime, the kernel will use the
840 regular load/store instructions if the cpu does not implement the
845 config ARM64_MODULE_CMODEL_LARGE
848 config ARM64_MODULE_PLTS
850 select ARM64_MODULE_CMODEL_LARGE
851 select HAVE_MOD_ARCH_SPECIFIC
856 This builds the kernel as a Position Independent Executable (PIE),
857 which retains all relocation metadata required to relocate the
858 kernel binary at runtime to a different virtual address than the
859 address it was linked at.
860 Since AArch64 uses the RELA relocation format, this requires a
861 relocation pass at runtime even if the kernel is loaded at the
862 same address it was linked at.
864 config RANDOMIZE_BASE
865 bool "Randomize the address of the kernel image"
866 select ARM64_MODULE_PLTS
869 Randomizes the virtual address at which the kernel image is
870 loaded, as a security feature that deters exploit attempts
871 relying on knowledge of the location of kernel internals.
873 It is the bootloader's job to provide entropy, by passing a
874 random u64 value in /chosen/kaslr-seed at kernel entry.
876 When booting via the UEFI stub, it will invoke the firmware's
877 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
878 to the kernel proper. In addition, it will randomise the physical
879 location of the kernel Image as well.
883 config RANDOMIZE_MODULE_REGION_FULL
884 bool "Randomize the module region independently from the core kernel"
885 depends on RANDOMIZE_BASE
888 Randomizes the location of the module region without considering the
889 location of the core kernel. This way, it is impossible for modules
890 to leak information about the location of core kernel data structures
891 but it does imply that function calls between modules and the core
892 kernel will need to be resolved via veneers in the module PLT.
894 When this option is not set, the module region will be randomized over
895 a limited range that contains the [_stext, _etext] interval of the
896 core kernel, so branch relocations are always in range.
902 config ARM64_ACPI_PARKING_PROTOCOL
903 bool "Enable support for the ARM64 ACPI parking protocol"
906 Enable support for the ARM64 ACPI parking protocol. If disabled
907 the kernel will not allow booting through the ARM64 ACPI parking
908 protocol even if the corresponding data is present in the ACPI
912 string "Default kernel command string"
915 Provide a set of default command-line options at build time by
916 entering them here. As a minimum, you should specify the the
917 root device (e.g. root=/dev/nfs).
920 bool "Always use the default kernel command string"
922 Always use the default kernel command string, even if the boot
923 loader passes other arguments to the kernel.
924 This is useful if you cannot or don't want to change the
925 command-line options your boot loader passes to the kernel.
931 bool "UEFI runtime support"
932 depends on OF && !CPU_BIG_ENDIAN
935 select EFI_PARAMS_FROM_FDT
936 select EFI_RUNTIME_WRAPPERS
941 This option provides support for runtime services provided
942 by UEFI firmware (such as non-volatile variables, realtime
943 clock, and platform reset). A UEFI stub is also provided to
944 allow the kernel to be booted as an EFI application. This
945 is only useful on systems that have UEFI firmware.
948 bool "Enable support for SMBIOS (DMI) tables"
952 This enables SMBIOS/DMI feature for systems.
954 This option is only useful on systems that have UEFI firmware.
955 However, even with this option, the resultant kernel should
956 continue to boot on existing non-UEFI platforms.
960 menu "Userspace binary formats"
962 source "fs/Kconfig.binfmt"
965 bool "Kernel support for 32-bit EL0"
966 depends on ARM64_4K_PAGES || EXPERT
967 select COMPAT_BINFMT_ELF
969 select OLD_SIGSUSPEND3
970 select COMPAT_OLD_SIGACTION
972 This option enables support for a 32-bit EL0 running under a 64-bit
973 kernel at EL1. AArch32-specific components such as system calls,
974 the user helper functions, VFP support and the ptrace interface are
975 handled appropriately by the kernel.
977 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
978 that you will only be able to execute AArch32 binaries that were compiled
979 with page size aligned segments.
981 If you want to execute 32-bit userspace applications, say Y.
983 config SYSVIPC_COMPAT
985 depends on COMPAT && SYSVIPC
989 menu "Power management options"
991 source "kernel/power/Kconfig"
993 config ARCH_HIBERNATION_POSSIBLE
997 config ARCH_HIBERNATION_HEADER
999 depends on HIBERNATION
1001 config ARCH_SUSPEND_POSSIBLE
1006 menu "CPU Power Management"
1008 source "drivers/cpuidle/Kconfig"
1010 source "drivers/cpufreq/Kconfig"
1014 source "net/Kconfig"
1016 source "drivers/Kconfig"
1018 source "drivers/firmware/Kconfig"
1020 source "drivers/acpi/Kconfig"
1024 source "arch/arm64/kvm/Kconfig"
1026 source "arch/arm64/Kconfig.debug"
1028 source "security/Kconfig"
1030 source "crypto/Kconfig"
1032 source "arch/arm64/crypto/Kconfig"
1035 source "lib/Kconfig"