arch/arm64/boot/dts/hisilicon/hi6220.dtsi

   1 /*
   2  * dts file for Hisilicon Hi6220 SoC
   3  *
   4  * Copyright (C) 2015, Hisilicon Ltd.
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/hi6220-clock.h>
   9 #include <dt-bindings/pinctrl/hisi.h>
  10
  11 / {
  12         compatible = "hisilicon,hi6220";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         psci {
  18                 compatible = "arm,psci-0.2";
  19                 method = "smc";
  20         };
  21
  22         cpus {
  23                 #address-cells = <2>;
  24                 #size-cells = <0>;
  25
  26                 cpu-map {
  27                         cluster0 {
  28                                 core0 {
  29                                         cpu = <&cpu0>;
  30                                 };
  31                                 core1 {
  32                                         cpu = <&cpu1>;
  33                                 };
  34                                 core2 {
  35                                         cpu = <&cpu2>;
  36                                 };
  37                                 core3 {
  38                                         cpu = <&cpu3>;
  39                                 };
  40                         };
  41                         cluster1 {
  42                                 core0 {
  43                                         cpu = <&cpu4>;
  44                                 };
  45                                 core1 {
  46                                         cpu = <&cpu5>;
  47                                 };
  48                                 core2 {
  49                                         cpu = <&cpu6>;
  50                                 };
  51                                 core3 {
  52                                         cpu = <&cpu7>;
  53                                 };
  54                         };
  55                 };
  56
  57                 idle-states {
  58                         entry-method = "psci";
  59
  60                         CPU_SLEEP: cpu-sleep {
  61                                 compatible = "arm,idle-state";
  62                                 local-timer-stop;
  63                                 arm,psci-suspend-param = <0x0010000>;
  64                                 entry-latency-us = <700>;
  65                                 exit-latency-us = <250>;
  66                                 min-residency-us = <1000>;
  67                         };
  68
  69                         CLUSTER_SLEEP: cluster-sleep {
  70                                 compatible = "arm,idle-state";
  71                                 local-timer-stop;
  72                                 arm,psci-suspend-param = <0x1010000>;
  73                                 entry-latency-us = <1000>;
  74                                 exit-latency-us = <700>;
  75                                 min-residency-us = <2700>;
  76                                 wakeup-latency-us = <1500>;
  77                         };
  78                 };
  79
  80                 cpu0: cpu@0 {
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         device_type = "cpu";
  83                         reg = <0x0 0x0>;
  84                         enable-method = "psci";
  85                         clocks = <&stub_clock 0>;
  86                         operating-points-v2 = <&cpu_opp_table>;
  87                         cooling-min-level = <4>;
  88                         cooling-max-level = <0>;
  89                         #cooling-cells = <2>; /* min followed by max */
  90                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  91                 };
  92
  93                 cpu1: cpu@1 {
  94                         compatible = "arm,cortex-a53", "arm,armv8";
  95                         device_type = "cpu";
  96                         reg = <0x0 0x1>;
  97                         enable-method = "psci";
  98                         operating-points-v2 = <&cpu_opp_table>;
  99                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 100                 };
 101
 102                 cpu2: cpu@2 {
 103                         compatible = "arm,cortex-a53", "arm,armv8";
 104                         device_type = "cpu";
 105                         reg = <0x0 0x2>;
 106                         enable-method = "psci";
 107                         operating-points-v2 = <&cpu_opp_table>;
 108                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 109                 };
 110
 111                 cpu3: cpu@3 {
 112                         compatible = "arm,cortex-a53", "arm,armv8";
 113                         device_type = "cpu";
 114                         reg = <0x0 0x3>;
 115                         enable-method = "psci";
 116                         operating-points-v2 = <&cpu_opp_table>;
 117                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 118                 };
 119
 120                 cpu4: cpu@100 {
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         device_type = "cpu";
 123                         reg = <0x0 0x100>;
 124                         enable-method = "psci";
 125                         operating-points-v2 = <&cpu_opp_table>;
 126                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 127                 };
 128
 129                 cpu5: cpu@101 {
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         device_type = "cpu";
 132                         reg = <0x0 0x101>;
 133                         enable-method = "psci";
 134                         operating-points-v2 = <&cpu_opp_table>;
 135                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 136                 };
 137
 138                 cpu6: cpu@102 {
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         device_type = "cpu";
 141                         reg = <0x0 0x102>;
 142                         enable-method = "psci";
 143                         operating-points-v2 = <&cpu_opp_table>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 145                 };
 146
 147                 cpu7: cpu@103 {
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         device_type = "cpu";
 150                         reg = <0x0 0x103>;
 151                         enable-method = "psci";
 152                         operating-points-v2 = <&cpu_opp_table>;
 153                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 154                 };
 155         };
 156
 157         cpu_opp_table: cpu_opp_table {
 158                 compatible = "operating-points-v2";
 159                 opp-shared;
 160
 161                 opp00 {
 162                         opp-hz = /bits/ 64 <208000000>;
 163                         opp-microvolt = <1040000>;
 164                         clock-latency-ns = <500000>;
 165                 };
 166                 opp01 {
 167                         opp-hz = /bits/ 64 <432000000>;
 168                         opp-microvolt = <1040000>;
 169                         clock-latency-ns = <500000>;
 170                 };
 171                 opp02 {
 172                         opp-hz = /bits/ 64 <729000000>;
 173                         opp-microvolt = <1090000>;
 174                         clock-latency-ns = <500000>;
 175                 };
 176                 opp03 {
 177                         opp-hz = /bits/ 64 <960000000>;
 178                         opp-microvolt = <1180000>;
 179                         clock-latency-ns = <500000>;
 180                 };
 181                 opp04 {
 182                         opp-hz = /bits/ 64 <1200000000>;
 183                         opp-microvolt = <1330000>;
 184                         clock-latency-ns = <500000>;
 185                 };
 186         };
 187
 188         gic: interrupt-controller@f6801000 {
 189                 compatible = "arm,gic-400";
 190                 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
 191                       <0x0 0xf6802000 0 0x2000>, /* GICC */
 192                       <0x0 0xf6804000 0 0x2000>, /* GICH */
 193                       <0x0 0xf6806000 0 0x2000>; /* GICV */
 194                 #address-cells = <0>;
 195                 #interrupt-cells = <3>;
 196                 interrupt-controller;
 197                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 198         };
 199
 200         timer {
 201                 compatible = "arm,armv8-timer";
 202                 interrupt-parent = <&gic>;
 203                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 204                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 205                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 206                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 207         };
 208
 209         soc {
 210                 compatible = "simple-bus";
 211                 #address-cells = <2>;
 212                 #size-cells = <2>;
 213                 ranges;
 214
 215                 sram: sram@fff80000 {
 216                         compatible = "hisilicon,hi6220-sramctrl", "syscon";
 217                         reg = <0x0 0xfff80000 0x0 0x12000>;
 218                 };
 219
 220                 ao_ctrl: ao_ctrl@f7800000 {
 221                         compatible = "hisilicon,hi6220-aoctrl", "syscon";
 222                         reg = <0x0 0xf7800000 0x0 0x2000>;
 223                         #clock-cells = <1>;
 224                 };
 225
 226                 sys_ctrl: sys_ctrl@f7030000 {
 227                         compatible = "hisilicon,hi6220-sysctrl", "syscon";
 228                         reg = <0x0 0xf7030000 0x0 0x2000>;
 229                         #clock-cells = <1>;
 230                         #reset-cells = <1>;
 231                 };
 232
 233                 media_ctrl: media_ctrl@f4410000 {
 234                         compatible = "hisilicon,hi6220-mediactrl", "syscon";
 235                         reg = <0x0 0xf4410000 0x0 0x1000>;
 236                         #clock-cells = <1>;
 237                 };
 238
 239                 pm_ctrl: pm_ctrl@f7032000 {
 240                         compatible = "hisilicon,hi6220-pmctrl", "syscon";
 241                         reg = <0x0 0xf7032000 0x0 0x1000>;
 242                         #clock-cells = <1>;
 243                 };
 244
 245                 stub_clock: stub_clock {
 246                         compatible = "hisilicon,hi6220-stub-clk";
 247                         hisilicon,hi6220-clk-sram = <&sram>;
 248                         #clock-cells = <1>;
 249                         mbox-names = "mbox-tx";
 250                         mboxes = <&mailbox 1 0 11>;
 251                 };
 252
 253                 uart0: uart@f8015000 {  /* console */
 254                         compatible = "arm,pl011", "arm,primecell";
 255                         reg = <0x0 0xf8015000 0x0 0x1000>;
 256                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 258                                  <&ao_ctrl HI6220_UART0_PCLK>;
 259                         clock-names = "uartclk", "apb_pclk";
 260                 };
 261
 262                 uart1: uart@f7111000 {
 263                         compatible = "arm,pl011", "arm,primecell";
 264                         reg = <0x0 0xf7111000 0x0 0x1000>;
 265                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 266                         clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 267                                  <&sys_ctrl HI6220_UART1_PCLK>;
 268                         clock-names = "uartclk", "apb_pclk";
 269                         status = "disabled";
 270                 };
 271
 272                 uart2: uart@f7112000 {
 273                         compatible = "arm,pl011", "arm,primecell";
 274                         reg = <0x0 0xf7112000 0x0 0x1000>;
 275                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 277                                  <&sys_ctrl HI6220_UART2_PCLK>;
 278                         clock-names = "uartclk", "apb_pclk";
 279                         status = "disabled";
 280                 };
 281
 282                 uart3: uart@f7113000 {
 283                         compatible = "arm,pl011", "arm,primecell";
 284                         reg = <0x0 0xf7113000 0x0 0x1000>;
 285                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 286                         clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 287                                  <&sys_ctrl HI6220_UART3_PCLK>;
 288                         clock-names = "uartclk", "apb_pclk";
 289                 };
 290
 291                 uart4: uart@f7114000 {
 292                         compatible = "arm,pl011", "arm,primecell";
 293                         reg = <0x0 0xf7114000 0x0 0x1000>;
 294                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 295                         clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 296                                  <&sys_ctrl HI6220_UART4_PCLK>;
 297                         clock-names = "uartclk", "apb_pclk";
 298                         status = "disabled";
 299                 };
 300
 301                 dual_timer0: timer@f8008000 {
 302                         compatible = "arm,sp804", "arm,primecell";
 303                         reg = <0x0 0xf8008000 0x0 0x1000>;
 304                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
 307                                  <&ao_ctrl HI6220_TIMER0_PCLK>,
 308                                  <&ao_ctrl HI6220_TIMER0_PCLK>;
 309                         clock-names = "timer1", "timer2", "apb_pclk";
 310                 };
 311
 312                 pmx0: pinmux@f7010000 {
 313                         compatible = "pinctrl-single";
 314                         reg = <0x0 0xf7010000  0x0 0x27c>;
 315                         #address-cells = <1>;
 316                         #size-cells = <1>;
 317                         #gpio-range-cells = <3>;
 318                         pinctrl-single,register-width = <32>;
 319                         pinctrl-single,function-mask = <7>;
 320                         pinctrl-single,gpio-range = <
 321                                 &range  80  8 MUX_M0 /* gpio  3: [0..7] */
 322                                 &range  88  8 MUX_M0 /* gpio  4: [0..7] */
 323                                 &range  96  8 MUX_M0 /* gpio  5: [0..7] */
 324                                 &range 104  8 MUX_M0 /* gpio  6: [0..7] */
 325                                 &range 112  8 MUX_M0 /* gpio  7: [0..7] */
 326                                 &range 120  2 MUX_M0 /* gpio  8: [0..1] */
 327                                 &range   2  6 MUX_M1 /* gpio  8: [2..7] */
 328                                 &range   8  8 MUX_M1 /* gpio  9: [0..7] */
 329                                 &range   0  1 MUX_M1 /* gpio 10: [0]    */
 330                                 &range  16  7 MUX_M1 /* gpio 10: [1..7] */
 331                                 &range  23  3 MUX_M1 /* gpio 11: [0..2] */
 332                                 &range  28  5 MUX_M1 /* gpio 11: [3..7] */
 333                                 &range  33  3 MUX_M1 /* gpio 12: [0..2] */
 334                                 &range  43  5 MUX_M1 /* gpio 12: [3..7] */
 335                                 &range  48  8 MUX_M1 /* gpio 13: [0..7] */
 336                                 &range  56  8 MUX_M1 /* gpio 14: [0..7] */
 337                                 &range  74  6 MUX_M1 /* gpio 15: [0..5] */
 338                                 &range 122  1 MUX_M1 /* gpio 15: [6]    */
 339                                 &range 126  1 MUX_M1 /* gpio 15: [7]    */
 340                                 &range 127  8 MUX_M1 /* gpio 16: [0..7] */
 341                                 &range 135  8 MUX_M1 /* gpio 17: [0..7] */
 342                                 &range 143  8 MUX_M1 /* gpio 18: [0..7] */
 343                                 &range 151  8 MUX_M1 /* gpio 19: [0..7] */
 344                         >;
 345                         range: gpio-range {
 346                                 #pinctrl-single,gpio-range-cells = <3>;
 347                         };
 348                 };
 349
 350                 pmx1: pinmux@f7010800 {
 351                         compatible = "pinconf-single";
 352                         reg = <0x0 0xf7010800 0x0 0x28c>;
 353                         #address-cells = <1>;
 354                         #size-cells = <1>;
 355                         pinctrl-single,register-width = <32>;
 356                 };
 357
 358                 pmx2: pinmux@f8001800 {
 359                         compatible = "pinconf-single";
 360                         reg = <0x0 0xf8001800 0x0 0x78>;
 361                         #address-cells = <1>;
 362                         #size-cells = <1>;
 363                         pinctrl-single,register-width = <32>;
 364                 };
 365
 366                 gpio0: gpio@f8011000 {
 367                         compatible = "arm,pl061", "arm,primecell";
 368                         reg = <0x0 0xf8011000 0x0 0x1000>;
 369                         interrupts = <0 52 0x4>;
 370                         gpio-controller;
 371                         #gpio-cells = <2>;
 372                         interrupt-controller;
 373                         #interrupt-cells = <2>;
 374                         clocks = <&ao_ctrl 2>;
 375                         clock-names = "apb_pclk";
 376                 };
 377
 378                 gpio1: gpio@f8012000 {
 379                         compatible = "arm,pl061", "arm,primecell";
 380                         reg = <0x0 0xf8012000 0x0 0x1000>;
 381                         interrupts = <0 53 0x4>;
 382                         gpio-controller;
 383                         #gpio-cells = <2>;
 384                         interrupt-controller;
 385                         #interrupt-cells = <2>;
 386                         clocks = <&ao_ctrl 2>;
 387                         clock-names = "apb_pclk";
 388                 };
 389
 390                 gpio2: gpio@f8013000 {
 391                         compatible = "arm,pl061", "arm,primecell";
 392                         reg = <0x0 0xf8013000 0x0 0x1000>;
 393                         interrupts = <0 54 0x4>;
 394                         gpio-controller;
 395                         #gpio-cells = <2>;
 396                         interrupt-controller;
 397                         #interrupt-cells = <2>;
 398                         clocks = <&ao_ctrl 2>;
 399                         clock-names = "apb_pclk";
 400                 };
 401
 402                 gpio3: gpio@f8014000 {
 403                         compatible = "arm,pl061", "arm,primecell";
 404                         reg = <0x0 0xf8014000 0x0 0x1000>;
 405                         interrupts = <0 55 0x4>;
 406                         gpio-controller;
 407                         #gpio-cells = <2>;
 408                         gpio-ranges = <&pmx0 0 80 8>;
 409                         interrupt-controller;
 410                         #interrupt-cells = <2>;
 411                         clocks = <&ao_ctrl 2>;
 412                         clock-names = "apb_pclk";
 413                 };
 414
 415                 gpio4: gpio@f7020000 {
 416                         compatible = "arm,pl061", "arm,primecell";
 417                         reg = <0x0 0xf7020000 0x0 0x1000>;
 418                         interrupts = <0 56 0x4>;
 419                         gpio-controller;
 420                         #gpio-cells = <2>;
 421                         gpio-ranges = <&pmx0 0 88 8>;
 422                         interrupt-controller;
 423                         #interrupt-cells = <2>;
 424                         clocks = <&ao_ctrl 2>;
 425                         clock-names = "apb_pclk";
 426                 };
 427
 428                 gpio5: gpio@f7021000 {
 429                         compatible = "arm,pl061", "arm,primecell";
 430                         reg = <0x0 0xf7021000 0x0 0x1000>;
 431                         interrupts = <0 57 0x4>;
 432                         gpio-controller;
 433                         #gpio-cells = <2>;
 434                         gpio-ranges = <&pmx0 0 96 8>;
 435                         interrupt-controller;
 436                         #interrupt-cells = <2>;
 437                         clocks = <&ao_ctrl 2>;
 438                         clock-names = "apb_pclk";
 439                 };
 440
 441                 gpio6: gpio@f7022000 {
 442                         compatible = "arm,pl061", "arm,primecell";
 443                         reg = <0x0 0xf7022000 0x0 0x1000>;
 444                         interrupts = <0 58 0x4>;
 445                         gpio-controller;
 446                         #gpio-cells = <2>;
 447                         gpio-ranges = <&pmx0 0 104 8>;
 448                         interrupt-controller;
 449                         #interrupt-cells = <2>;
 450                         clocks = <&ao_ctrl 2>;
 451                         clock-names = "apb_pclk";
 452                 };
 453
 454                 gpio7: gpio@f7023000 {
 455                         compatible = "arm,pl061", "arm,primecell";
 456                         reg = <0x0 0xf7023000 0x0 0x1000>;
 457                         interrupts = <0 59 0x4>;
 458                         gpio-controller;
 459                         #gpio-cells = <2>;
 460                         gpio-ranges = <&pmx0 0 112 8>;
 461                         interrupt-controller;
 462                         #interrupt-cells = <2>;
 463                         clocks = <&ao_ctrl 2>;
 464                         clock-names = "apb_pclk";
 465                 };
 466
 467                 gpio8: gpio@f7024000 {
 468                         compatible = "arm,pl061", "arm,primecell";
 469                         reg = <0x0 0xf7024000 0x0 0x1000>;
 470                         interrupts = <0 60 0x4>;
 471                         gpio-controller;
 472                         #gpio-cells = <2>;
 473                         gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
 474                         interrupt-controller;
 475                         #interrupt-cells = <2>;
 476                         clocks = <&ao_ctrl 2>;
 477                         clock-names = "apb_pclk";
 478                 };
 479
 480                 gpio9: gpio@f7025000 {
 481                         compatible = "arm,pl061", "arm,primecell";
 482                         reg = <0x0 0xf7025000 0x0 0x1000>;
 483                         interrupts = <0 61 0x4>;
 484                         gpio-controller;
 485                         #gpio-cells = <2>;
 486                         gpio-ranges = <&pmx0 0 8 8>;
 487                         interrupt-controller;
 488                         #interrupt-cells = <2>;
 489                         clocks = <&ao_ctrl 2>;
 490                         clock-names = "apb_pclk";
 491                 };
 492
 493                 gpio10: gpio@f7026000 {
 494                         compatible = "arm,pl061", "arm,primecell";
 495                         reg = <0x0 0xf7026000 0x0 0x1000>;
 496                         interrupts = <0 62 0x4>;
 497                         gpio-controller;
 498                         #gpio-cells = <2>;
 499                         gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
 500                         interrupt-controller;
 501                         #interrupt-cells = <2>;
 502                         clocks = <&ao_ctrl 2>;
 503                         clock-names = "apb_pclk";
 504                 };
 505
 506                 gpio11: gpio@f7027000 {
 507                         compatible = "arm,pl061", "arm,primecell";
 508                         reg = <0x0 0xf7027000 0x0 0x1000>;
 509                         interrupts = <0 63 0x4>;
 510                         gpio-controller;
 511                         #gpio-cells = <2>;
 512                         gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
 513                         interrupt-controller;
 514                         #interrupt-cells = <2>;
 515                         clocks = <&ao_ctrl 2>;
 516                         clock-names = "apb_pclk";
 517                 };
 518
 519                 gpio12: gpio@f7028000 {
 520                         compatible = "arm,pl061", "arm,primecell";
 521                         reg = <0x0 0xf7028000 0x0 0x1000>;
 522                         interrupts = <0 64 0x4>;
 523                         gpio-controller;
 524                         #gpio-cells = <2>;
 525                         gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
 526                         interrupt-controller;
 527                         #interrupt-cells = <2>;
 528                         clocks = <&ao_ctrl 2>;
 529                         clock-names = "apb_pclk";
 530                 };
 531
 532                 gpio13: gpio@f7029000 {
 533                         compatible = "arm,pl061", "arm,primecell";
 534                         reg = <0x0 0xf7029000 0x0 0x1000>;
 535                         interrupts = <0 65 0x4>;
 536                         gpio-controller;
 537                         #gpio-cells = <2>;
 538                         gpio-ranges = <&pmx0 0 48 8>;
 539                         interrupt-controller;
 540                         #interrupt-cells = <2>;
 541                         clocks = <&ao_ctrl 2>;
 542                         clock-names = "apb_pclk";
 543                 };
 544
 545                 gpio14: gpio@f702a000 {
 546                         compatible = "arm,pl061", "arm,primecell";
 547                         reg = <0x0 0xf702a000 0x0 0x1000>;
 548                         interrupts = <0 66 0x4>;
 549                         gpio-controller;
 550                         #gpio-cells = <2>;
 551                         gpio-ranges = <&pmx0 0 56 8>;
 552                         interrupt-controller;
 553                         #interrupt-cells = <2>;
 554                         clocks = <&ao_ctrl 2>;
 555                         clock-names = "apb_pclk";
 556                 };
 557
 558                 gpio15: gpio@f702b000 {
 559                         compatible = "arm,pl061", "arm,primecell";
 560                         reg = <0x0 0xf702b000 0x0 0x1000>;
 561                         interrupts = <0 67 0x4>;
 562                         gpio-controller;
 563                         #gpio-cells = <2>;
 564                         gpio-ranges = <
 565                                 &pmx0 0 74 6
 566                                 &pmx0 6 122 1
 567                                 &pmx0 7 126 1
 568                         >;
 569                         interrupt-controller;
 570                         #interrupt-cells = <2>;
 571                         clocks = <&ao_ctrl 2>;
 572                         clock-names = "apb_pclk";
 573                 };
 574
 575                 gpio16: gpio@f702c000 {
 576                         compatible = "arm,pl061", "arm,primecell";
 577                         reg = <0x0 0xf702c000 0x0 0x1000>;
 578                         interrupts = <0 68 0x4>;
 579                         gpio-controller;
 580                         #gpio-cells = <2>;
 581                         gpio-ranges = <&pmx0 0 127 8>;
 582                         interrupt-controller;
 583                         #interrupt-cells = <2>;
 584                         clocks = <&ao_ctrl 2>;
 585                         clock-names = "apb_pclk";
 586                 };
 587
 588                 gpio17: gpio@f702d000 {
 589                         compatible = "arm,pl061", "arm,primecell";
 590                         reg = <0x0 0xf702d000 0x0 0x1000>;
 591                         interrupts = <0 69 0x4>;
 592                         gpio-controller;
 593                         #gpio-cells = <2>;
 594                         gpio-ranges = <&pmx0 0 135 8>;
 595                         interrupt-controller;
 596                         #interrupt-cells = <2>;
 597                         clocks = <&ao_ctrl 2>;
 598                         clock-names = "apb_pclk";
 599                 };
 600
 601                 gpio18: gpio@f702e000 {
 602                         compatible = "arm,pl061", "arm,primecell";
 603                         reg = <0x0 0xf702e000 0x0 0x1000>;
 604                         interrupts = <0 70 0x4>;
 605                         gpio-controller;
 606                         #gpio-cells = <2>;
 607                         gpio-ranges = <&pmx0 0 143 8>;
 608                         interrupt-controller;
 609                         #interrupt-cells = <2>;
 610                         clocks = <&ao_ctrl 2>;
 611                         clock-names = "apb_pclk";
 612                 };
 613
 614                 gpio19: gpio@f702f000 {
 615                         compatible = "arm,pl061", "arm,primecell";
 616                         reg = <0x0 0xf702f000 0x0 0x1000>;
 617                         interrupts = <0 71 0x4>;
 618                         gpio-controller;
 619                         #gpio-cells = <2>;
 620                         gpio-ranges = <&pmx0 0 151 8>;
 621                         interrupt-controller;
 622                         #interrupt-cells = <2>;
 623                         clocks = <&ao_ctrl 2>;
 624                         clock-names = "apb_pclk";
 625                 };
 626
 627                 spi0: spi@f7106000 {
 628                         compatible = "arm,pl022", "arm,primecell";
 629                         reg = <0x0 0xf7106000 0x0 0x1000>;
 630                         interrupts = <0 50 4>;
 631                         bus-id = <0>;
 632                         enable-dma = <0>;
 633                         clocks = <&sys_ctrl HI6220_SPI_CLK>;
 634                         clock-names = "apb_pclk";
 635                         pinctrl-names = "default";
 636                         pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
 637                         num-cs = <1>;
 638                         cs-gpios = <&gpio6 2 0>;
 639                         status = "disabled";
 640                 };
 641
 642                 i2c0: i2c@f7100000 {
 643                         compatible = "snps,designware-i2c";
 644                         reg = <0x0 0xf7100000 0x0 0x1000>;
 645                         interrupts = <0 44 4>;
 646                         clocks = <&sys_ctrl HI6220_I2C0_CLK>;
 647                         i2c-sda-hold-time-ns = <300>;
 648                         pinctrl-names = "default";
 649                         pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
 650                         status = "disabled";
 651                 };
 652
 653                 i2c1: i2c@f7101000 {
 654                         compatible = "snps,designware-i2c";
 655                         reg = <0x0 0xf7101000 0x0 0x1000>;
 656                         clocks = <&sys_ctrl HI6220_I2C1_CLK>;
 657                         interrupts = <0 45 4>;
 658                         i2c-sda-hold-time-ns = <300>;
 659                         pinctrl-names = "default";
 660                         pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
 661                         status = "disabled";
 662                 };
 663
 664                 i2c2: i2c@f7102000 {
 665                         compatible = "snps,designware-i2c";
 666                         reg = <0x0 0xf7102000 0x0 0x1000>;
 667                         clocks = <&sys_ctrl HI6220_I2C2_CLK>;
 668                         interrupts = <0 46 4>;
 669                         i2c-sda-hold-time-ns = <300>;
 670                         pinctrl-names = "default";
 671                         pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
 672                         status = "disabled";
 673                 };
 674
 675                 fixed_5v_hub: regulator@0 {
 676                         compatible = "regulator-fixed";
 677                         regulator-name = "fixed_5v_hub";
 678                         regulator-min-microvolt = <5000000>;
 679                         regulator-max-microvolt = <5000000>;
 680                         regulator-boot-on;
 681                         gpio = <&gpio0 7 0>;
 682                         regulator-always-on;
 683                 };
 684
 685                 usb_phy: usbphy {
 686                         compatible = "hisilicon,hi6220-usb-phy";
 687                         #phy-cells = <0>;
 688                         phy-supply = <&fixed_5v_hub>;
 689                         hisilicon,peripheral-syscon = <&sys_ctrl>;
 690                 };
 691
 692                 usb: usb@f72c0000 {
 693                         compatible = "hisilicon,hi6220-usb";
 694                         reg = <0x0 0xf72c0000 0x0 0x40000>;
 695                         phys = <&usb_phy>;
 696                         phy-names = "usb2-phy";
 697                         clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
 698                         clock-names = "otg";
 699                         dr_mode = "otg";
 700                         g-use-dma;
 701                         g-rx-fifo-size = <512>;
 702                         g-np-tx-fifo-size = <128>;
 703                         g-tx-fifo-size = <128 128 128 128 128 128>;
 704                         interrupts = <0 77 0x4>;
 705                 };
 706
 707                 mailbox: mailbox@f7510000 {
 708                         compatible = "hisilicon,hi6220-mbox";
 709                         reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
 710                               <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
 711                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 712                         #mbox-cells = <3>;
 713                 };
 714         };
 715 };