2 * dts file for Hisilicon D03 Development Board
4 * Copyright (C) 2016 Hisilicon Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip06-d03";
16 interrupt-parent = <&gic>;
21 compatible = "arm,psci-0.2";
90 compatible = "arm,cortex-a57", "arm,armv8";
92 enable-method = "psci";
93 next-level-cache = <&cluster0_l2>;
98 compatible = "arm,cortex-a57", "arm,armv8";
100 enable-method = "psci";
101 next-level-cache = <&cluster0_l2>;
106 compatible = "arm,cortex-a57", "arm,armv8";
108 enable-method = "psci";
109 next-level-cache = <&cluster0_l2>;
114 compatible = "arm,cortex-a57", "arm,armv8";
116 enable-method = "psci";
117 next-level-cache = <&cluster0_l2>;
122 compatible = "arm,cortex-a57", "arm,armv8";
124 enable-method = "psci";
125 next-level-cache = <&cluster1_l2>;
130 compatible = "arm,cortex-a57", "arm,armv8";
132 enable-method = "psci";
133 next-level-cache = <&cluster1_l2>;
138 compatible = "arm,cortex-a57", "arm,armv8";
140 enable-method = "psci";
141 next-level-cache = <&cluster1_l2>;
146 compatible = "arm,cortex-a57", "arm,armv8";
148 enable-method = "psci";
149 next-level-cache = <&cluster1_l2>;
154 compatible = "arm,cortex-a57", "arm,armv8";
156 enable-method = "psci";
157 next-level-cache = <&cluster2_l2>;
162 compatible = "arm,cortex-a57", "arm,armv8";
164 enable-method = "psci";
165 next-level-cache = <&cluster2_l2>;
170 compatible = "arm,cortex-a57", "arm,armv8";
172 enable-method = "psci";
173 next-level-cache = <&cluster2_l2>;
178 compatible = "arm,cortex-a57", "arm,armv8";
180 enable-method = "psci";
181 next-level-cache = <&cluster2_l2>;
186 compatible = "arm,cortex-a57", "arm,armv8";
188 enable-method = "psci";
189 next-level-cache = <&cluster3_l2>;
194 compatible = "arm,cortex-a57", "arm,armv8";
196 enable-method = "psci";
197 next-level-cache = <&cluster3_l2>;
202 compatible = "arm,cortex-a57", "arm,armv8";
204 enable-method = "psci";
205 next-level-cache = <&cluster3_l2>;
210 compatible = "arm,cortex-a57", "arm,armv8";
212 enable-method = "psci";
213 next-level-cache = <&cluster3_l2>;
216 cluster0_l2: l2-cache0 {
217 compatible = "cache";
220 cluster1_l2: l2-cache1 {
221 compatible = "cache";
224 cluster2_l2: l2-cache2 {
225 compatible = "cache";
228 cluster3_l2: l2-cache3 {
229 compatible = "cache";
233 gic: interrupt-controller@4d000000 {
234 compatible = "arm,gic-v3";
235 #interrupt-cells = <3>;
236 #address-cells = <2>;
239 interrupt-controller;
240 #redistributor-regions = <1>;
241 redistributor-stride = <0x0 0x30000>;
242 reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
243 <0x0 0x4d100000 0 0x300000>, /* GICR */
244 <0x0 0xfe000000 0 0x10000>, /* GICC */
245 <0x0 0xfe010000 0 0x10000>, /* GICH */
246 <0x0 0xfe020000 0 0x10000>; /* GICV */
247 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
249 its_dsa: interrupt-controller@c6000000 {
250 compatible = "arm,gic-v3-its";
253 reg = <0x0 0xc6000000 0x0 0x40000>;
258 compatible = "arm,armv8-timer";
259 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
260 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
261 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
262 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
266 compatible = "arm,cortex-a57-pmu";
267 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
270 mbigen_pcie@a0080000 {
271 compatible = "hisilicon,mbigen-v2";
272 reg = <0x0 0xa0080000 0x0 0x10000>;
274 mbigen_usb: intc_usb {
275 msi-parent = <&its_dsa 0x40080>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
283 compatible = "simple-bus";
284 #address-cells = <2>;
288 usb_ohci: ohci@a7030000 {
289 compatible = "generic-ohci";
290 reg = <0x0 0xa7030000 0x0 0x10000>;
291 interrupt-parent = <&mbigen_usb>;
297 usb_ehci: ehci@a7020000 {
298 compatible = "generic-ehci";
299 reg = <0x0 0xa7020000 0x0 0x10000>;
300 interrupt-parent = <&mbigen_usb>;