arch/arm64/boot/dts/renesas/r8a7796.dtsi

   1 /*
   2  * Device Tree Source for the r8a7796 SoC
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13
  14 / {
  15         compatible = "renesas,r8a7796";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         psci {
  20                 compatible = "arm,psci-0.2";
  21                 method = "smc";
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 /* 1 core only at this point */
  29                 a57_0: cpu@0 {
  30                         compatible = "arm,cortex-a57", "arm,armv8";
  31                         reg = <0x0>;
  32                         device_type = "cpu";
  33                         next-level-cache = <&L2_CA57>;
  34                         enable-method = "psci";
  35                 };
  36
  37                 L2_CA57: cache-controller@0 {
  38                         compatible = "cache";
  39                         reg = <0>;
  40                         cache-unified;
  41                         cache-level = <2>;
  42                 };
  43         };
  44
  45         extal_clk: extal {
  46                 compatible = "fixed-clock";
  47                 #clock-cells = <0>;
  48                 /* This value must be overridden by the board */
  49                 clock-frequency = <0>;
  50         };
  51
  52         extalr_clk: extalr {
  53                 compatible = "fixed-clock";
  54                 #clock-cells = <0>;
  55                 /* This value must be overridden by the board */
  56                 clock-frequency = <0>;
  57         };
  58
  59         /* External SCIF clock - to be overridden by boards that provide it */
  60         scif_clk: scif {
  61                 compatible = "fixed-clock";
  62                 #clock-cells = <0>;
  63                 clock-frequency = <0>;
  64         };
  65
  66         soc {
  67                 compatible = "simple-bus";
  68                 interrupt-parent = <&gic>;
  69                 #address-cells = <2>;
  70                 #size-cells = <2>;
  71                 ranges;
  72
  73                 gic: interrupt-controller@f1010000 {
  74                         compatible = "arm,gic-400";
  75                         #interrupt-cells = <3>;
  76                         #address-cells = <0>;
  77                         interrupt-controller;
  78                         reg = <0x0 0xf1010000 0 0x1000>,
  79                               <0x0 0xf1020000 0 0x20000>,
  80                               <0x0 0xf1040000 0 0x20000>,
  81                               <0x0 0xf1060000 0 0x20000>;
  82                         interrupts = <GIC_PPI 9
  83                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  84                 };
  85
  86                 timer {
  87                         compatible = "arm,armv8-timer";
  88                         interrupts = <GIC_PPI 13
  89                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  90                                      <GIC_PPI 14
  91                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  92                                      <GIC_PPI 11
  93                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  94                                      <GIC_PPI 10
  95                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  96                 };
  97
  98                 cpg: clock-controller@e6150000 {
  99                         compatible = "renesas,r8a7796-cpg-mssr";
 100                         reg = <0 0xe6150000 0 0x1000>;
 101                         clocks = <&extal_clk>, <&extalr_clk>;
 102                         clock-names = "extal", "extalr";
 103                         #clock-cells = <2>;
 104                         #power-domain-cells = <0>;
 105                 };
 106
 107                 scif2: serial@e6e88000 {
 108                         compatible = "renesas,scif-r8a7796",
 109                                      "renesas,rcar-gen3-scif", "renesas,scif";
 110                         reg = <0 0xe6e88000 0 64>;
 111                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 112                         clocks = <&cpg CPG_MOD 310>,
 113                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 114                                  <&scif_clk>;
 115                         clock-names = "fck", "brg_int", "scif_clk";
 116                         power-domains = <&cpg>;
 117                         status = "disabled";
 118                 };
 119         };
 120 };