2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/thread_info.h>
32 #include <asm/unistd.h>
35 * Context tracking subsystem. Used to instrument transitions
36 * between user and kernel mode.
38 .macro ct_user_exit, syscall = 0
39 #ifdef CONFIG_CONTEXT_TRACKING
40 bl context_tracking_user_exit
43 * Save/restore needed during syscalls. Restore syscall arguments from
44 * the values already saved on stack during kernel_entry.
47 ldp x2, x3, [sp, #S_X2]
48 ldp x4, x5, [sp, #S_X4]
49 ldp x6, x7, [sp, #S_X6]
55 #ifdef CONFIG_CONTEXT_TRACKING
56 bl context_tracking_user_enter
69 .macro kernel_entry, el, regsize = 64
70 sub sp, sp, #S_FRAME_SIZE
72 mov w0, w0 // zero upper 32 bits of x0
74 stp x0, x1, [sp, #16 * 0]
75 stp x2, x3, [sp, #16 * 1]
76 stp x4, x5, [sp, #16 * 2]
77 stp x6, x7, [sp, #16 * 3]
78 stp x8, x9, [sp, #16 * 4]
79 stp x10, x11, [sp, #16 * 5]
80 stp x12, x13, [sp, #16 * 6]
81 stp x14, x15, [sp, #16 * 7]
82 stp x16, x17, [sp, #16 * 8]
83 stp x18, x19, [sp, #16 * 9]
84 stp x20, x21, [sp, #16 * 10]
85 stp x22, x23, [sp, #16 * 11]
86 stp x24, x25, [sp, #16 * 12]
87 stp x26, x27, [sp, #16 * 13]
88 stp x28, x29, [sp, #16 * 14]
93 and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear,
94 ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
95 disable_step_tsk x19, x20 // exceptions when scheduling.
97 add x21, sp, #S_FRAME_SIZE
101 stp lr, x21, [sp, #S_LR]
102 stp x22, x23, [sp, #S_PC]
105 * Set syscallno to -1 by default (overridden later if real syscall).
109 str x21, [sp, #S_SYSCALLNO]
113 * Set sp_el0 to current thread_info.
120 * Registers that may be useful after this macro is invoked:
124 * x23 - aborted PSTATE
128 .macro kernel_exit, el
129 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
132 ldr x23, [sp, #S_SP] // load return stack pointer
134 #ifdef CONFIG_ARM64_ERRATUM_845719
135 alternative_if_not ARM64_WORKAROUND_845719
138 #ifdef CONFIG_PID_IN_CONTEXTIDR
143 #ifdef CONFIG_PID_IN_CONTEXTIDR
144 mrs x29, contextidr_el1
145 msr contextidr_el1, x29
147 msr contextidr_el1, xzr
153 msr elr_el1, x21 // set up the return data
155 ldp x0, x1, [sp, #16 * 0]
156 ldp x2, x3, [sp, #16 * 1]
157 ldp x4, x5, [sp, #16 * 2]
158 ldp x6, x7, [sp, #16 * 3]
159 ldp x8, x9, [sp, #16 * 4]
160 ldp x10, x11, [sp, #16 * 5]
161 ldp x12, x13, [sp, #16 * 6]
162 ldp x14, x15, [sp, #16 * 7]
163 ldp x16, x17, [sp, #16 * 8]
164 ldp x18, x19, [sp, #16 * 9]
165 ldp x20, x21, [sp, #16 * 10]
166 ldp x22, x23, [sp, #16 * 11]
167 ldp x24, x25, [sp, #16 * 12]
168 ldp x26, x27, [sp, #16 * 13]
169 ldp x28, x29, [sp, #16 * 14]
171 add sp, sp, #S_FRAME_SIZE // restore sp
172 eret // return to kernel
175 .macro get_thread_info, rd
179 .macro irq_stack_entry, dummy_lr
180 mov x19, sp // preserve the original sp
187 * Check the lowest address on irq_stack for the irq_count value,
188 * incremented by do_softirq_own_stack if we have re-enabled irqs
189 * while on the irq_stack.
192 cbnz x26, 9998f // recursive use?
194 /* switch to the irq stack */
195 mov x26, #IRQ_STACK_START_SP
199 /* Add a dummy stack frame */
200 stp x29, \dummy_lr, [sp, #-16]! // dummy stack frame
202 stp x19, xzr, [sp, #-16]!
208 * x19 should be preserved between irq_stack_entry and
211 .macro irq_stack_exit
216 * These are the registers used in the syscall handler, and allow us to
217 * have in theory up to 7 arguments to a function - x0 to x6.
219 * x7 is reserved for the system call number in 32-bit mode.
221 sc_nr .req x25 // number of system calls
222 scno .req x26 // syscall number
223 stbl .req x27 // syscall table pointer
224 tsk .req x28 // current thread_info
227 * Interrupt handling.
230 ldr_l x1, handle_arch_irq
245 ventry el1_sync_invalid // Synchronous EL1t
246 ventry el1_irq_invalid // IRQ EL1t
247 ventry el1_fiq_invalid // FIQ EL1t
248 ventry el1_error_invalid // Error EL1t
250 ventry el1_sync // Synchronous EL1h
251 ventry el1_irq // IRQ EL1h
252 ventry el1_fiq_invalid // FIQ EL1h
253 ventry el1_error_invalid // Error EL1h
255 ventry el0_sync // Synchronous 64-bit EL0
256 ventry el0_irq // IRQ 64-bit EL0
257 ventry el0_fiq_invalid // FIQ 64-bit EL0
258 ventry el0_error_invalid // Error 64-bit EL0
261 ventry el0_sync_compat // Synchronous 32-bit EL0
262 ventry el0_irq_compat // IRQ 32-bit EL0
263 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
264 ventry el0_error_invalid_compat // Error 32-bit EL0
266 ventry el0_sync_invalid // Synchronous 32-bit EL0
267 ventry el0_irq_invalid // IRQ 32-bit EL0
268 ventry el0_fiq_invalid // FIQ 32-bit EL0
269 ventry el0_error_invalid // Error 32-bit EL0
274 * Invalid mode handlers
276 .macro inv_entry, el, reason, regsize = 64
277 kernel_entry el, \regsize
285 inv_entry 0, BAD_SYNC
286 ENDPROC(el0_sync_invalid)
290 ENDPROC(el0_irq_invalid)
294 ENDPROC(el0_fiq_invalid)
297 inv_entry 0, BAD_ERROR
298 ENDPROC(el0_error_invalid)
301 el0_fiq_invalid_compat:
302 inv_entry 0, BAD_FIQ, 32
303 ENDPROC(el0_fiq_invalid_compat)
305 el0_error_invalid_compat:
306 inv_entry 0, BAD_ERROR, 32
307 ENDPROC(el0_error_invalid_compat)
311 inv_entry 1, BAD_SYNC
312 ENDPROC(el1_sync_invalid)
316 ENDPROC(el1_irq_invalid)
320 ENDPROC(el1_fiq_invalid)
323 inv_entry 1, BAD_ERROR
324 ENDPROC(el1_error_invalid)
332 mrs x1, esr_el1 // read the syndrome register
333 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
334 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
336 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
338 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
340 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
342 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
344 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
349 * Data abort handling
353 // re-enable interrupts if they were enabled in the aborted context
354 tbnz x23, #7, 1f // PSR_I_BIT
357 mov x2, sp // struct pt_regs
360 // disable interrupts before pulling preserved data off the stack
365 * Stack or PC alignment exception handling
373 * Undefined instruction
380 * Debug exception handling
382 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
383 cinc x24, x24, eq // set bit '0'
384 tbz x24, #0, el1_inv // EL1 only
386 mov x2, sp // struct pt_regs
387 bl do_debug_exception
390 // TODO: add support for undefined instructions in kernel mode
402 #ifdef CONFIG_TRACE_IRQFLAGS
403 bl trace_hardirqs_off
408 #ifdef CONFIG_PREEMPT
410 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
411 cbnz w24, 1f // preempt count != 0
412 ldr x0, [tsk, #TI_FLAGS] // get flags
413 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
417 #ifdef CONFIG_TRACE_IRQFLAGS
423 #ifdef CONFIG_PREEMPT
426 1: bl preempt_schedule_irq // irq en/disable is done inside
427 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
428 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
438 mrs x25, esr_el1 // read the syndrome register
439 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
440 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
442 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
444 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
446 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
448 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
450 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
452 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
454 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
456 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
458 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
466 mrs x25, esr_el1 // read the syndrome register
467 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
468 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
470 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
472 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
474 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
476 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
478 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
480 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
482 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
484 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
486 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
488 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
490 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
492 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
497 * AArch32 syscall handling
499 adrp stbl, compat_sys_call_table // load compat syscall table pointer
500 uxtw scno, w7 // syscall number in w7 (r7)
501 mov sc_nr, #__NR_compat_syscalls
512 * Data abort handling
515 // enable interrupts before calling the main handler
518 bic x0, x26, #(0xff << 56)
525 * Instruction abort handling
528 // enable interrupts before calling the main handler
532 orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts
538 * Floating Point or Advanced SIMD access
548 * Floating Point or Advanced SIMD exception
558 * Stack or PC alignment exception handling
561 // enable interrupts before calling the main handler
571 * Undefined instruction
573 // enable interrupts before calling the main handler
581 * Debug exception handling
583 tbnz x24, #0, el0_inv // EL0 only
587 bl do_debug_exception
606 #ifdef CONFIG_TRACE_IRQFLAGS
607 bl trace_hardirqs_off
613 #ifdef CONFIG_TRACE_IRQFLAGS
620 * Register switch for AArch64. The callee-saved registers need to be saved
621 * and restored. On entry:
622 * x0 = previous task_struct (must be preserved across the switch)
623 * x1 = next task_struct
624 * Previous and next are guaranteed not to be the same.
628 mov x10, #THREAD_CPU_CONTEXT
631 stp x19, x20, [x8], #16 // store callee-saved registers
632 stp x21, x22, [x8], #16
633 stp x23, x24, [x8], #16
634 stp x25, x26, [x8], #16
635 stp x27, x28, [x8], #16
636 stp x29, x9, [x8], #16
639 ldp x19, x20, [x8], #16 // restore callee-saved registers
640 ldp x21, x22, [x8], #16
641 ldp x23, x24, [x8], #16
642 ldp x25, x26, [x8], #16
643 ldp x27, x28, [x8], #16
644 ldp x29, x9, [x8], #16
647 and x9, x9, #~(THREAD_SIZE - 1)
650 ENDPROC(cpu_switch_to)
653 * This is the fast syscall return path. We do as little as possible here,
654 * and this includes saving x0 back into the kernel stack.
657 disable_irq // disable interrupts
658 str x0, [sp, #S_X0] // returned x0
659 ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing
660 and x2, x1, #_TIF_SYSCALL_WORK
661 cbnz x2, ret_fast_syscall_trace
662 and x2, x1, #_TIF_WORK_MASK
663 cbnz x2, work_pending
664 enable_step_tsk x1, x2
666 ret_fast_syscall_trace:
667 enable_irq // enable interrupts
668 b __sys_trace_return_skipped // we already saved x0
671 * Ok, we need to do extra processing, enter the slow path.
674 tbnz x1, #TIF_NEED_RESCHED, work_resched
675 /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */
676 ldr x2, [sp, #S_PSTATE]
678 tst x2, #PSR_MODE_MASK // user mode regs?
679 b.ne no_work_pending // returning to kernel
680 enable_irq // enable interrupts for do_notify_resume()
684 #ifdef CONFIG_TRACE_IRQFLAGS
685 bl trace_hardirqs_off // the IRQs are off here, inform the tracing code
690 * "slow" syscall return path.
693 disable_irq // disable interrupts
694 ldr x1, [tsk, #TI_FLAGS]
695 and x2, x1, #_TIF_WORK_MASK
696 cbnz x2, work_pending
697 enable_step_tsk x1, x2
703 * This is how we return from a fork.
707 cbz x19, 1f // not a kernel thread
710 1: get_thread_info tsk
712 ENDPROC(ret_from_fork)
719 adrp stbl, sys_call_table // load syscall table pointer
720 uxtw scno, w8 // syscall number in w8
721 mov sc_nr, #__NR_syscalls
722 el0_svc_naked: // compat entry point
723 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
727 ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks
728 tst x16, #_TIF_SYSCALL_WORK
730 cmp scno, sc_nr // check upper syscall limit
732 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
733 blr x16 // call sys_* routine
742 * This is the really slow path. We're going to be doing context
743 * switches, and waiting for our parent to respond.
746 mov w0, #-1 // set default errno for
747 cmp scno, x0 // user-issued syscall(-1)
752 bl syscall_trace_enter
753 cmp w0, #-1 // skip the syscall?
754 b.eq __sys_trace_return_skipped
755 uxtw scno, w0 // syscall number (possibly new)
756 mov x1, sp // pointer to regs
757 cmp scno, sc_nr // check upper syscall limit
759 ldp x0, x1, [sp] // restore the syscall args
760 ldp x2, x3, [sp, #S_X2]
761 ldp x4, x5, [sp, #S_X4]
762 ldp x6, x7, [sp, #S_X6]
763 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
764 blr x16 // call sys_* routine
767 str x0, [sp, #S_X0] // save returned x0
768 __sys_trace_return_skipped:
770 bl syscall_trace_exit
779 * Special system call wrappers.
781 ENTRY(sys_rt_sigreturn_wrapper)
784 ENDPROC(sys_rt_sigreturn_wrapper)