arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/platform_data/dma-dw.h>
  11 #include <linux/fb.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/slab.h>
  16 #include <linux/gpio.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/usb/atmel_usba_udc.h>
  19
  20 #include <mach/atmel-mci.h>
  21 #include <linux/atmel-mci.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/irq.h>
  25
  26 #include <mach/at32ap700x.h>
  27 #include <mach/board.h>
  28 #include <mach/hmatrix.h>
  29 #include <mach/portmux.h>
  30 #include <mach/sram.h>
  31
  32 #include <sound/atmel-abdac.h>
  33 #include <sound/atmel-ac97c.h>
  34
  35 #include <video/atmel_lcdc.h>
  36
  37 #include "clock.h"
  38 #include "pio.h"
  39 #include "pm.h"
  40
  41
  42 #define PBMEM(base)                                     \
  43         {                                               \
  44                 .start          = base,                 \
  45                 .end            = base + 0x3ff,         \
  46                 .flags          = IORESOURCE_MEM,       \
  47         }
  48 #define IRQ(num)                                        \
  49         {                                               \
  50                 .start          = num,                  \
  51                 .end            = num,                  \
  52                 .flags          = IORESOURCE_IRQ,       \
  53         }
  54 #define NAMED_IRQ(num, _name)                           \
  55         {                                               \
  56                 .start          = num,                  \
  57                 .end            = num,                  \
  58                 .name           = _name,                \
  59                 .flags          = IORESOURCE_IRQ,       \
  60         }
  61
  62 /* REVISIT these assume *every* device supports DMA, but several
  63  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  64  */
  65 #define DEFINE_DEV(_name, _id)                                  \
  66 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32);            \
  67 static struct platform_device _name##_id##_device = {           \
  68         .name           = #_name,                               \
  69         .id             = _id,                                  \
  70         .dev            = {                                     \
  71                 .dma_mask = &_name##_id##_dma_mask,             \
  72                 .coherent_dma_mask = DMA_BIT_MASK(32),          \
  73         },                                                      \
  74         .resource       = _name##_id##_resource,                \
  75         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  76 }
  77 #define DEFINE_DEV_DATA(_name, _id)                             \
  78 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32);            \
  79 static struct platform_device _name##_id##_device = {           \
  80         .name           = #_name,                               \
  81         .id             = _id,                                  \
  82         .dev            = {                                     \
  83                 .dma_mask = &_name##_id##_dma_mask,             \
  84                 .platform_data  = &_name##_id##_data,           \
  85                 .coherent_dma_mask = DMA_BIT_MASK(32),          \
  86         },                                                      \
  87         .resource       = _name##_id##_resource,                \
  88         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  89 }
  90
  91 #define select_peripheral(port, pin_mask, periph, flags)        \
  92         at32_select_periph(GPIO_##port##_BASE, pin_mask,        \
  93                            GPIO_##periph, flags)
  94
  95 #define DEV_CLK(_name, devname, bus, _index)                    \
  96 static struct clk devname##_##_name = {                         \
  97         .name           = #_name,                               \
  98         .dev            = &devname##_device.dev,                \
  99         .parent         = &bus##_clk,                           \
 100         .mode           = bus##_clk_mode,                       \
 101         .get_rate       = bus##_clk_get_rate,                   \
 102         .index          = _index,                               \
 103 }
 104
 105 static DEFINE_SPINLOCK(pm_lock);
 106
 107 static struct clk osc0;
 108 static struct clk osc1;
 109
 110 static unsigned long osc_get_rate(struct clk *clk)
 111 {
 112         return at32_board_osc_rates[clk->index];
 113 }
 114
 115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 116 {
 117         unsigned long div, mul, rate;
 118
 119         div = PM_BFEXT(PLLDIV, control) + 1;
 120         mul = PM_BFEXT(PLLMUL, control) + 1;
 121
 122         rate = clk->parent->get_rate(clk->parent);
 123         rate = (rate + div / 2) / div;
 124         rate *= mul;
 125
 126         return rate;
 127 }
 128
 129 static long pll_set_rate(struct clk *clk, unsigned long rate,
 130                          u32 *pll_ctrl)
 131 {
 132         unsigned long mul;
 133         unsigned long mul_best_fit = 0;
 134         unsigned long div;
 135         unsigned long div_min;
 136         unsigned long div_max;
 137         unsigned long div_best_fit = 0;
 138         unsigned long base;
 139         unsigned long pll_in;
 140         unsigned long actual = 0;
 141         unsigned long rate_error;
 142         unsigned long rate_error_prev = ~0UL;
 143         u32 ctrl;
 144
 145         /* Rate must be between 80 MHz and 200 Mhz. */
 146         if (rate < 80000000UL || rate > 200000000UL)
 147                 return -EINVAL;
 148
 149         ctrl = PM_BF(PLLOPT, 4);
 150         base = clk->parent->get_rate(clk->parent);
 151
 152         /* PLL input frequency must be between 6 MHz and 32 MHz. */
 153         div_min = DIV_ROUND_UP(base, 32000000UL);
 154         div_max = base / 6000000UL;
 155
 156         if (div_max < div_min)
 157                 return -EINVAL;
 158
 159         for (div = div_min; div <= div_max; div++) {
 160                 pll_in = (base + div / 2) / div;
 161                 mul = (rate + pll_in / 2) / pll_in;
 162
 163                 if (mul == 0)
 164                         continue;
 165
 166                 actual = pll_in * mul;
 167                 rate_error = abs(actual - rate);
 168
 169                 if (rate_error < rate_error_prev) {
 170                         mul_best_fit = mul;
 171                         div_best_fit = div;
 172                         rate_error_prev = rate_error;
 173                 }
 174
 175                 if (rate_error == 0)
 176                         break;
 177         }
 178
 179         if (div_best_fit == 0)
 180                 return -EINVAL;
 181
 182         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 183         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 184         ctrl |= PM_BF(PLLCOUNT, 16);
 185
 186         if (clk->parent == &osc1)
 187                 ctrl |= PM_BIT(PLLOSC);
 188
 189         *pll_ctrl = ctrl;
 190
 191         return actual;
 192 }
 193
 194 static unsigned long pll0_get_rate(struct clk *clk)
 195 {
 196         u32 control;
 197
 198         control = pm_readl(PLL0);
 199
 200         return pll_get_rate(clk, control);
 201 }
 202
 203 static void pll1_mode(struct clk *clk, int enabled)
 204 {
 205         unsigned long timeout;
 206         u32 status;
 207         u32 ctrl;
 208
 209         ctrl = pm_readl(PLL1);
 210
 211         if (enabled) {
 212                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 213                         pr_debug("clk %s: failed to enable, rate not set\n",
 214                                         clk->name);
 215                         return;
 216                 }
 217
 218                 ctrl |= PM_BIT(PLLEN);
 219                 pm_writel(PLL1, ctrl);
 220
 221                 /* Wait for PLL lock. */
 222                 for (timeout = 10000; timeout; timeout--) {
 223                         status = pm_readl(ISR);
 224                         if (status & PM_BIT(LOCK1))
 225                                 break;
 226                         udelay(10);
 227                 }
 228
 229                 if (!(status & PM_BIT(LOCK1)))
 230                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 231                                         clk->name);
 232         } else {
 233                 ctrl &= ~PM_BIT(PLLEN);
 234                 pm_writel(PLL1, ctrl);
 235         }
 236 }
 237
 238 static unsigned long pll1_get_rate(struct clk *clk)
 239 {
 240         u32 control;
 241
 242         control = pm_readl(PLL1);
 243
 244         return pll_get_rate(clk, control);
 245 }
 246
 247 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 248 {
 249         u32 ctrl = 0;
 250         unsigned long actual_rate;
 251
 252         actual_rate = pll_set_rate(clk, rate, &ctrl);
 253
 254         if (apply) {
 255                 if (actual_rate != rate)
 256                         return -EINVAL;
 257                 if (clk->users > 0)
 258                         return -EBUSY;
 259                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 260                                 clk->name, rate, actual_rate);
 261                 pm_writel(PLL1, ctrl);
 262         }
 263
 264         return actual_rate;
 265 }
 266
 267 static int pll1_set_parent(struct clk *clk, struct clk *parent)
 268 {
 269         u32 ctrl;
 270
 271         if (clk->users > 0)
 272                 return -EBUSY;
 273
 274         ctrl = pm_readl(PLL1);
 275         WARN_ON(ctrl & PM_BIT(PLLEN));
 276
 277         if (parent == &osc0)
 278                 ctrl &= ~PM_BIT(PLLOSC);
 279         else if (parent == &osc1)
 280                 ctrl |= PM_BIT(PLLOSC);
 281         else
 282                 return -EINVAL;
 283
 284         pm_writel(PLL1, ctrl);
 285         clk->parent = parent;
 286
 287         return 0;
 288 }
 289
 290 /*
 291  * The AT32AP7000 has five primary clock sources: One 32kHz
 292  * oscillator, two crystal oscillators and two PLLs.
 293  */
 294 static struct clk osc32k = {
 295         .name           = "osc32k",
 296         .get_rate       = osc_get_rate,
 297         .users          = 1,
 298         .index          = 0,
 299 };
 300 static struct clk osc0 = {
 301         .name           = "osc0",
 302         .get_rate       = osc_get_rate,
 303         .users          = 1,
 304         .index          = 1,
 305 };
 306 static struct clk osc1 = {
 307         .name           = "osc1",
 308         .get_rate       = osc_get_rate,
 309         .index          = 2,
 310 };
 311 static struct clk pll0 = {
 312         .name           = "pll0",
 313         .get_rate       = pll0_get_rate,
 314         .parent         = &osc0,
 315 };
 316 static struct clk pll1 = {
 317         .name           = "pll1",
 318         .mode           = pll1_mode,
 319         .get_rate       = pll1_get_rate,
 320         .set_rate       = pll1_set_rate,
 321         .set_parent     = pll1_set_parent,
 322         .parent         = &osc0,
 323 };
 324
 325 /*
 326  * The main clock can be either osc0 or pll0.  The boot loader may
 327  * have chosen one for us, so we don't really know which one until we
 328  * have a look at the SM.
 329  */
 330 static struct clk *main_clock;
 331
 332 /*
 333  * Synchronous clocks are generated from the main clock. The clocks
 334  * must satisfy the constraint
 335  *   fCPU >= fHSB >= fPB
 336  * i.e. each clock must not be faster than its parent.
 337  */
 338 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 339 {
 340         return main_clock->get_rate(main_clock) >> shift;
 341 };
 342
 343 static void cpu_clk_mode(struct clk *clk, int enabled)
 344 {
 345         unsigned long flags;
 346         u32 mask;
 347
 348         spin_lock_irqsave(&pm_lock, flags);
 349         mask = pm_readl(CPU_MASK);
 350         if (enabled)
 351                 mask |= 1 << clk->index;
 352         else
 353                 mask &= ~(1 << clk->index);
 354         pm_writel(CPU_MASK, mask);
 355         spin_unlock_irqrestore(&pm_lock, flags);
 356 }
 357
 358 static unsigned long cpu_clk_get_rate(struct clk *clk)
 359 {
 360         unsigned long cksel, shift = 0;
 361
 362         cksel = pm_readl(CKSEL);
 363         if (cksel & PM_BIT(CPUDIV))
 364                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 365
 366         return bus_clk_get_rate(clk, shift);
 367 }
 368
 369 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 370 {
 371         u32 control;
 372         unsigned long parent_rate, child_div, actual_rate, div;
 373
 374         parent_rate = clk->parent->get_rate(clk->parent);
 375         control = pm_readl(CKSEL);
 376
 377         if (control & PM_BIT(HSBDIV))
 378                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 379         else
 380                 child_div = 1;
 381
 382         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 383                 actual_rate = parent_rate;
 384                 control &= ~PM_BIT(CPUDIV);
 385         } else {
 386                 unsigned int cpusel;
 387                 div = (parent_rate + rate / 2) / rate;
 388                 if (div > child_div)
 389                         div = child_div;
 390                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 391                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 392                 actual_rate = parent_rate / (1 << (cpusel + 1));
 393         }
 394
 395         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 396                         clk->name, rate, actual_rate);
 397
 398         if (apply)
 399                 pm_writel(CKSEL, control);
 400
 401         return actual_rate;
 402 }
 403
 404 static void hsb_clk_mode(struct clk *clk, int enabled)
 405 {
 406         unsigned long flags;
 407         u32 mask;
 408
 409         spin_lock_irqsave(&pm_lock, flags);
 410         mask = pm_readl(HSB_MASK);
 411         if (enabled)
 412                 mask |= 1 << clk->index;
 413         else
 414                 mask &= ~(1 << clk->index);
 415         pm_writel(HSB_MASK, mask);
 416         spin_unlock_irqrestore(&pm_lock, flags);
 417 }
 418
 419 static unsigned long hsb_clk_get_rate(struct clk *clk)
 420 {
 421         unsigned long cksel, shift = 0;
 422
 423         cksel = pm_readl(CKSEL);
 424         if (cksel & PM_BIT(HSBDIV))
 425                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 426
 427         return bus_clk_get_rate(clk, shift);
 428 }
 429
 430 void pba_clk_mode(struct clk *clk, int enabled)
 431 {
 432         unsigned long flags;
 433         u32 mask;
 434
 435         spin_lock_irqsave(&pm_lock, flags);
 436         mask = pm_readl(PBA_MASK);
 437         if (enabled)
 438                 mask |= 1 << clk->index;
 439         else
 440                 mask &= ~(1 << clk->index);
 441         pm_writel(PBA_MASK, mask);
 442         spin_unlock_irqrestore(&pm_lock, flags);
 443 }
 444
 445 unsigned long pba_clk_get_rate(struct clk *clk)
 446 {
 447         unsigned long cksel, shift = 0;
 448
 449         cksel = pm_readl(CKSEL);
 450         if (cksel & PM_BIT(PBADIV))
 451                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 452
 453         return bus_clk_get_rate(clk, shift);
 454 }
 455
 456 static void pbb_clk_mode(struct clk *clk, int enabled)
 457 {
 458         unsigned long flags;
 459         u32 mask;
 460
 461         spin_lock_irqsave(&pm_lock, flags);
 462         mask = pm_readl(PBB_MASK);
 463         if (enabled)
 464                 mask |= 1 << clk->index;
 465         else
 466                 mask &= ~(1 << clk->index);
 467         pm_writel(PBB_MASK, mask);
 468         spin_unlock_irqrestore(&pm_lock, flags);
 469 }
 470
 471 static unsigned long pbb_clk_get_rate(struct clk *clk)
 472 {
 473         unsigned long cksel, shift = 0;
 474
 475         cksel = pm_readl(CKSEL);
 476         if (cksel & PM_BIT(PBBDIV))
 477                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 478
 479         return bus_clk_get_rate(clk, shift);
 480 }
 481
 482 static struct clk cpu_clk = {
 483         .name           = "cpu",
 484         .get_rate       = cpu_clk_get_rate,
 485         .set_rate       = cpu_clk_set_rate,
 486         .users          = 1,
 487 };
 488 static struct clk hsb_clk = {
 489         .name           = "hsb",
 490         .parent         = &cpu_clk,
 491         .get_rate       = hsb_clk_get_rate,
 492 };
 493 static struct clk pba_clk = {
 494         .name           = "pba",
 495         .parent         = &hsb_clk,
 496         .mode           = hsb_clk_mode,
 497         .get_rate       = pba_clk_get_rate,
 498         .index          = 1,
 499 };
 500 static struct clk pbb_clk = {
 501         .name           = "pbb",
 502         .parent         = &hsb_clk,
 503         .mode           = hsb_clk_mode,
 504         .get_rate       = pbb_clk_get_rate,
 505         .users          = 1,
 506         .index          = 2,
 507 };
 508
 509 /* --------------------------------------------------------------------
 510  *  Generic Clock operations
 511  * -------------------------------------------------------------------- */
 512
 513 static void genclk_mode(struct clk *clk, int enabled)
 514 {
 515         u32 control;
 516
 517         control = pm_readl(GCCTRL(clk->index));
 518         if (enabled)
 519                 control |= PM_BIT(CEN);
 520         else
 521                 control &= ~PM_BIT(CEN);
 522         pm_writel(GCCTRL(clk->index), control);
 523 }
 524
 525 static unsigned long genclk_get_rate(struct clk *clk)
 526 {
 527         u32 control;
 528         unsigned long div = 1;
 529
 530         control = pm_readl(GCCTRL(clk->index));
 531         if (control & PM_BIT(DIVEN))
 532                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 533
 534         return clk->parent->get_rate(clk->parent) / div;
 535 }
 536
 537 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 538 {
 539         u32 control;
 540         unsigned long parent_rate, actual_rate, div;
 541
 542         parent_rate = clk->parent->get_rate(clk->parent);
 543         control = pm_readl(GCCTRL(clk->index));
 544
 545         if (rate > 3 * parent_rate / 4) {
 546                 actual_rate = parent_rate;
 547                 control &= ~PM_BIT(DIVEN);
 548         } else {
 549                 div = (parent_rate + rate) / (2 * rate) - 1;
 550                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 551                 actual_rate = parent_rate / (2 * (div + 1));
 552         }
 553
 554         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 555                 clk->name, rate, actual_rate);
 556
 557         if (apply)
 558                 pm_writel(GCCTRL(clk->index), control);
 559
 560         return actual_rate;
 561 }
 562
 563 int genclk_set_parent(struct clk *clk, struct clk *parent)
 564 {
 565         u32 control;
 566
 567         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 568                 clk->name, parent->name, clk->parent->name);
 569
 570         control = pm_readl(GCCTRL(clk->index));
 571
 572         if (parent == &osc1 || parent == &pll1)
 573                 control |= PM_BIT(OSCSEL);
 574         else if (parent == &osc0 || parent == &pll0)
 575                 control &= ~PM_BIT(OSCSEL);
 576         else
 577                 return -EINVAL;
 578
 579         if (parent == &pll0 || parent == &pll1)
 580                 control |= PM_BIT(PLLSEL);
 581         else
 582                 control &= ~PM_BIT(PLLSEL);
 583
 584         pm_writel(GCCTRL(clk->index), control);
 585         clk->parent = parent;
 586
 587         return 0;
 588 }
 589
 590 static void __init genclk_init_parent(struct clk *clk)
 591 {
 592         u32 control;
 593         struct clk *parent;
 594
 595         BUG_ON(clk->index > 7);
 596
 597         control = pm_readl(GCCTRL(clk->index));
 598         if (control & PM_BIT(OSCSEL))
 599                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 600         else
 601                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 602
 603         clk->parent = parent;
 604 }
 605
 606 static struct dw_dma_platform_data dw_dmac0_data = {
 607         .nr_channels    = 3,
 608         .block_size     = 4095U,
 609         .nr_masters     = 2,
 610         .data_width     = { 2, 2, 0, 0 },
 611 };
 612
 613 static struct resource dw_dmac0_resource[] = {
 614         PBMEM(0xff200000),
 615         IRQ(2),
 616 };
 617 DEFINE_DEV_DATA(dw_dmac, 0);
 618 DEV_CLK(hclk, dw_dmac0, hsb, 10);
 619
 620 /* --------------------------------------------------------------------
 621  *  System peripherals
 622  * -------------------------------------------------------------------- */
 623 static struct resource at32_pm0_resource[] = {
 624         {
 625                 .start  = 0xfff00000,
 626                 .end    = 0xfff0007f,
 627                 .flags  = IORESOURCE_MEM,
 628         },
 629         IRQ(20),
 630 };
 631
 632 static struct resource at32ap700x_rtc0_resource[] = {
 633         {
 634                 .start  = 0xfff00080,
 635                 .end    = 0xfff000af,
 636                 .flags  = IORESOURCE_MEM,
 637         },
 638         IRQ(21),
 639 };
 640
 641 static struct resource at32_wdt0_resource[] = {
 642         {
 643                 .start  = 0xfff000b0,
 644                 .end    = 0xfff000cf,
 645                 .flags  = IORESOURCE_MEM,
 646         },
 647 };
 648
 649 static struct resource at32_eic0_resource[] = {
 650         {
 651                 .start  = 0xfff00100,
 652                 .end    = 0xfff0013f,
 653                 .flags  = IORESOURCE_MEM,
 654         },
 655         IRQ(19),
 656 };
 657
 658 DEFINE_DEV(at32_pm, 0);
 659 DEFINE_DEV(at32ap700x_rtc, 0);
 660 DEFINE_DEV(at32_wdt, 0);
 661 DEFINE_DEV(at32_eic, 0);
 662
 663 /*
 664  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 665  * is always running.
 666  */
 667 static struct clk at32_pm_pclk = {
 668         .name           = "pclk",
 669         .dev            = &at32_pm0_device.dev,
 670         .parent         = &pbb_clk,
 671         .mode           = pbb_clk_mode,
 672         .get_rate       = pbb_clk_get_rate,
 673         .users          = 1,
 674         .index          = 0,
 675 };
 676
 677 static struct resource intc0_resource[] = {
 678         PBMEM(0xfff00400),
 679 };
 680 struct platform_device at32_intc0_device = {
 681         .name           = "intc",
 682         .id             = 0,
 683         .resource       = intc0_resource,
 684         .num_resources  = ARRAY_SIZE(intc0_resource),
 685 };
 686 DEV_CLK(pclk, at32_intc0, pbb, 1);
 687
 688 static struct clk ebi_clk = {
 689         .name           = "ebi",
 690         .parent         = &hsb_clk,
 691         .mode           = hsb_clk_mode,
 692         .get_rate       = hsb_clk_get_rate,
 693         .users          = 1,
 694 };
 695 static struct clk hramc_clk = {
 696         .name           = "hramc",
 697         .parent         = &hsb_clk,
 698         .mode           = hsb_clk_mode,
 699         .get_rate       = hsb_clk_get_rate,
 700         .users          = 1,
 701         .index          = 3,
 702 };
 703 static struct clk sdramc_clk = {
 704         .name           = "sdramc_clk",
 705         .parent         = &pbb_clk,
 706         .mode           = pbb_clk_mode,
 707         .get_rate       = pbb_clk_get_rate,
 708         .users          = 1,
 709         .index          = 14,
 710 };
 711
 712 static struct resource smc0_resource[] = {
 713         PBMEM(0xfff03400),
 714 };
 715 DEFINE_DEV(smc, 0);
 716 DEV_CLK(pclk, smc0, pbb, 13);
 717 DEV_CLK(mck, smc0, hsb, 0);
 718
 719 static struct platform_device pdc_device = {
 720         .name           = "pdc",
 721         .id             = 0,
 722 };
 723 DEV_CLK(hclk, pdc, hsb, 4);
 724 DEV_CLK(pclk, pdc, pba, 16);
 725
 726 static struct clk pico_clk = {
 727         .name           = "pico",
 728         .parent         = &cpu_clk,
 729         .mode           = cpu_clk_mode,
 730         .get_rate       = cpu_clk_get_rate,
 731         .users          = 1,
 732 };
 733
 734 /* --------------------------------------------------------------------
 735  * HMATRIX
 736  * -------------------------------------------------------------------- */
 737
 738 struct clk at32_hmatrix_clk = {
 739         .name           = "hmatrix_clk",
 740         .parent         = &pbb_clk,
 741         .mode           = pbb_clk_mode,
 742         .get_rate       = pbb_clk_get_rate,
 743         .index          = 2,
 744         .users          = 1,
 745 };
 746
 747 /*
 748  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 749  * External Bus Interface (EBI). This can be used to enable special
 750  * features like CompactFlash support, NAND Flash support, etc. on
 751  * certain chipselects.
 752  */
 753 static inline void set_ebi_sfr_bits(u32 mask)
 754 {
 755         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
 756 }
 757
 758 /* --------------------------------------------------------------------
 759  *  Timer/Counter (TC)
 760  * -------------------------------------------------------------------- */
 761
 762 static struct resource at32_tcb0_resource[] = {
 763         PBMEM(0xfff00c00),
 764         IRQ(22),
 765 };
 766 static struct platform_device at32_tcb0_device = {
 767         .name           = "atmel_tcb",
 768         .id             = 0,
 769         .resource       = at32_tcb0_resource,
 770         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 771 };
 772 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 773
 774 static struct resource at32_tcb1_resource[] = {
 775         PBMEM(0xfff01000),
 776         IRQ(23),
 777 };
 778 static struct platform_device at32_tcb1_device = {
 779         .name           = "atmel_tcb",
 780         .id             = 1,
 781         .resource       = at32_tcb1_resource,
 782         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 783 };
 784 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 785
 786 /* --------------------------------------------------------------------
 787  *  PIO
 788  * -------------------------------------------------------------------- */
 789
 790 static struct resource pio0_resource[] = {
 791         PBMEM(0xffe02800),
 792         IRQ(13),
 793 };
 794 DEFINE_DEV(pio, 0);
 795 DEV_CLK(mck, pio0, pba, 10);
 796
 797 static struct resource pio1_resource[] = {
 798         PBMEM(0xffe02c00),
 799         IRQ(14),
 800 };
 801 DEFINE_DEV(pio, 1);
 802 DEV_CLK(mck, pio1, pba, 11);
 803
 804 static struct resource pio2_resource[] = {
 805         PBMEM(0xffe03000),
 806         IRQ(15),
 807 };
 808 DEFINE_DEV(pio, 2);
 809 DEV_CLK(mck, pio2, pba, 12);
 810
 811 static struct resource pio3_resource[] = {
 812         PBMEM(0xffe03400),
 813         IRQ(16),
 814 };
 815 DEFINE_DEV(pio, 3);
 816 DEV_CLK(mck, pio3, pba, 13);
 817
 818 static struct resource pio4_resource[] = {
 819         PBMEM(0xffe03800),
 820         IRQ(17),
 821 };
 822 DEFINE_DEV(pio, 4);
 823 DEV_CLK(mck, pio4, pba, 14);
 824
 825 static int __init system_device_init(void)
 826 {
 827         platform_device_register(&at32_pm0_device);
 828         platform_device_register(&at32_intc0_device);
 829         platform_device_register(&at32ap700x_rtc0_device);
 830         platform_device_register(&at32_wdt0_device);
 831         platform_device_register(&at32_eic0_device);
 832         platform_device_register(&smc0_device);
 833         platform_device_register(&pdc_device);
 834         platform_device_register(&dw_dmac0_device);
 835
 836         platform_device_register(&at32_tcb0_device);
 837         platform_device_register(&at32_tcb1_device);
 838
 839         platform_device_register(&pio0_device);
 840         platform_device_register(&pio1_device);
 841         platform_device_register(&pio2_device);
 842         platform_device_register(&pio3_device);
 843         platform_device_register(&pio4_device);
 844
 845         return 0;
 846 }
 847 core_initcall(system_device_init);
 848
 849 /* --------------------------------------------------------------------
 850  *  PSIF
 851  * -------------------------------------------------------------------- */
 852 static struct resource atmel_psif0_resource[] __initdata = {
 853         {
 854                 .start  = 0xffe03c00,
 855                 .end    = 0xffe03cff,
 856                 .flags  = IORESOURCE_MEM,
 857         },
 858         IRQ(18),
 859 };
 860 static struct clk atmel_psif0_pclk = {
 861         .name           = "pclk",
 862         .parent         = &pba_clk,
 863         .mode           = pba_clk_mode,
 864         .get_rate       = pba_clk_get_rate,
 865         .index          = 15,
 866 };
 867
 868 static struct resource atmel_psif1_resource[] __initdata = {
 869         {
 870                 .start  = 0xffe03d00,
 871                 .end    = 0xffe03dff,
 872                 .flags  = IORESOURCE_MEM,
 873         },
 874         IRQ(18),
 875 };
 876 static struct clk atmel_psif1_pclk = {
 877         .name           = "pclk",
 878         .parent         = &pba_clk,
 879         .mode           = pba_clk_mode,
 880         .get_rate       = pba_clk_get_rate,
 881         .index          = 15,
 882 };
 883
 884 struct platform_device *__init at32_add_device_psif(unsigned int id)
 885 {
 886         struct platform_device *pdev;
 887         u32 pin_mask;
 888
 889         if (!(id == 0 || id == 1))
 890                 return NULL;
 891
 892         pdev = platform_device_alloc("atmel_psif", id);
 893         if (!pdev)
 894                 return NULL;
 895
 896         switch (id) {
 897         case 0:
 898                 pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */
 899
 900                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
 901                                         ARRAY_SIZE(atmel_psif0_resource)))
 902                         goto err_add_resources;
 903                 atmel_psif0_pclk.dev = &pdev->dev;
 904                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
 905                 break;
 906         case 1:
 907                 pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */
 908
 909                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
 910                                         ARRAY_SIZE(atmel_psif1_resource)))
 911                         goto err_add_resources;
 912                 atmel_psif1_pclk.dev = &pdev->dev;
 913                 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
 914                 break;
 915         default:
 916                 return NULL;
 917         }
 918
 919         platform_device_add(pdev);
 920         return pdev;
 921
 922 err_add_resources:
 923         platform_device_put(pdev);
 924         return NULL;
 925 }
 926
 927 /* --------------------------------------------------------------------
 928  *  USART
 929  * -------------------------------------------------------------------- */
 930
 931 static struct atmel_uart_data atmel_usart0_data = {
 932         .use_dma_tx     = 1,
 933         .use_dma_rx     = 1,
 934 };
 935 static struct resource atmel_usart0_resource[] = {
 936         PBMEM(0xffe00c00),
 937         IRQ(6),
 938 };
 939 DEFINE_DEV_DATA(atmel_usart, 0);
 940 DEV_CLK(usart, atmel_usart0, pba, 3);
 941
 942 static struct atmel_uart_data atmel_usart1_data = {
 943         .use_dma_tx     = 1,
 944         .use_dma_rx     = 1,
 945 };
 946 static struct resource atmel_usart1_resource[] = {
 947         PBMEM(0xffe01000),
 948         IRQ(7),
 949 };
 950 DEFINE_DEV_DATA(atmel_usart, 1);
 951 DEV_CLK(usart, atmel_usart1, pba, 4);
 952
 953 static struct atmel_uart_data atmel_usart2_data = {
 954         .use_dma_tx     = 1,
 955         .use_dma_rx     = 1,
 956 };
 957 static struct resource atmel_usart2_resource[] = {
 958         PBMEM(0xffe01400),
 959         IRQ(8),
 960 };
 961 DEFINE_DEV_DATA(atmel_usart, 2);
 962 DEV_CLK(usart, atmel_usart2, pba, 5);
 963
 964 static struct atmel_uart_data atmel_usart3_data = {
 965         .use_dma_tx     = 1,
 966         .use_dma_rx     = 1,
 967 };
 968 static struct resource atmel_usart3_resource[] = {
 969         PBMEM(0xffe01800),
 970         IRQ(9),
 971 };
 972 DEFINE_DEV_DATA(atmel_usart, 3);
 973 DEV_CLK(usart, atmel_usart3, pba, 6);
 974
 975 static inline void configure_usart0_pins(int flags)
 976 {
 977         u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
 978         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 6);
 979         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 7);
 980         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 10);
 981
 982         select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
 983 }
 984
 985 static inline void configure_usart1_pins(int flags)
 986 {
 987         u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
 988         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 19);
 989         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 20);
 990         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 16);
 991
 992         select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
 993 }
 994
 995 static inline void configure_usart2_pins(int flags)
 996 {
 997         u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
 998         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 30);
 999         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 29);
1000         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 28);
1001
1002         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1003 }
1004
1005 static inline void configure_usart3_pins(int flags)
1006 {
1007         u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1008         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 16);
1009         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 15);
1010         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 19);
1011
1012         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1013 }
1014
1015 static struct platform_device *__initdata at32_usarts[4];
1016
1017 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1018 {
1019         struct platform_device *pdev;
1020         struct atmel_uart_data *pdata;
1021
1022         switch (hw_id) {
1023         case 0:
1024                 pdev = &atmel_usart0_device;
1025                 configure_usart0_pins(flags);
1026                 break;
1027         case 1:
1028                 pdev = &atmel_usart1_device;
1029                 configure_usart1_pins(flags);
1030                 break;
1031         case 2:
1032                 pdev = &atmel_usart2_device;
1033                 configure_usart2_pins(flags);
1034                 break;
1035         case 3:
1036                 pdev = &atmel_usart3_device;
1037                 configure_usart3_pins(flags);
1038                 break;
1039         default:
1040                 return;
1041         }
1042
1043         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1044                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1045                 struct atmel_uart_data *data = pdev->dev.platform_data;
1046                 data->regs = (void __iomem *)pdev->resource[0].start;
1047         }
1048
1049         pdev->id = line;
1050         pdata = pdev->dev.platform_data;
1051         pdata->num = line;
1052         at32_usarts[line] = pdev;
1053 }
1054
1055 struct platform_device *__init at32_add_device_usart(unsigned int id)
1056 {
1057         platform_device_register(at32_usarts[id]);
1058         return at32_usarts[id];
1059 }
1060
1061 void __init at32_setup_serial_console(unsigned int usart_id)
1062 {
1063 #ifdef CONFIG_SERIAL_ATMEL
1064         atmel_default_console_device = at32_usarts[usart_id];
1065 #endif
1066 }
1067
1068 /* --------------------------------------------------------------------
1069  *  Ethernet
1070  * -------------------------------------------------------------------- */
1071
1072 #ifdef CONFIG_CPU_AT32AP7000
1073 static struct macb_platform_data macb0_data;
1074 static struct resource macb0_resource[] = {
1075         PBMEM(0xfff01800),
1076         IRQ(25),
1077 };
1078 DEFINE_DEV_DATA(macb, 0);
1079 DEV_CLK(hclk, macb0, hsb, 8);
1080 DEV_CLK(pclk, macb0, pbb, 6);
1081
1082 static struct macb_platform_data macb1_data;
1083 static struct resource macb1_resource[] = {
1084         PBMEM(0xfff01c00),
1085         IRQ(26),
1086 };
1087 DEFINE_DEV_DATA(macb, 1);
1088 DEV_CLK(hclk, macb1, hsb, 9);
1089 DEV_CLK(pclk, macb1, pbb, 7);
1090
1091 struct platform_device *__init
1092 at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
1093 {
1094         struct platform_device *pdev;
1095         u32 pin_mask;
1096
1097         switch (id) {
1098         case 0:
1099                 pdev = &macb0_device;
1100
1101                 pin_mask  = (1 << 3);   /* TXD0 */
1102                 pin_mask |= (1 << 4);   /* TXD1 */
1103                 pin_mask |= (1 << 7);   /* TXEN */
1104                 pin_mask |= (1 << 8);   /* TXCK */
1105                 pin_mask |= (1 << 9);   /* RXD0 */
1106                 pin_mask |= (1 << 10);  /* RXD1 */
1107                 pin_mask |= (1 << 13);  /* RXER */
1108                 pin_mask |= (1 << 15);  /* RXDV */
1109                 pin_mask |= (1 << 16);  /* MDC  */
1110                 pin_mask |= (1 << 17);  /* MDIO */
1111
1112                 if (!data->is_rmii) {
1113                         pin_mask |= (1 << 0);   /* COL  */
1114                         pin_mask |= (1 << 1);   /* CRS  */
1115                         pin_mask |= (1 << 2);   /* TXER */
1116                         pin_mask |= (1 << 5);   /* TXD2 */
1117                         pin_mask |= (1 << 6);   /* TXD3 */
1118                         pin_mask |= (1 << 11);  /* RXD2 */
1119                         pin_mask |= (1 << 12);  /* RXD3 */
1120                         pin_mask |= (1 << 14);  /* RXCK */
1121 #ifndef CONFIG_BOARD_MIMC200
1122                         pin_mask |= (1 << 18);  /* SPD  */
1123 #endif
1124                 }
1125
1126                 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1127
1128                 break;
1129
1130         case 1:
1131                 pdev = &macb1_device;
1132
1133                 pin_mask  = (1 << 13);  /* TXD0 */
1134                 pin_mask |= (1 << 14);  /* TXD1 */
1135                 pin_mask |= (1 << 11);  /* TXEN */
1136                 pin_mask |= (1 << 12);  /* TXCK */
1137                 pin_mask |= (1 << 10);  /* RXD0 */
1138                 pin_mask |= (1 << 6);   /* RXD1 */
1139                 pin_mask |= (1 << 5);   /* RXER */
1140                 pin_mask |= (1 << 4);   /* RXDV */
1141                 pin_mask |= (1 << 3);   /* MDC  */
1142                 pin_mask |= (1 << 2);   /* MDIO */
1143
1144 #ifndef CONFIG_BOARD_MIMC200
1145                 if (!data->is_rmii)
1146                         pin_mask |= (1 << 15);  /* SPD  */
1147 #endif
1148
1149                 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1150
1151                 if (!data->is_rmii) {
1152                         pin_mask  = (1 << 19);  /* COL  */
1153                         pin_mask |= (1 << 23);  /* CRS  */
1154                         pin_mask |= (1 << 26);  /* TXER */
1155                         pin_mask |= (1 << 27);  /* TXD2 */
1156                         pin_mask |= (1 << 28);  /* TXD3 */
1157                         pin_mask |= (1 << 29);  /* RXD2 */
1158                         pin_mask |= (1 << 30);  /* RXD3 */
1159                         pin_mask |= (1 << 24);  /* RXCK */
1160
1161                         select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1162                 }
1163                 break;
1164
1165         default:
1166                 return NULL;
1167         }
1168
1169         memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
1170         platform_device_register(pdev);
1171
1172         return pdev;
1173 }
1174 #endif
1175
1176 /* --------------------------------------------------------------------
1177  *  SPI
1178  * -------------------------------------------------------------------- */
1179 static struct resource atmel_spi0_resource[] = {
1180         PBMEM(0xffe00000),
1181         IRQ(3),
1182 };
1183 DEFINE_DEV(atmel_spi, 0);
1184 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1185
1186 static struct resource atmel_spi1_resource[] = {
1187         PBMEM(0xffe00400),
1188         IRQ(4),
1189 };
1190 DEFINE_DEV(atmel_spi, 1);
1191 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1192
1193 void __init
1194 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1195 {
1196         /*
1197          * Manage the chipselects as GPIOs, normally using the same pins
1198          * the SPI controller expects; but boards can use other pins.
1199          */
1200         static u8 __initdata spi_pins[][4] = {
1201                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1202                   GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1203                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1204                   GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1205         };
1206         unsigned int pin, mode;
1207
1208         /* There are only 2 SPI controllers */
1209         if (bus_num > 1)
1210                 return;
1211
1212         for (; n; n--, b++) {
1213                 b->bus_num = bus_num;
1214                 if (b->chip_select >= 4)
1215                         continue;
1216                 pin = (unsigned)b->controller_data;
1217                 if (!pin) {
1218                         pin = spi_pins[bus_num][b->chip_select];
1219                         b->controller_data = (void *)pin;
1220                 }
1221                 mode = AT32_GPIOF_OUTPUT;
1222                 if (!(b->mode & SPI_CS_HIGH))
1223                         mode |= AT32_GPIOF_HIGH;
1224                 at32_select_gpio(pin, mode);
1225         }
1226 }
1227
1228 struct platform_device *__init
1229 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1230 {
1231         struct platform_device *pdev;
1232         u32 pin_mask;
1233
1234         switch (id) {
1235         case 0:
1236                 pdev = &atmel_spi0_device;
1237                 pin_mask  = (1 << 1) | (1 << 2);        /* MOSI & SCK */
1238
1239                 /* pullup MISO so a level is always defined */
1240                 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1241                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1242
1243                 at32_spi_setup_slaves(0, b, n);
1244                 break;
1245
1246         case 1:
1247                 pdev = &atmel_spi1_device;
1248                 pin_mask  = (1 << 1) | (1 << 5);        /* MOSI */
1249
1250                 /* pullup MISO so a level is always defined */
1251                 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1252                 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1253
1254                 at32_spi_setup_slaves(1, b, n);
1255                 break;
1256
1257         default:
1258                 return NULL;
1259         }
1260
1261         spi_register_board_info(b, n);
1262         platform_device_register(pdev);
1263         return pdev;
1264 }
1265
1266 /* --------------------------------------------------------------------
1267  *  TWI
1268  * -------------------------------------------------------------------- */
1269 static struct resource atmel_twi0_resource[] __initdata = {
1270         PBMEM(0xffe00800),
1271         IRQ(5),
1272 };
1273 static struct clk atmel_twi0_pclk = {
1274         .name           = "twi_pclk",
1275         .parent         = &pba_clk,
1276         .mode           = pba_clk_mode,
1277         .get_rate       = pba_clk_get_rate,
1278         .index          = 2,
1279 };
1280
1281 struct platform_device *__init at32_add_device_twi(unsigned int id,
1282                                                     struct i2c_board_info *b,
1283                                                     unsigned int n)
1284 {
1285         struct platform_device *pdev;
1286         u32 pin_mask;
1287
1288         if (id != 0)
1289                 return NULL;
1290
1291         pdev = platform_device_alloc("atmel_twi", id);
1292         if (!pdev)
1293                 return NULL;
1294
1295         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1296                                 ARRAY_SIZE(atmel_twi0_resource)))
1297                 goto err_add_resources;
1298
1299         pin_mask  = (1 << 6) | (1 << 7);        /* SDA & SDL */
1300
1301         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1302
1303         atmel_twi0_pclk.dev = &pdev->dev;
1304
1305         if (b)
1306                 i2c_register_board_info(id, b, n);
1307
1308         platform_device_add(pdev);
1309         return pdev;
1310
1311 err_add_resources:
1312         platform_device_put(pdev);
1313         return NULL;
1314 }
1315
1316 /* --------------------------------------------------------------------
1317  * MMC
1318  * -------------------------------------------------------------------- */
1319 static struct resource atmel_mci0_resource[] __initdata = {
1320         PBMEM(0xfff02400),
1321         IRQ(28),
1322 };
1323 static struct clk atmel_mci0_pclk = {
1324         .name           = "mci_clk",
1325         .parent         = &pbb_clk,
1326         .mode           = pbb_clk_mode,
1327         .get_rate       = pbb_clk_get_rate,
1328         .index          = 9,
1329 };
1330
1331 struct platform_device *__init
1332 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1333 {
1334         struct platform_device          *pdev;
1335         struct mci_dma_data             *slave;
1336         u32                             pioa_mask;
1337         u32                             piob_mask;
1338
1339         if (id != 0 || !data)
1340                 return NULL;
1341
1342         /* Must have at least one usable slot */
1343         if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1344                 return NULL;
1345
1346         pdev = platform_device_alloc("atmel_mci", id);
1347         if (!pdev)
1348                 goto fail;
1349
1350         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1351                                 ARRAY_SIZE(atmel_mci0_resource)))
1352                 goto fail;
1353
1354         slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
1355         if (!slave)
1356                 goto fail;
1357
1358         slave->sdata.dma_dev = &dw_dmac0_device.dev;
1359         slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
1360                                 | DWC_CFGH_DST_PER(1));
1361         slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1362                                 | DWC_CFGL_HS_SRC_POL);
1363         slave->sdata.src_master = 1;
1364         slave->sdata.dst_master = 0;
1365
1366         data->dma_slave = slave;
1367
1368         if (platform_device_add_data(pdev, data,
1369                                 sizeof(struct mci_platform_data)))
1370                 goto fail_free;
1371
1372         /* CLK line is common to both slots */
1373         pioa_mask = 1 << 10;
1374
1375         switch (data->slot[0].bus_width) {
1376         case 4:
1377                 pioa_mask |= 1 << 13;           /* DATA1 */
1378                 pioa_mask |= 1 << 14;           /* DATA2 */
1379                 pioa_mask |= 1 << 15;           /* DATA3 */
1380                 /* fall through */
1381         case 1:
1382                 pioa_mask |= 1 << 11;           /* CMD   */
1383                 pioa_mask |= 1 << 12;           /* DATA0 */
1384
1385                 if (gpio_is_valid(data->slot[0].detect_pin))
1386                         at32_select_gpio(data->slot[0].detect_pin, 0);
1387                 if (gpio_is_valid(data->slot[0].wp_pin))
1388                         at32_select_gpio(data->slot[0].wp_pin, 0);
1389                 break;
1390         case 0:
1391                 /* Slot is unused */
1392                 break;
1393         default:
1394                 goto fail_free;
1395         }
1396
1397         select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1398         piob_mask = 0;
1399
1400         switch (data->slot[1].bus_width) {
1401         case 4:
1402                 piob_mask |= 1 <<  8;           /* DATA1 */
1403                 piob_mask |= 1 <<  9;           /* DATA2 */
1404                 piob_mask |= 1 << 10;           /* DATA3 */
1405                 /* fall through */
1406         case 1:
1407                 piob_mask |= 1 <<  6;           /* CMD   */
1408                 piob_mask |= 1 <<  7;           /* DATA0 */
1409                 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1410
1411                 if (gpio_is_valid(data->slot[1].detect_pin))
1412                         at32_select_gpio(data->slot[1].detect_pin, 0);
1413                 if (gpio_is_valid(data->slot[1].wp_pin))
1414                         at32_select_gpio(data->slot[1].wp_pin, 0);
1415                 break;
1416         case 0:
1417                 /* Slot is unused */
1418                 break;
1419         default:
1420                 if (!data->slot[0].bus_width)
1421                         goto fail_free;
1422
1423                 data->slot[1].bus_width = 0;
1424                 break;
1425         }
1426
1427         atmel_mci0_pclk.dev = &pdev->dev;
1428
1429         platform_device_add(pdev);
1430         return pdev;
1431
1432 fail_free:
1433         kfree(slave);
1434 fail:
1435         data->dma_slave = NULL;
1436         platform_device_put(pdev);
1437         return NULL;
1438 }
1439
1440 /* --------------------------------------------------------------------
1441  *  LCDC
1442  * -------------------------------------------------------------------- */
1443 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1444 static struct atmel_lcdfb_pdata atmel_lcdfb0_data;
1445 static struct resource atmel_lcdfb0_resource[] = {
1446         {
1447                 .start          = 0xff000000,
1448                 .end            = 0xff000fff,
1449                 .flags          = IORESOURCE_MEM,
1450         },
1451         IRQ(1),
1452         {
1453                 /* Placeholder for pre-allocated fb memory */
1454                 .start          = 0x00000000,
1455                 .end            = 0x00000000,
1456                 .flags          = 0,
1457         },
1458 };
1459 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1460 DEV_CLK(hclk, atmel_lcdfb0, hsb, 7);
1461 static struct clk atmel_lcdfb0_pixclk = {
1462         .name           = "lcdc_clk",
1463         .dev            = &atmel_lcdfb0_device.dev,
1464         .mode           = genclk_mode,
1465         .get_rate       = genclk_get_rate,
1466         .set_rate       = genclk_set_rate,
1467         .set_parent     = genclk_set_parent,
1468         .index          = 7,
1469 };
1470
1471 struct platform_device *__init
1472 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_pdata *data,
1473                      unsigned long fbmem_start, unsigned long fbmem_len,
1474                      u64 pin_mask)
1475 {
1476         struct platform_device *pdev;
1477         struct atmel_lcdfb_pdata *info;
1478         struct fb_monspecs *monspecs;
1479         struct fb_videomode *modedb;
1480         unsigned int modedb_size;
1481         u32 portc_mask, portd_mask, porte_mask;
1482
1483         /*
1484          * Do a deep copy of the fb data, monspecs and modedb. Make
1485          * sure all allocations are done before setting up the
1486          * portmux.
1487          */
1488         monspecs = kmemdup(data->default_monspecs,
1489                            sizeof(struct fb_monspecs), GFP_KERNEL);
1490         if (!monspecs)
1491                 return NULL;
1492
1493         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1494         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1495         if (!modedb)
1496                 goto err_dup_modedb;
1497         monspecs->modedb = modedb;
1498
1499         switch (id) {
1500         case 0:
1501                 pdev = &atmel_lcdfb0_device;
1502
1503                 if (pin_mask == 0ULL)
1504                         /* Default to "full" lcdc control signals and 24bit */
1505                         pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1506
1507                 /* LCDC on port C */
1508                 portc_mask = pin_mask & 0xfff80000;
1509                 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1510
1511                 /* LCDC on port D */
1512                 portd_mask = pin_mask & 0x0003ffff;
1513                 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1514
1515                 /* LCDC on port E */
1516                 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1517                 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1518
1519                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1520                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1521                 break;
1522
1523         default:
1524                 goto err_invalid_id;
1525         }
1526
1527         if (fbmem_len) {
1528                 pdev->resource[2].start = fbmem_start;
1529                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1530                 pdev->resource[2].flags = IORESOURCE_MEM;
1531         }
1532
1533         info = pdev->dev.platform_data;
1534         memcpy(info, data, sizeof(struct atmel_lcdfb_pdata));
1535         info->default_monspecs = monspecs;
1536
1537         pdev->name = "at32ap-lcdfb";
1538
1539         platform_device_register(pdev);
1540         return pdev;
1541
1542 err_invalid_id:
1543         kfree(modedb);
1544 err_dup_modedb:
1545         kfree(monspecs);
1546         return NULL;
1547 }
1548 #endif
1549
1550 /* --------------------------------------------------------------------
1551  *  PWM
1552  * -------------------------------------------------------------------- */
1553 static struct resource atmel_pwm0_resource[] __initdata = {
1554         PBMEM(0xfff01400),
1555         IRQ(24),
1556 };
1557 static struct clk atmel_pwm0_mck = {
1558         .name           = "at91sam9rl-pwm",
1559         .parent         = &pbb_clk,
1560         .mode           = pbb_clk_mode,
1561         .get_rate       = pbb_clk_get_rate,
1562         .index          = 5,
1563 };
1564
1565 struct platform_device *__init at32_add_device_pwm(u32 mask)
1566 {
1567         struct platform_device *pdev;
1568         u32 pin_mask;
1569
1570         if (!mask)
1571                 return NULL;
1572
1573         pdev = platform_device_alloc("at91sam9rl-pwm", 0);
1574         if (!pdev)
1575                 return NULL;
1576
1577         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1578                                 ARRAY_SIZE(atmel_pwm0_resource)))
1579                 goto out_free_pdev;
1580
1581         pin_mask = 0;
1582         if (mask & (1 << 0))
1583                 pin_mask |= (1 << 28);
1584         if (mask & (1 << 1))
1585                 pin_mask |= (1 << 29);
1586         if (pin_mask > 0)
1587                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1588
1589         pin_mask = 0;
1590         if (mask & (1 << 2))
1591                 pin_mask |= (1 << 21);
1592         if (mask & (1 << 3))
1593                 pin_mask |= (1 << 22);
1594         if (pin_mask > 0)
1595                 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1596
1597         atmel_pwm0_mck.dev = &pdev->dev;
1598
1599         platform_device_add(pdev);
1600
1601         return pdev;
1602
1603 out_free_pdev:
1604         platform_device_put(pdev);
1605         return NULL;
1606 }
1607
1608 /* --------------------------------------------------------------------
1609  *  SSC
1610  * -------------------------------------------------------------------- */
1611 static struct resource ssc0_resource[] = {
1612         PBMEM(0xffe01c00),
1613         IRQ(10),
1614 };
1615 DEFINE_DEV(ssc, 0);
1616 DEV_CLK(pclk, ssc0, pba, 7);
1617
1618 static struct resource ssc1_resource[] = {
1619         PBMEM(0xffe02000),
1620         IRQ(11),
1621 };
1622 DEFINE_DEV(ssc, 1);
1623 DEV_CLK(pclk, ssc1, pba, 8);
1624
1625 static struct resource ssc2_resource[] = {
1626         PBMEM(0xffe02400),
1627         IRQ(12),
1628 };
1629 DEFINE_DEV(ssc, 2);
1630 DEV_CLK(pclk, ssc2, pba, 9);
1631
1632 struct platform_device *__init
1633 at32_add_device_ssc(unsigned int id, unsigned int flags)
1634 {
1635         struct platform_device *pdev;
1636         u32 pin_mask = 0;
1637
1638         switch (id) {
1639         case 0:
1640                 pdev = &ssc0_device;
1641                 if (flags & ATMEL_SSC_RF)
1642                         pin_mask |= (1 << 21);  /* RF */
1643                 if (flags & ATMEL_SSC_RK)
1644                         pin_mask |= (1 << 22);  /* RK */
1645                 if (flags & ATMEL_SSC_TK)
1646                         pin_mask |= (1 << 23);  /* TK */
1647                 if (flags & ATMEL_SSC_TF)
1648                         pin_mask |= (1 << 24);  /* TF */
1649                 if (flags & ATMEL_SSC_TD)
1650                         pin_mask |= (1 << 25);  /* TD */
1651                 if (flags & ATMEL_SSC_RD)
1652                         pin_mask |= (1 << 26);  /* RD */
1653
1654                 if (pin_mask > 0)
1655                         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1656
1657                 break;
1658         case 1:
1659                 pdev = &ssc1_device;
1660                 if (flags & ATMEL_SSC_RF)
1661                         pin_mask |= (1 << 0);   /* RF */
1662                 if (flags & ATMEL_SSC_RK)
1663                         pin_mask |= (1 << 1);   /* RK */
1664                 if (flags & ATMEL_SSC_TK)
1665                         pin_mask |= (1 << 2);   /* TK */
1666                 if (flags & ATMEL_SSC_TF)
1667                         pin_mask |= (1 << 3);   /* TF */
1668                 if (flags & ATMEL_SSC_TD)
1669                         pin_mask |= (1 << 4);   /* TD */
1670                 if (flags & ATMEL_SSC_RD)
1671                         pin_mask |= (1 << 5);   /* RD */
1672
1673                 if (pin_mask > 0)
1674                         select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1675
1676                 break;
1677         case 2:
1678                 pdev = &ssc2_device;
1679                 if (flags & ATMEL_SSC_TD)
1680                         pin_mask |= (1 << 13);  /* TD */
1681                 if (flags & ATMEL_SSC_RD)
1682                         pin_mask |= (1 << 14);  /* RD */
1683                 if (flags & ATMEL_SSC_TK)
1684                         pin_mask |= (1 << 15);  /* TK */
1685                 if (flags & ATMEL_SSC_TF)
1686                         pin_mask |= (1 << 16);  /* TF */
1687                 if (flags & ATMEL_SSC_RF)
1688                         pin_mask |= (1 << 17);  /* RF */
1689                 if (flags & ATMEL_SSC_RK)
1690                         pin_mask |= (1 << 18);  /* RK */
1691
1692                 if (pin_mask > 0)
1693                         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1694
1695                 break;
1696         default:
1697                 return NULL;
1698         }
1699
1700         platform_device_register(pdev);
1701         return pdev;
1702 }
1703
1704 /* --------------------------------------------------------------------
1705  *  USB Device Controller
1706  * -------------------------------------------------------------------- */
1707 static struct resource usba0_resource[] __initdata = {
1708         {
1709                 .start          = 0xff300000,
1710                 .end            = 0xff3fffff,
1711                 .flags          = IORESOURCE_MEM,
1712         }, {
1713                 .start          = 0xfff03000,
1714                 .end            = 0xfff033ff,
1715                 .flags          = IORESOURCE_MEM,
1716         },
1717         IRQ(31),
1718 };
1719 static struct clk usba0_pclk = {
1720         .name           = "pclk",
1721         .parent         = &pbb_clk,
1722         .mode           = pbb_clk_mode,
1723         .get_rate       = pbb_clk_get_rate,
1724         .index          = 12,
1725 };
1726 static struct clk usba0_hclk = {
1727         .name           = "hclk",
1728         .parent         = &hsb_clk,
1729         .mode           = hsb_clk_mode,
1730         .get_rate       = hsb_clk_get_rate,
1731         .index          = 6,
1732 };
1733
1734 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1735         [idx] = {                                               \
1736                 .name           = nam,                          \
1737                 .index          = idx,                          \
1738                 .fifo_size      = maxpkt,                       \
1739                 .nr_banks       = maxbk,                        \
1740                 .can_dma        = dma,                          \
1741                 .can_isoc       = isoc,                         \
1742         }
1743
1744 static struct usba_ep_data at32_usba_ep[] __initdata = {
1745         EP("ep0",     0,   64, 1, 0, 0),
1746         EP("ep1",     1,  512, 2, 1, 1),
1747         EP("ep2",     2,  512, 2, 1, 1),
1748         EP("ep3-int", 3,   64, 3, 1, 0),
1749         EP("ep4-int", 4,   64, 3, 1, 0),
1750         EP("ep5",     5, 1024, 3, 1, 1),
1751         EP("ep6",     6, 1024, 3, 1, 1),
1752 };
1753
1754 #undef EP
1755
1756 struct platform_device *__init
1757 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1758 {
1759         /*
1760          * pdata doesn't have room for any endpoints, so we need to
1761          * append room for the ones we need right after it.
1762          */
1763         struct {
1764                 struct usba_platform_data pdata;
1765                 struct usba_ep_data ep[7];
1766         } usba_data;
1767         struct platform_device *pdev;
1768
1769         if (id != 0)
1770                 return NULL;
1771
1772         pdev = platform_device_alloc("atmel_usba_udc", 0);
1773         if (!pdev)
1774                 return NULL;
1775
1776         if (platform_device_add_resources(pdev, usba0_resource,
1777                                           ARRAY_SIZE(usba0_resource)))
1778                 goto out_free_pdev;
1779
1780         if (data) {
1781                 usba_data.pdata.vbus_pin = data->vbus_pin;
1782                 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
1783         } else {
1784                 usba_data.pdata.vbus_pin = -EINVAL;
1785                 usba_data.pdata.vbus_pin_inverted = -EINVAL;
1786         }
1787
1788         data = &usba_data.pdata;
1789         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1790         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1791
1792         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1793                 goto out_free_pdev;
1794
1795         if (gpio_is_valid(data->vbus_pin))
1796                 at32_select_gpio(data->vbus_pin, 0);
1797
1798         usba0_pclk.dev = &pdev->dev;
1799         usba0_hclk.dev = &pdev->dev;
1800
1801         platform_device_add(pdev);
1802
1803         return pdev;
1804
1805 out_free_pdev:
1806         platform_device_put(pdev);
1807         return NULL;
1808 }
1809
1810 /* --------------------------------------------------------------------
1811  * IDE / CompactFlash
1812  * -------------------------------------------------------------------- */
1813 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1814 static struct resource at32_smc_cs4_resource[] __initdata = {
1815         {
1816                 .start  = 0x04000000,
1817                 .end    = 0x07ffffff,
1818                 .flags  = IORESOURCE_MEM,
1819         },
1820         IRQ(~0UL), /* Magic IRQ will be overridden */
1821 };
1822 static struct resource at32_smc_cs5_resource[] __initdata = {
1823         {
1824                 .start  = 0x20000000,
1825                 .end    = 0x23ffffff,
1826                 .flags  = IORESOURCE_MEM,
1827         },
1828         IRQ(~0UL), /* Magic IRQ will be overridden */
1829 };
1830
1831 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1832                 unsigned int cs, unsigned int extint)
1833 {
1834         static unsigned int extint_pin_map[4] __initdata = {
1835                 (1 << 25),
1836                 (1 << 26),
1837                 (1 << 27),
1838                 (1 << 28),
1839         };
1840         static bool common_pins_initialized __initdata = false;
1841         unsigned int extint_pin;
1842         int ret;
1843         u32 pin_mask;
1844
1845         if (extint >= ARRAY_SIZE(extint_pin_map))
1846                 return -EINVAL;
1847         extint_pin = extint_pin_map[extint];
1848
1849         switch (cs) {
1850         case 4:
1851                 ret = platform_device_add_resources(pdev,
1852                                 at32_smc_cs4_resource,
1853                                 ARRAY_SIZE(at32_smc_cs4_resource));
1854                 if (ret)
1855                         return ret;
1856
1857                 /* NCS4   -> OE_N  */
1858                 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1859                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1860                 break;
1861         case 5:
1862                 ret = platform_device_add_resources(pdev,
1863                                 at32_smc_cs5_resource,
1864                                 ARRAY_SIZE(at32_smc_cs5_resource));
1865                 if (ret)
1866                         return ret;
1867
1868                 /* NCS5   -> OE_N  */
1869                 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1870                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1871                 break;
1872         default:
1873                 return -EINVAL;
1874         }
1875
1876         if (!common_pins_initialized) {
1877                 pin_mask  = (1 << 19);  /* CFCE1  -> CS0_N */
1878                 pin_mask |= (1 << 20);  /* CFCE2  -> CS1_N */
1879                 pin_mask |= (1 << 23);  /* CFRNW  -> DIR   */
1880                 pin_mask |= (1 << 24);  /* NWAIT  <- IORDY */
1881
1882                 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1883
1884                 common_pins_initialized = true;
1885         }
1886
1887         select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1888
1889         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1890         pdev->resource[1].end = pdev->resource[1].start;
1891
1892         return 0;
1893 }
1894
1895 struct platform_device *__init
1896 at32_add_device_ide(unsigned int id, unsigned int extint,
1897                     struct ide_platform_data *data)
1898 {
1899         struct platform_device *pdev;
1900
1901         pdev = platform_device_alloc("at32_ide", id);
1902         if (!pdev)
1903                 goto fail;
1904
1905         if (platform_device_add_data(pdev, data,
1906                                 sizeof(struct ide_platform_data)))
1907                 goto fail;
1908
1909         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1910                 goto fail;
1911
1912         platform_device_add(pdev);
1913         return pdev;
1914
1915 fail:
1916         platform_device_put(pdev);
1917         return NULL;
1918 }
1919
1920 struct platform_device *__init
1921 at32_add_device_cf(unsigned int id, unsigned int extint,
1922                     struct cf_platform_data *data)
1923 {
1924         struct platform_device *pdev;
1925
1926         pdev = platform_device_alloc("at32_cf", id);
1927         if (!pdev)
1928                 goto fail;
1929
1930         if (platform_device_add_data(pdev, data,
1931                                 sizeof(struct cf_platform_data)))
1932                 goto fail;
1933
1934         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1935                 goto fail;
1936
1937         if (gpio_is_valid(data->detect_pin))
1938                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1939         if (gpio_is_valid(data->reset_pin))
1940                 at32_select_gpio(data->reset_pin, 0);
1941         if (gpio_is_valid(data->vcc_pin))
1942                 at32_select_gpio(data->vcc_pin, 0);
1943         /* READY is used as extint, so we can't select it as gpio */
1944
1945         platform_device_add(pdev);
1946         return pdev;
1947
1948 fail:
1949         platform_device_put(pdev);
1950         return NULL;
1951 }
1952 #endif
1953
1954 /* --------------------------------------------------------------------
1955  * NAND Flash / SmartMedia
1956  * -------------------------------------------------------------------- */
1957 static struct resource smc_cs3_resource[] __initdata = {
1958         {
1959                 .start  = 0x0c000000,
1960                 .end    = 0x0fffffff,
1961                 .flags  = IORESOURCE_MEM,
1962         }, {
1963                 .start  = 0xfff03c00,
1964                 .end    = 0xfff03fff,
1965                 .flags  = IORESOURCE_MEM,
1966         },
1967 };
1968
1969 struct platform_device *__init
1970 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1971 {
1972         struct platform_device *pdev;
1973
1974         if (id != 0 || !data)
1975                 return NULL;
1976
1977         pdev = platform_device_alloc("atmel_nand", id);
1978         if (!pdev)
1979                 goto fail;
1980
1981         if (platform_device_add_resources(pdev, smc_cs3_resource,
1982                                 ARRAY_SIZE(smc_cs3_resource)))
1983                 goto fail;
1984
1985         /* For at32ap7000, we use the reset workaround for nand driver */
1986         data->need_reset_workaround = true;
1987
1988         if (platform_device_add_data(pdev, data,
1989                                 sizeof(struct atmel_nand_data)))
1990                 goto fail;
1991
1992         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1993         if (data->enable_pin)
1994                 at32_select_gpio(data->enable_pin,
1995                                 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1996         if (data->rdy_pin)
1997                 at32_select_gpio(data->rdy_pin, 0);
1998         if (data->det_pin)
1999                 at32_select_gpio(data->det_pin, 0);
2000
2001         platform_device_add(pdev);
2002         return pdev;
2003
2004 fail:
2005         platform_device_put(pdev);
2006         return NULL;
2007 }
2008
2009 /* --------------------------------------------------------------------
2010  * AC97C
2011  * -------------------------------------------------------------------- */
2012 static struct resource atmel_ac97c0_resource[] __initdata = {
2013         PBMEM(0xfff02800),
2014         IRQ(29),
2015 };
2016 static struct clk atmel_ac97c0_pclk = {
2017         .name           = "pclk",
2018         .parent         = &pbb_clk,
2019         .mode           = pbb_clk_mode,
2020         .get_rate       = pbb_clk_get_rate,
2021         .index          = 10,
2022 };
2023
2024 struct platform_device *__init
2025 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2026                       unsigned int flags)
2027 {
2028         struct platform_device          *pdev;
2029         struct dw_dma_slave             *rx_dws;
2030         struct dw_dma_slave             *tx_dws;
2031         struct ac97c_platform_data      _data;
2032         u32                             pin_mask;
2033
2034         if (id != 0)
2035                 return NULL;
2036
2037         pdev = platform_device_alloc("atmel_ac97c", id);
2038         if (!pdev)
2039                 return NULL;
2040
2041         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2042                                 ARRAY_SIZE(atmel_ac97c0_resource)))
2043                 goto out_free_resources;
2044
2045         if (!data) {
2046                 data = &_data;
2047                 memset(data, 0, sizeof(struct ac97c_platform_data));
2048                 data->reset_pin = -ENODEV;
2049         }
2050
2051         rx_dws = &data->rx_dws;
2052         tx_dws = &data->tx_dws;
2053
2054         /* Check if DMA slave interface for capture should be configured. */
2055         if (flags & AC97C_CAPTURE) {
2056                 rx_dws->dma_dev = &dw_dmac0_device.dev;
2057                 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2058                 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2059                 rx_dws->src_master = 0;
2060                 rx_dws->dst_master = 1;
2061         }
2062
2063         /* Check if DMA slave interface for playback should be configured. */
2064         if (flags & AC97C_PLAYBACK) {
2065                 tx_dws->dma_dev = &dw_dmac0_device.dev;
2066                 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2067                 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2068                 tx_dws->src_master = 0;
2069                 tx_dws->dst_master = 1;
2070         }
2071
2072         if (platform_device_add_data(pdev, data,
2073                                 sizeof(struct ac97c_platform_data)))
2074                 goto out_free_resources;
2075
2076         /* SDO | SYNC | SCLK | SDI */
2077         pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2078
2079         select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2080
2081         if (gpio_is_valid(data->reset_pin))
2082                 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2083                                 | AT32_GPIOF_HIGH);
2084
2085         atmel_ac97c0_pclk.dev = &pdev->dev;
2086
2087         platform_device_add(pdev);
2088         return pdev;
2089
2090 out_free_resources:
2091         platform_device_put(pdev);
2092         return NULL;
2093 }
2094
2095 /* --------------------------------------------------------------------
2096  * ABDAC
2097  * -------------------------------------------------------------------- */
2098 static struct resource abdac0_resource[] __initdata = {
2099         PBMEM(0xfff02000),
2100         IRQ(27),
2101 };
2102 static struct clk abdac0_pclk = {
2103         .name           = "pclk",
2104         .parent         = &pbb_clk,
2105         .mode           = pbb_clk_mode,
2106         .get_rate       = pbb_clk_get_rate,
2107         .index          = 8,
2108 };
2109 static struct clk abdac0_sample_clk = {
2110         .name           = "sample_clk",
2111         .mode           = genclk_mode,
2112         .get_rate       = genclk_get_rate,
2113         .set_rate       = genclk_set_rate,
2114         .set_parent     = genclk_set_parent,
2115         .index          = 6,
2116 };
2117
2118 struct platform_device *__init
2119 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2120 {
2121         struct platform_device  *pdev;
2122         struct dw_dma_slave     *dws;
2123         u32                     pin_mask;
2124
2125         if (id != 0 || !data)
2126                 return NULL;
2127
2128         pdev = platform_device_alloc("atmel_abdac", id);
2129         if (!pdev)
2130                 return NULL;
2131
2132         if (platform_device_add_resources(pdev, abdac0_resource,
2133                                 ARRAY_SIZE(abdac0_resource)))
2134                 goto out_free_resources;
2135
2136         dws = &data->dws;
2137
2138         dws->dma_dev = &dw_dmac0_device.dev;
2139         dws->cfg_hi = DWC_CFGH_DST_PER(2);
2140         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2141         dws->src_master = 0;
2142         dws->dst_master = 1;
2143
2144         if (platform_device_add_data(pdev, data,
2145                                 sizeof(struct atmel_abdac_pdata)))
2146                 goto out_free_resources;
2147
2148         pin_mask  = (1 << 20) | (1 << 22);      /* DATA1 & DATAN1 */
2149         pin_mask |= (1 << 21) | (1 << 23);      /* DATA0 & DATAN0 */
2150
2151         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2152
2153         abdac0_pclk.dev = &pdev->dev;
2154         abdac0_sample_clk.dev = &pdev->dev;
2155
2156         platform_device_add(pdev);
2157         return pdev;
2158
2159 out_free_resources:
2160         platform_device_put(pdev);
2161         return NULL;
2162 }
2163
2164 /* --------------------------------------------------------------------
2165  *  GCLK
2166  * -------------------------------------------------------------------- */
2167 static struct clk gclk0 = {
2168         .name           = "gclk0",
2169         .mode           = genclk_mode,
2170         .get_rate       = genclk_get_rate,
2171         .set_rate       = genclk_set_rate,
2172         .set_parent     = genclk_set_parent,
2173         .index          = 0,
2174 };
2175 static struct clk gclk1 = {
2176         .name           = "gclk1",
2177         .mode           = genclk_mode,
2178         .get_rate       = genclk_get_rate,
2179         .set_rate       = genclk_set_rate,
2180         .set_parent     = genclk_set_parent,
2181         .index          = 1,
2182 };
2183 static struct clk gclk2 = {
2184         .name           = "gclk2",
2185         .mode           = genclk_mode,
2186         .get_rate       = genclk_get_rate,
2187         .set_rate       = genclk_set_rate,
2188         .set_parent     = genclk_set_parent,
2189         .index          = 2,
2190 };
2191 static struct clk gclk3 = {
2192         .name           = "gclk3",
2193         .mode           = genclk_mode,
2194         .get_rate       = genclk_get_rate,
2195         .set_rate       = genclk_set_rate,
2196         .set_parent     = genclk_set_parent,
2197         .index          = 3,
2198 };
2199 static struct clk gclk4 = {
2200         .name           = "gclk4",
2201         .mode           = genclk_mode,
2202         .get_rate       = genclk_get_rate,
2203         .set_rate       = genclk_set_rate,
2204         .set_parent     = genclk_set_parent,
2205         .index          = 4,
2206 };
2207
2208 static __initdata struct clk *init_clocks[] = {
2209         &osc32k,
2210         &osc0,
2211         &osc1,
2212         &pll0,
2213         &pll1,
2214         &cpu_clk,
2215         &hsb_clk,
2216         &pba_clk,
2217         &pbb_clk,
2218         &at32_pm_pclk,
2219         &at32_intc0_pclk,
2220         &at32_hmatrix_clk,
2221         &ebi_clk,
2222         &hramc_clk,
2223         &sdramc_clk,
2224         &smc0_pclk,
2225         &smc0_mck,
2226         &pdc_hclk,
2227         &pdc_pclk,
2228         &dw_dmac0_hclk,
2229         &pico_clk,
2230         &pio0_mck,
2231         &pio1_mck,
2232         &pio2_mck,
2233         &pio3_mck,
2234         &pio4_mck,
2235         &at32_tcb0_t0_clk,
2236         &at32_tcb1_t0_clk,
2237         &atmel_psif0_pclk,
2238         &atmel_psif1_pclk,
2239         &atmel_usart0_usart,
2240         &atmel_usart1_usart,
2241         &atmel_usart2_usart,
2242         &atmel_usart3_usart,
2243         &atmel_pwm0_mck,
2244 #if defined(CONFIG_CPU_AT32AP7000)
2245         &macb0_hclk,
2246         &macb0_pclk,
2247         &macb1_hclk,
2248         &macb1_pclk,
2249 #endif
2250         &atmel_spi0_spi_clk,
2251         &atmel_spi1_spi_clk,
2252         &atmel_twi0_pclk,
2253         &atmel_mci0_pclk,
2254 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2255         &atmel_lcdfb0_hclk,
2256         &atmel_lcdfb0_pixclk,
2257 #endif
2258         &ssc0_pclk,
2259         &ssc1_pclk,
2260         &ssc2_pclk,
2261         &usba0_hclk,
2262         &usba0_pclk,
2263         &atmel_ac97c0_pclk,
2264         &abdac0_pclk,
2265         &abdac0_sample_clk,
2266         &gclk0,
2267         &gclk1,
2268         &gclk2,
2269         &gclk3,
2270         &gclk4,
2271 };
2272
2273 void __init setup_platform(void)
2274 {
2275         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2276         int i;
2277
2278         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2279                 main_clock = &pll0;
2280                 cpu_clk.parent = &pll0;
2281         } else {
2282                 main_clock = &osc0;
2283                 cpu_clk.parent = &osc0;
2284         }
2285
2286         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2287                 pll0.parent = &osc1;
2288         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2289                 pll1.parent = &osc1;
2290
2291         genclk_init_parent(&gclk0);
2292         genclk_init_parent(&gclk1);
2293         genclk_init_parent(&gclk2);
2294         genclk_init_parent(&gclk3);
2295         genclk_init_parent(&gclk4);
2296 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2297         genclk_init_parent(&atmel_lcdfb0_pixclk);
2298 #endif
2299         genclk_init_parent(&abdac0_sample_clk);
2300
2301         /*
2302          * Build initial dynamic clock list by registering all clocks
2303          * from the array.
2304          * At the same time, turn on all clocks that have at least one
2305          * user already, and turn off everything else. We only do this
2306          * for module clocks, and even though it isn't particularly
2307          * pretty to  check the address of the mode function, it should
2308          * do the trick...
2309          */
2310         for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2311                 struct clk *clk = init_clocks[i];
2312
2313                 /* first, register clock */
2314                 at32_clk_register(clk);
2315
2316                 if (clk->users == 0)
2317                         continue;
2318
2319                 if (clk->mode == &cpu_clk_mode)
2320                         cpu_mask |= 1 << clk->index;
2321                 else if (clk->mode == &hsb_clk_mode)
2322                         hsb_mask |= 1 << clk->index;
2323                 else if (clk->mode == &pba_clk_mode)
2324                         pba_mask |= 1 << clk->index;
2325                 else if (clk->mode == &pbb_clk_mode)
2326                         pbb_mask |= 1 << clk->index;
2327         }
2328
2329         pm_writel(CPU_MASK, cpu_mask);
2330         pm_writel(HSB_MASK, hsb_mask);
2331         pm_writel(PBA_MASK, pba_mask);
2332         pm_writel(PBB_MASK, pbb_mask);
2333
2334         /* Initialize the port muxes */
2335         at32_init_pio(&pio0_device);
2336         at32_init_pio(&pio1_device);
2337         at32_init_pio(&pio2_device);
2338         at32_init_pio(&pio3_device);
2339         at32_init_pio(&pio4_device);
2340 }
2341
2342 struct gen_pool *sram_pool;
2343
2344 static int __init sram_init(void)
2345 {
2346         struct gen_pool *pool;
2347
2348         /* 1KiB granularity */
2349         pool = gen_pool_create(10, -1);
2350         if (!pool)
2351                 goto fail;
2352
2353         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2354                 goto err_pool_add;
2355
2356         sram_pool = pool;
2357         return 0;
2358
2359 err_pool_add:
2360         gen_pool_destroy(pool);
2361 fail:
2362         pr_err("Failed to create SRAM pool\n");
2363         return -ENOMEM;
2364 }
2365 core_initcall(sram_init);