2 * Blackfin core clock scaling
4 * Copyright 2008-2011 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/cpufreq.h>
15 #include <linux/delay.h>
16 #include <asm/blackfin.h>
20 /* this is the table of CCLK frequencies, in Hz */
21 /* .index is the entry in the auxiliary dpm_state_table[] */
22 static struct cpufreq_frequency_table bfin_freq_table[] = {
24 .frequency = CPUFREQ_TABLE_END,
28 .frequency = CPUFREQ_TABLE_END,
32 .frequency = CPUFREQ_TABLE_END,
36 .frequency = CPUFREQ_TABLE_END,
41 static struct bfin_dpm_state {
42 unsigned int csel; /* system clock divider */
43 unsigned int tscale; /* change the divider on the core timer interrupt */
46 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
48 * normalized to maximum frequency offset for CYCLES,
49 * used in time-ts cycles clock source, but could be used
52 unsigned long long __bfin_cycles_off;
53 unsigned int __bfin_cycles_mod;
56 /**************************************************************************/
57 static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
60 unsigned long csel, min_cclk;
63 /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
64 #if ANOMALY_05000273 || ANOMALY_05000274 || \
65 (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
70 csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
72 for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
73 bfin_freq_table[index].frequency = cclk >> index;
74 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
75 dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1;
77 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
78 bfin_freq_table[index].frequency,
79 dpm_state_table[index].csel,
80 dpm_state_table[index].tscale);
85 static void bfin_adjust_core_timer(void *info)
88 unsigned int index = *(unsigned int *)info;
90 /* we have to adjust the core timer, because it is using cclk */
91 tscale = dpm_state_table[index].tscale;
92 bfin_write_TSCALE(tscale);
96 static unsigned int bfin_getfreq_khz(unsigned int cpu)
98 /* Both CoreA/B have the same core clock */
99 return get_cclk() / 1000;
102 static int bfin_target(struct cpufreq_policy *poli,
103 unsigned int target_freq, unsigned int relation)
105 unsigned int index, plldiv, cpu;
106 unsigned long flags, cclk_hz;
107 struct cpufreq_freqs freqs;
108 static unsigned long lpj_ref;
109 static unsigned int lpj_ref_freq;
111 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
115 for_each_online_cpu(cpu) {
116 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
121 if (cpufreq_frequency_table_target(policy, bfin_freq_table,
122 target_freq, relation, &index))
125 cclk_hz = bfin_freq_table[index].frequency;
127 freqs.old = bfin_getfreq_khz(0);
131 pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
132 cclk_hz, target_freq, freqs.old);
134 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
135 if (cpu == CPUFREQ_CPU) {
136 flags = hard_local_irq_save();
137 plldiv = (bfin_read_PLL_DIV() & SSEL) |
138 dpm_state_table[index].csel;
139 bfin_write_PLL_DIV(plldiv);
140 on_each_cpu(bfin_adjust_core_timer, &index, 1);
141 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
142 cycles = get_cycles();
144 cycles += 10; /* ~10 cycles we lose after get_cycles() */
146 (cycles << __bfin_cycles_mod) - (cycles << index);
147 __bfin_cycles_mod = index;
150 lpj_ref = loops_per_jiffy;
151 lpj_ref_freq = freqs.old;
153 if (freqs.new != freqs.old) {
154 loops_per_jiffy = cpufreq_scale(lpj_ref,
155 lpj_ref_freq, freqs.new);
157 hard_local_irq_restore(flags);
159 /* TODO: just test case for cycles clock source, remove later */
160 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
163 pr_debug("cpufreq: done\n");
167 static int bfin_verify_speed(struct cpufreq_policy *policy)
169 return cpufreq_frequency_table_verify(policy, bfin_freq_table);
172 static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
175 unsigned long cclk, sclk;
177 cclk = get_cclk() / 1000;
178 sclk = get_sclk() / 1000;
180 if (policy->cpu == CPUFREQ_CPU)
181 bfin_init_tables(cclk, sclk);
183 policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
186 cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
187 return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
190 static struct freq_attr *bfin_freq_attr[] = {
191 &cpufreq_freq_attr_scaling_available_freqs,
195 static struct cpufreq_driver bfin_driver = {
196 .verify = bfin_verify_speed,
197 .target = bfin_target,
198 .get = bfin_getfreq_khz,
199 .init = __bfin_cpu_init,
200 .name = "bfin cpufreq",
201 .owner = THIS_MODULE,
202 .attr = bfin_freq_attr,
205 static int __init bfin_cpu_init(void)
207 return cpufreq_register_driver(&bfin_driver);
210 static void __exit bfin_cpu_exit(void)
212 cpufreq_unregister_driver(&bfin_driver);
215 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
216 MODULE_DESCRIPTION("cpufreq driver for Blackfin");
217 MODULE_LICENSE("GPL");
219 module_init(bfin_cpu_init);
220 module_exit(bfin_cpu_exit);