2 * Artec-3 general port I/O device
4 * Copyright (c) 2007 Axis Communications AB
6 * Authors: Bjorn Wesen (initial version)
7 * Ola Knutsson (LED handling)
8 * Johan Adolfsson (read/set directions, write, port G,
10 * Ricard Wanderlof (PWM for Artpec-3)
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/errno.h>
19 #include <linux/kernel.h>
21 #include <linux/string.h>
22 #include <linux/poll.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/spinlock.h>
27 #include <asm/etraxgpio.h>
28 #include <hwregs/reg_map.h>
29 #include <hwregs/reg_rdwr.h>
30 #include <hwregs/gio_defs.h>
31 #include <hwregs/intr_vect_defs.h>
33 #include <asm/system.h>
35 #include <asm/arch/mach/pinmux.h>
37 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
40 #define VIRT_I2C_ADDR 0x40
43 /* The following gio ports on ARTPEC-3 is available:
47 * each port has a rw_px_dout, r_px_din and rw_px_oe register.
50 #define GPIO_MAJOR 120 /* experimental MAJOR number */
52 #define I2C_INTERRUPT_BITS 0x300 /* i2c0_done and i2c1_done bits */
61 if (dp_cnt % 1000 == 0) \
68 static char gpio_name[] = "etrax gpio";
70 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
71 static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
74 static int gpio_ioctl(struct inode *inode, struct file *file,
75 unsigned int cmd, unsigned long arg);
76 static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
78 static int gpio_open(struct inode *inode, struct file *filp);
79 static int gpio_release(struct inode *inode, struct file *filp);
80 static unsigned int gpio_poll(struct file *filp,
81 struct poll_table_struct *wait);
83 /* private data per open() of this driver */
86 struct gpio_private *next;
87 /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
88 unsigned char clk_mask;
89 unsigned char data_mask;
90 unsigned char write_msb;
92 /* These fields are generic */
93 unsigned long highalarm, lowalarm;
94 wait_queue_head_t alarm_wq;
98 static void gpio_set_alarm(struct gpio_private *priv);
100 /* linked list of alarms to check for */
102 static struct gpio_private *alarmlist;
104 static int wanted_interrupts;
106 static DEFINE_SPINLOCK(alarm_lock);
108 #define NUM_PORTS (GPIO_MINOR_LAST+1)
109 #define GIO_REG_RD_ADDR(reg) \
110 (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
111 #define GIO_REG_WR_ADDR(reg) \
112 (volatile unsigned long *)(regi_gio + REG_WR_ADDR_gio_##reg)
113 unsigned long led_dummy;
114 unsigned long port_d_dummy; /* Only input on Artpec-3 */
115 unsigned long port_e_dummy; /* Non existent on Artpec-3 */
116 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
117 static unsigned long virtual_dummy;
118 static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
119 static unsigned short cached_virtual_gpio_read;
122 static volatile unsigned long *data_out[NUM_PORTS] = {
123 GIO_REG_WR_ADDR(rw_pa_dout),
124 GIO_REG_WR_ADDR(rw_pb_dout),
126 GIO_REG_WR_ADDR(rw_pc_dout),
128 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
134 static volatile unsigned long *data_in[NUM_PORTS] = {
135 GIO_REG_RD_ADDR(r_pa_din),
136 GIO_REG_RD_ADDR(r_pb_din),
138 GIO_REG_RD_ADDR(r_pc_din),
139 GIO_REG_RD_ADDR(r_pd_din),
140 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
146 static unsigned long changeable_dir[NUM_PORTS] = {
147 CONFIG_ETRAX_PA_CHANGEABLE_DIR,
148 CONFIG_ETRAX_PB_CHANGEABLE_DIR,
150 CONFIG_ETRAX_PC_CHANGEABLE_DIR,
152 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
154 CONFIG_ETRAX_PV_CHANGEABLE_DIR,
158 static unsigned long changeable_bits[NUM_PORTS] = {
159 CONFIG_ETRAX_PA_CHANGEABLE_BITS,
160 CONFIG_ETRAX_PB_CHANGEABLE_BITS,
162 CONFIG_ETRAX_PC_CHANGEABLE_BITS,
164 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
166 CONFIG_ETRAX_PV_CHANGEABLE_BITS,
170 static volatile unsigned long *dir_oe[NUM_PORTS] = {
171 GIO_REG_WR_ADDR(rw_pa_oe),
172 GIO_REG_WR_ADDR(rw_pb_oe),
174 GIO_REG_WR_ADDR(rw_pc_oe),
176 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
183 gpio_set_alarm(struct gpio_private *priv)
191 local_irq_save(flags);
192 intr_cfg = REG_RD_INT(gio, regi_gio, rw_intr_cfg);
193 pins = REG_RD_INT(gio, regi_gio, rw_intr_pins);
194 mask = REG_RD_INT(gio, regi_gio, rw_intr_mask) & I2C_INTERRUPT_BITS;
196 for (bit = 0; bit < 32; bit++) {
199 if (priv->minor < GPIO_MINOR_LEDS)
200 pin += priv->minor * 4;
202 pin += (priv->minor - 1) * 4;
204 if (priv->highalarm & (1<<bit)) {
205 intr_cfg |= (regk_gio_hi << (intr * 3));
207 wanted_interrupts = mask & 0xff;
208 pins |= pin << (intr * 4);
209 } else if (priv->lowalarm & (1<<bit)) {
210 intr_cfg |= (regk_gio_lo << (intr * 3));
212 wanted_interrupts = mask & 0xff;
213 pins |= pin << (intr * 4);
217 REG_WR_INT(gio, regi_gio, rw_intr_cfg, intr_cfg);
218 REG_WR_INT(gio, regi_gio, rw_intr_pins, pins);
219 REG_WR_INT(gio, regi_gio, rw_intr_mask, mask);
221 local_irq_restore(flags);
225 gpio_poll(struct file *file, struct poll_table_struct *wait)
227 unsigned int mask = 0;
228 struct gpio_private *priv = (struct gpio_private *)file->private_data;
232 if (priv->minor >= GPIO_MINOR_PWM0 &&
233 priv->minor <= GPIO_MINOR_LAST_PWM)
236 poll_wait(file, &priv->alarm_wq, wait);
237 if (priv->minor <= GPIO_MINOR_D) {
238 data = *data_in[priv->minor];
239 REG_WR_INT(gio, regi_gio, rw_ack_intr, wanted_interrupts);
240 tmp = REG_RD_INT(gio, regi_gio, rw_intr_mask);
241 tmp &= I2C_INTERRUPT_BITS;
242 tmp |= wanted_interrupts;
243 REG_WR_INT(gio, regi_gio, rw_intr_mask, tmp);
247 if ((data & priv->highalarm) || (~data & priv->lowalarm))
248 mask = POLLIN|POLLRDNORM;
250 DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
255 gpio_interrupt(int irq, void *dev_id)
257 reg_gio_rw_intr_mask intr_mask;
258 reg_gio_r_masked_intr masked_intr;
259 reg_gio_rw_ack_intr ack_intr;
262 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
263 unsigned char enable_gpiov_ack = 0;
266 /* Find what PA interrupts are active */
267 masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
268 tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
270 /* Find those that we have enabled */
271 spin_lock(&alarm_lock);
272 tmp &= wanted_interrupts;
273 spin_unlock(&alarm_lock);
275 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
276 /* Something changed on virtual GPIO. Interrupt is acked by
277 * reading the device.
279 if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
280 i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
281 sizeof(cached_virtual_gpio_read));
282 enable_gpiov_ack = 1;
287 ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
288 REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
290 /* Disable those interrupts.. */
291 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
292 tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
294 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
295 /* Do not disable interrupt on virtual GPIO. Changes on virtual
296 * pins are only noticed by an interrupt.
298 if (enable_gpiov_ack)
299 tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
301 intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
302 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
304 return IRQ_RETVAL(tmp);
308 static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
311 struct gpio_private *priv = (struct gpio_private *)file->private_data;
312 unsigned char data, clk_mask, data_mask, write_msb;
314 unsigned long shadow;
315 volatile unsigned long *port;
316 ssize_t retval = count;
317 /* Only bits 0-7 may be used for write operations but allow all
318 devices except leds... */
319 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
320 if (priv->minor == GPIO_MINOR_V)
323 if (priv->minor == GPIO_MINOR_LEDS)
326 if (priv->minor >= GPIO_MINOR_PWM0 &&
327 priv->minor <= GPIO_MINOR_LAST_PWM)
330 if (!access_ok(VERIFY_READ, buf, count))
333 clk_mask = priv->clk_mask;
334 data_mask = priv->data_mask;
335 /* It must have been configured using the IO_CFG_WRITE_MODE */
336 /* Perhaps a better error code? */
337 if (clk_mask == 0 || data_mask == 0)
340 write_msb = priv->write_msb;
341 D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
343 count, data_mask, clk_mask, write_msb));
344 port = data_out[priv->minor];
349 if (priv->write_msb) {
350 for (i = 7; i >= 0; i--) {
351 local_irq_save(flags);
353 *port = shadow &= ~clk_mask;
355 *port = shadow |= data_mask;
357 *port = shadow &= ~data_mask;
358 /* For FPGA: min 5.0ns (DCC) before CCLK high */
359 *port = shadow |= clk_mask;
360 local_irq_restore(flags);
363 for (i = 0; i <= 7; i++) {
364 local_irq_save(flags);
366 *port = shadow &= ~clk_mask;
368 *port = shadow |= data_mask;
370 *port = shadow &= ~data_mask;
371 /* For FPGA: min 5.0ns (DCC) before CCLK high */
372 *port = shadow |= clk_mask;
373 local_irq_restore(flags);
381 gpio_open(struct inode *inode, struct file *filp)
383 struct gpio_private *priv;
384 int p = iminor(inode);
386 if (p > GPIO_MINOR_LAST_PWM ||
387 (p > GPIO_MINOR_LAST && p < GPIO_MINOR_PWM0))
390 priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
394 memset(priv, 0, sizeof(*priv));
397 filp->private_data = (void *)priv;
399 /* initialize the io/alarm struct, not for PWM ports though */
400 if (p <= GPIO_MINOR_LAST) {
407 init_waitqueue_head(&priv->alarm_wq);
409 /* link it into our alarmlist */
410 spin_lock_irq(&alarm_lock);
411 priv->next = alarmlist;
413 spin_unlock_irq(&alarm_lock);
420 gpio_release(struct inode *inode, struct file *filp)
422 struct gpio_private *p;
423 struct gpio_private *todel;
424 /* local copies while updating them: */
425 unsigned long a_high, a_low;
427 /* prepare to free private structure */
428 todel = (struct gpio_private *)filp->private_data;
430 /* unlink from alarmlist - only for non-PWM ports though */
431 if (todel->minor <= GPIO_MINOR_LAST) {
432 spin_lock_irq(&alarm_lock);
436 alarmlist = todel->next;
438 while (p->next != todel)
440 p->next = todel->next;
443 /* Check if there are still any alarms set */
448 if (p->minor == GPIO_MINOR_A) {
449 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
450 p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
452 a_high |= p->highalarm;
453 a_low |= p->lowalarm;
459 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
460 /* Variable 'a_low' needs to be set here again
461 * to ensure that interrupt for virtual GPIO is handled.
463 a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
466 spin_unlock_irq(&alarm_lock);
473 /* Main device API. ioctl's to read/set/clear bits, as well as to
474 * set alarms to wait for using a subsequent select().
477 inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
479 /* Set direction 0=unchanged 1=input,
480 * return mask with 1=input
483 unsigned long dir_shadow;
485 local_irq_save(flags);
486 dir_shadow = *dir_oe[priv->minor];
487 dir_shadow &= ~(arg & changeable_dir[priv->minor]);
488 *dir_oe[priv->minor] = dir_shadow;
489 local_irq_restore(flags);
491 if (priv->minor == GPIO_MINOR_C)
492 dir_shadow ^= 0xFFFF; /* Only 16 bits */
493 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
494 else if (priv->minor == GPIO_MINOR_V)
495 dir_shadow ^= 0xFFFF; /* Only 16 bits */
498 dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */
504 inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
507 unsigned long dir_shadow;
509 local_irq_save(flags);
510 dir_shadow = *dir_oe[priv->minor];
511 dir_shadow |= (arg & changeable_dir[priv->minor]);
512 *dir_oe[priv->minor] = dir_shadow;
513 local_irq_restore(flags);
515 } /* setget_output */
518 gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
521 gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, unsigned long arg);
524 gpio_ioctl(struct inode *inode, struct file *file,
525 unsigned int cmd, unsigned long arg)
529 unsigned long shadow;
530 struct gpio_private *priv = (struct gpio_private *)file->private_data;
532 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
535 /* Check for special ioctl handlers first */
537 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
538 if (priv->minor == GPIO_MINOR_V)
539 return virtual_gpio_ioctl(file, cmd, arg);
542 if (priv->minor == GPIO_MINOR_LEDS)
543 return gpio_leds_ioctl(cmd, arg);
545 if (priv->minor >= GPIO_MINOR_PWM0 &&
546 priv->minor <= GPIO_MINOR_LAST_PWM)
547 return gpio_pwm_ioctl(priv, cmd, arg);
549 switch (_IOC_NR(cmd)) {
550 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
552 return *data_in[priv->minor];
555 local_irq_save(flags);
556 /* Set changeable bits with a 1 in arg. */
557 shadow = *data_out[priv->minor];
558 shadow |= (arg & changeable_bits[priv->minor]);
559 *data_out[priv->minor] = shadow;
560 local_irq_restore(flags);
563 local_irq_save(flags);
564 /* Clear changeable bits with a 1 in arg. */
565 shadow = *data_out[priv->minor];
566 shadow &= ~(arg & changeable_bits[priv->minor]);
567 *data_out[priv->minor] = shadow;
568 local_irq_restore(flags);
571 /* Set alarm when bits with 1 in arg go high. */
572 priv->highalarm |= arg;
573 gpio_set_alarm(priv);
576 /* Set alarm when bits with 1 in arg go low. */
577 priv->lowalarm |= arg;
578 gpio_set_alarm(priv);
581 /* Clear alarm for bits with 1 in arg. */
582 priv->highalarm &= ~arg;
583 priv->lowalarm &= ~arg;
584 gpio_set_alarm(priv);
586 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
587 /* Read direction 0=input 1=output */
588 return *dir_oe[priv->minor];
589 case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
590 /* Set direction 0=unchanged 1=input,
591 * return mask with 1=input
593 return setget_input(priv, arg);
595 case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
596 /* Set direction 0=unchanged 1=output,
597 * return mask with 1=output
599 return setget_output(priv, arg);
601 case IO_CFG_WRITE_MODE:
603 unsigned long dir_shadow;
604 dir_shadow = *dir_oe[priv->minor];
606 priv->clk_mask = arg & 0xFF;
607 priv->data_mask = (arg >> 8) & 0xFF;
608 priv->write_msb = (arg >> 16) & 0x01;
609 /* Check if we're allowed to change the bits and
610 * the direction is correct
612 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
613 (priv->data_mask & changeable_bits[priv->minor]) &&
614 (priv->clk_mask & dir_shadow) &&
615 (priv->data_mask & dir_shadow))) {
623 /* *arg is result of reading the input pins */
624 val = *data_in[priv->minor];
625 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
629 case IO_READ_OUTBITS:
630 /* *arg is result of reading the output shadow */
631 val = *data_out[priv->minor];
632 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
635 case IO_SETGET_INPUT:
636 /* bits set in *arg is set to input,
637 * *arg updated with current input pins.
639 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
641 val = setget_input(priv, val);
642 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
645 case IO_SETGET_OUTPUT:
646 /* bits set in *arg is set to output,
647 * *arg updated with current output pins.
649 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
651 val = setget_output(priv, val);
652 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
662 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
664 virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
668 unsigned short shadow;
669 struct gpio_private *priv = (struct gpio_private *)file->private_data;
671 switch (_IOC_NR(cmd)) {
673 local_irq_save(flags);
674 /* Set changeable bits with a 1 in arg. */
675 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
676 shadow |= ~*dir_oe[priv->minor];
677 shadow |= (arg & changeable_bits[priv->minor]);
678 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
679 local_irq_restore(flags);
682 local_irq_save(flags);
683 /* Clear changeable bits with a 1 in arg. */
684 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
685 shadow |= ~*dir_oe[priv->minor];
686 shadow &= ~(arg & changeable_bits[priv->minor]);
687 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
688 local_irq_restore(flags);
691 /* Set alarm when bits with 1 in arg go high. */
692 priv->highalarm |= arg;
695 /* Set alarm when bits with 1 in arg go low. */
696 priv->lowalarm |= arg;
699 /* Clear alarm for bits with 1 in arg. */
700 priv->highalarm &= ~arg;
701 priv->lowalarm &= ~arg;
703 case IO_CFG_WRITE_MODE:
705 unsigned long dir_shadow;
706 dir_shadow = *dir_oe[priv->minor];
708 priv->clk_mask = arg & 0xFF;
709 priv->data_mask = (arg >> 8) & 0xFF;
710 priv->write_msb = (arg >> 16) & 0x01;
711 /* Check if we're allowed to change the bits and
712 * the direction is correct
714 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
715 (priv->data_mask & changeable_bits[priv->minor]) &&
716 (priv->clk_mask & dir_shadow) &&
717 (priv->data_mask & dir_shadow))) {
725 /* *arg is result of reading the input pins */
726 val = cached_virtual_gpio_read;
727 val &= ~*dir_oe[priv->minor];
728 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
732 case IO_READ_OUTBITS:
733 /* *arg is result of reading the output shadow */
734 i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
735 val &= *dir_oe[priv->minor];
736 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
739 case IO_SETGET_INPUT:
741 /* bits set in *arg is set to input,
742 * *arg updated with current input pins.
744 unsigned short input_mask = ~*dir_oe[priv->minor];
745 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
747 val = setget_input(priv, val);
748 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
750 if ((input_mask & val) != input_mask) {
751 /* Input pins changed. All ports desired as input
752 * should be set to logic 1.
754 unsigned short change = input_mask ^ val;
755 i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
759 i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
764 case IO_SETGET_OUTPUT:
765 /* bits set in *arg is set to output,
766 * *arg updated with current output pins.
768 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
770 val = setget_output(priv, val);
771 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
779 #endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
782 gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
787 switch (_IOC_NR(cmd)) {
788 case IO_LEDACTIVE_SET:
789 green = ((unsigned char) arg) & 1;
790 red = (((unsigned char) arg) >> 1) & 1;
791 CRIS_LED_ACTIVE_SET_G(green);
792 CRIS_LED_ACTIVE_SET_R(red);
802 static int gpio_pwm_set_mode(unsigned long arg, int pwm_port)
804 int pinmux_pwm = pinmux_pwm0 + pwm_port;
806 reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = {
808 .ccd_override = regk_gio_no,
813 if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode))
815 rw_pwm_ctrl.mode = mode;
817 allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm);
819 allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm);
822 REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) +
823 12 * pwm_port, rw_pwm_ctrl);
827 static int gpio_pwm_set_period(unsigned long arg, int pwm_port)
829 struct io_pwm_set_period periods;
830 reg_gio_rw_pwm0_var rw_pwm_widths;
832 if (copy_from_user(&periods, (struct io_pwm_set_period *) arg,
835 if (periods.lo > 8191 || periods.hi > 8191)
837 rw_pwm_widths.lo = periods.lo;
838 rw_pwm_widths.hi = periods.hi;
839 REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) +
840 12 * pwm_port, rw_pwm_widths);
844 static int gpio_pwm_set_duty(unsigned long arg, int pwm_port)
847 reg_gio_rw_pwm0_data rw_pwm_duty;
849 if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty))
853 rw_pwm_duty.data = duty;
854 REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) +
855 12 * pwm_port, rw_pwm_duty);
860 gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, unsigned long arg)
862 int pwm_port = priv->minor - GPIO_MINOR_PWM0;
864 switch (_IOC_NR(cmd)) {
865 case IO_PWM_SET_MODE:
866 return gpio_pwm_set_mode(arg, pwm_port);
867 case IO_PWM_SET_PERIOD:
868 return gpio_pwm_set_period(arg, pwm_port);
869 case IO_PWM_SET_DUTY:
870 return gpio_pwm_set_duty(arg, pwm_port);
877 struct file_operations gpio_fops = {
878 .owner = THIS_MODULE,
883 .release = gpio_release,
886 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
888 virtual_gpio_init(void)
890 reg_gio_rw_intr_cfg intr_cfg;
891 reg_gio_rw_intr_mask intr_mask;
892 unsigned short shadow;
894 shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
895 shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
896 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
898 /* Set interrupt mask and on what state the interrupt shall trigger.
899 * For virtual gpio the interrupt shall trigger on logic '0'.
901 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
902 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
904 switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
906 intr_cfg.pa0 = regk_gio_lo;
907 intr_mask.pa0 = regk_gio_yes;
910 intr_cfg.pa1 = regk_gio_lo;
911 intr_mask.pa1 = regk_gio_yes;
914 intr_cfg.pa2 = regk_gio_lo;
915 intr_mask.pa2 = regk_gio_yes;
918 intr_cfg.pa3 = regk_gio_lo;
919 intr_mask.pa3 = regk_gio_yes;
922 intr_cfg.pa4 = regk_gio_lo;
923 intr_mask.pa4 = regk_gio_yes;
926 intr_cfg.pa5 = regk_gio_lo;
927 intr_mask.pa5 = regk_gio_yes;
930 intr_cfg.pa6 = regk_gio_lo;
931 intr_mask.pa6 = regk_gio_yes;
934 intr_cfg.pa7 = regk_gio_lo;
935 intr_mask.pa7 = regk_gio_yes;
939 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
940 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
944 /* main driver initialization routine, called from mem.c */
951 /* do the formalities */
953 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
955 printk(KERN_ERR "gpio: couldn't get a major number.\n");
960 CRIS_LED_NETWORK_GRP0_SET(0);
961 CRIS_LED_NETWORK_GRP1_SET(0);
962 CRIS_LED_ACTIVE_SET(0);
963 CRIS_LED_DISK_READ(0);
964 CRIS_LED_DISK_WRITE(0);
966 printk(KERN_INFO "ETRAX FS GPIO driver v2.6, (c) 2003-2007 "
967 "Axis Communications AB\n");
968 if (request_irq(GIO_INTR_VECT, gpio_interrupt,
969 IRQF_SHARED | IRQF_DISABLED, "gpio", &alarmlist))
970 printk(KERN_ERR "err: irq for gpio\n");
972 /* No IRQs by default. */
973 REG_WR_INT(gio, regi_gio, rw_intr_pins, 0);
975 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
982 /* this makes sure that gpio_init is called during kernel boot */
984 module_init(gpio_init);