2 * Copyright (C) 2005-2012 Imagination Technologies Ltd.
4 * This file contains the architecture-dependant parts of system setup.
8 #include <linux/export.h>
9 #include <linux/bootmem.h>
10 #include <linux/console.h>
11 #include <linux/cpu.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
15 #include <linux/genhd.h>
16 #include <linux/init.h>
17 #include <linux/initrd.h>
18 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/memblock.h>
22 #include <linux/of_fdt.h>
23 #include <linux/of_platform.h>
24 #include <linux/pfn.h>
25 #include <linux/root_dev.h>
26 #include <linux/sched.h>
27 #include <linux/seq_file.h>
28 #include <linux/start_kernel.h>
29 #include <linux/string.h>
31 #include <asm/cachepart.h>
32 #include <asm/clock.h>
33 #include <asm/core_reg.h>
36 #include <asm/highmem.h>
37 #include <asm/hwthread.h>
38 #include <asm/l2cache.h>
39 #include <asm/mach/arch.h>
40 #include <asm/metag_mem.h>
41 #include <asm/metag_regs.h>
43 #include <asm/mmzone.h>
44 #include <asm/processor.h>
46 #include <asm/sections.h>
47 #include <asm/setup.h>
48 #include <asm/traps.h>
50 /* Priv protect as many registers as possible. */
51 #define DEFAULT_PRIV (TXPRIVEXT_COPRO_BITS | \
52 TXPRIVEXT_TXTRIGGER_BIT | \
53 TXPRIVEXT_TXGBLCREG_BIT | \
54 TXPRIVEXT_ILOCK_BIT | \
55 TXPRIVEXT_TXITACCYC_BIT | \
56 TXPRIVEXT_TXDIVTIME_BIT | \
57 TXPRIVEXT_TXAMAREGX_BIT | \
58 TXPRIVEXT_TXTIMERI_BIT | \
59 TXPRIVEXT_TXSTATUS_BIT | \
60 TXPRIVEXT_TXDISABLE_BIT)
62 /* Meta2 specific bits. */
63 #ifdef CONFIG_METAG_META12
66 #define META2_PRIV (TXPRIVEXT_TXTIMER_BIT | \
70 /* Unaligned access checking bits. */
71 #ifdef CONFIG_METAG_UNALIGNED
72 #define UNALIGNED_PRIV TXPRIVEXT_ALIGNREW_BIT
74 #define UNALIGNED_PRIV 0
77 #define PRIV_BITS (DEFAULT_PRIV | \
83 * 0x06000000-0x07ffffff Direct mapped region
84 * 0x05000000-0x05ffffff MMU table region (Meta1)
85 * 0x04400000-0x047fffff Cache flush region
86 * 0x84000000-0x87ffffff Core cache memory region (Meta2)
89 * 0x80000000-0x81ffffff Core code memory region (Meta2)
91 #ifdef CONFIG_METAG_META12
92 #define PRIVSYSR_BITS TXPRIVSYSR_ALL_BITS
94 #define PRIVSYSR_BITS (TXPRIVSYSR_ALL_BITS & ~TXPRIVSYSR_CORECODE_BIT)
97 /* Protect all 0x02xxxxxx and 0x048xxxxx. */
98 #define PIOREG_BITS 0xffffffff
101 * Protect all 0x04000xx0 (system events)
102 * except write combiner flush and write fence (system events 4 and 5).
104 #define PSYREG_BITS 0xfffffffb
107 extern char _heap_start[];
109 #ifdef CONFIG_METAG_BUILTIN_DTB
110 extern u32 __dtb_start[];
113 #ifdef CONFIG_DA_CONSOLE
114 /* Our early channel based console driver */
115 extern struct console dash_console;
118 struct machine_desc *machine_desc __initdata;
121 * Map a Linux CPU number to a hardware thread ID
122 * In SMP this will be setup with the correct mapping at startup; in UP this
123 * will map to the HW thread on which we are running.
125 u8 cpu_2_hwthread_id[NR_CPUS] __read_mostly = {
126 [0 ... NR_CPUS-1] = BAD_HWTHREAD_ID
128 EXPORT_SYMBOL_GPL(cpu_2_hwthread_id);
131 * Map a hardware thread ID to a Linux CPU number
132 * In SMP this will be fleshed out with the correct CPU ID for a particular
133 * hardware thread. In UP this will be initialised with the boot CPU ID.
135 u8 hwthread_id_2_cpu[4] __read_mostly = {
136 [0 ... 3] = BAD_CPU_ID
139 /* The relative offset of the MMU mapped memory (from ldlk or bootloader)
140 * to the real physical memory. This is needed as we have to use the
141 * physical addresses in the MMU tables (pte entries), and not the virtual
143 * This variable is used in the __pa() and __va() macros, and should
144 * probably only be used via them.
146 unsigned int meta_memoffset;
147 EXPORT_SYMBOL(meta_memoffset);
149 static char __initdata *original_cmd_line;
151 DEFINE_PER_CPU(PTBI, pTBI);
154 * Mapping are specified as "CPU_ID:HWTHREAD_ID", e.g.
156 * "hwthread_map=0:1,1:2,2:3,3:0"
158 * Linux CPU ID HWTHREAD_ID
159 * ---------------------------
165 static int __init parse_hwthread_map(char *p)
171 if (cpu < 0 || cpu > 9)
174 p++; /* skip semi-colon */
175 cpu_2_hwthread_id[cpu] = (*p++) - '0';
176 if (cpu_2_hwthread_id[cpu] >= 4)
178 hwthread_id_2_cpu[cpu_2_hwthread_id[cpu]] = cpu;
181 p++; /* skip comma */
186 pr_err("%s: hwthread_map cpu argument out of range\n", __func__);
189 pr_err("%s: hwthread_map thread argument out of range\n", __func__);
192 early_param("hwthread_map", parse_hwthread_map);
194 void __init dump_machine_table(void)
196 struct machine_desc *p;
199 pr_info("Available machine support:\n\tNAME\t\tCOMPATIBLE LIST\n");
200 for_each_machine_desc(p) {
201 pr_info("\t%s\t[", p->name);
202 for (compat = p->dt_compat; compat && *compat; ++compat)
203 printk(" '%s'", *compat);
207 pr_info("\nPlease check your kernel config and/or bootloader.\n");
209 hard_processor_halt(HALT_PANIC);
212 #ifdef CONFIG_METAG_HALT_ON_PANIC
213 static int metag_panic_event(struct notifier_block *this, unsigned long event,
216 hard_processor_halt(HALT_PANIC);
220 static struct notifier_block metag_panic_block = {
227 void __init setup_arch(char **cmdline_p)
229 unsigned long start_pfn;
230 unsigned long text_start = (unsigned long)(&_stext);
231 unsigned long cpu = smp_processor_id();
232 unsigned long heap_start, heap_end;
233 unsigned long start_pte;
241 #ifdef CONFIG_DA_CONSOLE
242 if (metag_da_enabled()) {
243 /* An early channel based console driver */
244 register_console(&dash_console);
245 add_preferred_console("ttyDA", 1, NULL);
249 /* try interpreting the argument as a device tree */
250 machine_desc = setup_machine_fdt(original_cmd_line);
251 /* if it doesn't look like a device tree it must be a command line */
253 #ifdef CONFIG_METAG_BUILTIN_DTB
254 /* try the embedded device tree */
255 machine_desc = setup_machine_fdt(__dtb_start);
257 panic("Invalid embedded device tree.");
259 /* use the default machine description */
260 machine_desc = default_machine_desc();
262 #ifndef CONFIG_CMDLINE_FORCE
263 /* append the bootloader cmdline to any builtin fdt cmdline */
264 if (boot_command_line[0] && original_cmd_line[0])
265 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
266 strlcat(boot_command_line, original_cmd_line,
270 setup_meta_clocks(machine_desc->clocks);
272 *cmdline_p = boot_command_line;
276 * Make sure we don't alias in dcache or icache
278 check_for_cache_aliasing(cpu);
281 #ifdef CONFIG_METAG_HALT_ON_PANIC
282 atomic_notifier_chain_register(&panic_notifier_list,
286 #ifdef CONFIG_DUMMY_CONSOLE
287 conswitchp = &dummy_con;
290 if (!(__core_reg_get(TXSTATUS) & TXSTATUS_PSTAT_BIT))
291 panic("Privilege must be enabled for this thread.");
293 _pTBI = __TBI(TBID_ISTAT_BIT);
295 per_cpu(pTBI, cpu) = _pTBI;
297 if (!per_cpu(pTBI, cpu))
298 panic("No TBI found!");
301 * Initialize all interrupt vectors to our copy of __TBIUnExpXXX,
302 * rather than the version from the bootloader. This makes call
303 * stacks easier to understand and may allow us to unmap the
304 * bootloader at some point.
306 for (i = 0; i <= TBID_SIGNUM_MAX; i++)
307 _pTBI->fnSigs[i] = __TBIUnExpXXX;
309 /* A Meta requirement is that the kernel is loaded (virtually)
310 * at the PAGE_OFFSET.
312 if (PAGE_OFFSET != text_start)
313 panic("Kernel not loaded at PAGE_OFFSET (%#x) but at %#lx.",
314 PAGE_OFFSET, text_start);
316 start_pte = mmu_read_second_level_page(text_start);
319 * Kernel pages should have the PRIV bit set by the bootloader.
321 if (!(start_pte & _PAGE_KERNEL))
322 panic("kernel pte does not have PRIV set");
325 * See __pa and __va in include/asm/page.h.
326 * This value is negative when running in local space but the
327 * calculations work anyway.
329 meta_memoffset = text_start - (start_pte & PAGE_MASK);
331 /* Now lets look at the heap space */
332 heap_id = (__TBIThreadId() & TBID_THREAD_BITS)
333 + TBID_SEG(0, TBID_SEGSCOPE_LOCAL, TBID_SEGTYPE_HEAP);
335 p_heap = __TBIFindSeg(NULL, heap_id);
338 panic("Could not find heap from TBI!");
340 /* The heap begins at the first full page after the kernel data. */
341 heap_start = (unsigned long) &_heap_start;
343 /* The heap ends at the end of the heap segment specified with
346 if (is_global_space(text_start)) {
347 pr_debug("WARNING: running in global space!\n");
348 heap_end = (unsigned long)p_heap->pGAddr + p_heap->Bytes;
350 heap_end = (unsigned long)p_heap->pLAddr + p_heap->Bytes;
353 ROOT_DEV = Root_RAM0;
355 /* init_mm is the mm struct used for the first task. It is then
356 * cloned for all other tasks spawned from that task.
358 * Note - we are using the virtual addresses here.
360 init_mm.start_code = (unsigned long)(&_stext);
361 init_mm.end_code = (unsigned long)(&_etext);
362 init_mm.end_data = (unsigned long)(&_edata);
363 init_mm.brk = (unsigned long)heap_start;
365 min_low_pfn = PFN_UP(__pa(text_start));
366 max_low_pfn = PFN_DOWN(__pa(heap_end));
368 pfn_base = min_low_pfn;
370 /* Round max_pfn up to a 4Mb boundary. The free_bootmem_node()
371 * call later makes sure to keep the rounded up pages marked reserved.
373 max_pfn = max_low_pfn + ((1 << MAX_ORDER) - 1);
374 max_pfn &= ~((1 << MAX_ORDER) - 1);
376 start_pfn = PFN_UP(__pa(heap_start));
378 if (min_low_pfn & ((1 << MAX_ORDER) - 1)) {
379 /* Theoretically, we could expand the space that the
380 * bootmem allocator covers - much as we do for the
381 * 'high' address, and then tell the bootmem system
382 * that the lowest chunk is 'not available'. Right
383 * now it is just much easier to constrain the
384 * user to always MAX_ORDER align their kernel space.
387 panic("Kernel must be %d byte aligned, currently at %#lx.",
388 1 << (MAX_ORDER + PAGE_SHIFT),
389 min_low_pfn << PAGE_SHIFT);
392 #ifdef CONFIG_HIGHMEM
393 highstart_pfn = highend_pfn = max_pfn;
394 high_memory = (void *) __va(PFN_PHYS(highstart_pfn));
396 high_memory = (void *)__va(PFN_PHYS(max_pfn));
399 paging_init(heap_end);
403 /* Setup the boot cpu's mapping. The rest will be setup below. */
404 cpu_2_hwthread_id[smp_processor_id()] = hard_processor_id();
405 hwthread_id_2_cpu[hard_processor_id()] = smp_processor_id();
407 /* Copy device tree blob into non-init memory before unflattening */
409 unflatten_device_tree();
415 if (machine_desc->init_early)
416 machine_desc->init_early();
419 static int __init customize_machine(void)
421 /* customizes platform devices, or adds new ones */
422 if (machine_desc->init_machine)
423 machine_desc->init_machine();
425 of_platform_populate(NULL, of_default_bus_match_table, NULL,
429 arch_initcall(customize_machine);
431 static int __init init_machine_late(void)
433 if (machine_desc->init_late)
434 machine_desc->init_late();
437 late_initcall(init_machine_late);
439 #ifdef CONFIG_PROC_FS
441 * Get CPU information for use by the procfs.
443 static const char *get_cpu_capabilities(unsigned int txenable)
445 #ifdef CONFIG_METAG_META21
446 /* See CORE_ID in META HTP.GP TRM - Architecture Overview 2.1.238 */
447 int coreid = metag_in32(METAC_CORE_ID);
448 unsigned int dsp_type = (coreid >> 3) & 7;
449 unsigned int fpu_type = (coreid >> 7) & 3;
451 switch (dsp_type | fpu_type << 3) {
452 case (0x00): return "EDSP";
453 case (0x01): return "DSP";
454 case (0x08): return "EDSP+LFPU";
455 case (0x09): return "DSP+LFPU";
456 case (0x10): return "EDSP+FPU";
457 case (0x11): return "DSP+FPU";
462 if (!(txenable & TXENABLE_CLASS_BITS))
469 static int show_cpuinfo(struct seq_file *m, void *v)
472 unsigned int txenable, thread_id, major, minor;
473 unsigned long clockfreq = get_coreclock();
481 txenable = __core_reg_get(TXENABLE);
482 major = (txenable & TXENABLE_MAJOR_REV_BITS) >> TXENABLE_MAJOR_REV_S;
483 minor = (txenable & TXENABLE_MINOR_REV_BITS) >> TXENABLE_MINOR_REV_S;
484 thread_id = (txenable >> 8) & 0x3;
487 for_each_online_cpu(i) {
488 lpj = per_cpu(cpu_data, i).loops_per_jiffy;
489 txenable = core_reg_read(TXUCT_ID, TXENABLE_REGNUM,
490 cpu_2_hwthread_id[i]);
492 seq_printf(m, "CPU:\t\t%s %d.%d (thread %d)\n"
493 "Clocking:\t%lu.%1luMHz\n"
494 "BogoMips:\t%lu.%02lu\n"
495 "Calibration:\t%lu loops\n"
496 "Capabilities:\t%s\n\n",
497 cpu, major, minor, i,
498 clockfreq / 1000000, (clockfreq / 100000) % 10,
499 lpj / (500000 / HZ), (lpj / (5000 / HZ)) % 100,
501 get_cpu_capabilities(txenable));
504 seq_printf(m, "CPU:\t\t%s %d.%d (thread %d)\n"
505 "Clocking:\t%lu.%1luMHz\n"
506 "BogoMips:\t%lu.%02lu\n"
507 "Calibration:\t%lu loops\n"
508 "Capabilities:\t%s\n",
509 cpu, major, minor, thread_id,
510 clockfreq / 1000000, (clockfreq / 100000) % 10,
511 loops_per_jiffy / (500000 / HZ),
512 (loops_per_jiffy / (5000 / HZ)) % 100,
514 get_cpu_capabilities(txenable));
515 #endif /* CONFIG_SMP */
517 #ifdef CONFIG_METAG_L2C
518 if (meta_l2c_is_present()) {
519 seq_printf(m, "L2 cache:\t%s\n"
520 "L2 cache size:\t%d KB\n",
521 meta_l2c_is_enabled() ? "enabled" : "disabled",
522 meta_l2c_size() >> 10);
528 static void *c_start(struct seq_file *m, loff_t *pos)
530 return (void *)(*pos == 0);
532 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
536 static void c_stop(struct seq_file *m, void *v)
539 const struct seq_operations cpuinfo_op = {
543 .show = show_cpuinfo,
545 #endif /* CONFIG_PROC_FS */
547 void __init metag_start_kernel(char *args)
549 /* Zero the timer register so timestamps are from the point at
550 * which the kernel started running.
552 __core_reg_set(TXTIMER, 0);
555 memset(__bss_start, 0,
556 (unsigned long)__bss_stop - (unsigned long)__bss_start);
558 /* Remember where these are for use in setup_arch */
559 original_cmd_line = args;
561 current_thread_info()->cpu = hard_processor_id();
567 * setup_priv() - Set up privilege protection registers.
569 * Set up privilege protection registers such as TXPRIVEXT to prevent userland
570 * from touching our precious registers and sensitive memory areas.
572 void setup_priv(void)
574 unsigned int offset = hard_processor_id() << TXPRIVREG_STRIDE_S;
576 __core_reg_set(TXPRIVEXT, PRIV_BITS);
578 metag_out32(PRIVSYSR_BITS, T0PRIVSYSR + offset);
579 metag_out32(PIOREG_BITS, T0PIOREG + offset);
580 metag_out32(PSYREG_BITS, T0PSYREG + offset);
583 PTBI pTBI_get(unsigned int cpu)
585 return per_cpu(pTBI, cpu);
587 EXPORT_SYMBOL(pTBI_get);
589 #if defined(CONFIG_METAG_DSP) && defined(CONFIG_METAG_FPU)
590 static char capabilities[] = "dsp fpu";
591 #elif defined(CONFIG_METAG_DSP)
592 static char capabilities[] = "dsp";
593 #elif defined(CONFIG_METAG_FPU)
594 static char capabilities[] = "fpu";
596 static char capabilities[] = "";
599 static struct ctl_table caps_kern_table[] = {
601 .procname = "capabilities",
602 .data = capabilities,
603 .maxlen = sizeof(capabilities),
605 .proc_handler = proc_dostring,
610 static struct ctl_table caps_root_table[] = {
612 .procname = "kernel",
614 .child = caps_kern_table,
619 static int __init capabilities_register_sysctl(void)
621 struct ctl_table_header *caps_table_header;
623 caps_table_header = register_sysctl_table(caps_root_table);
624 if (!caps_table_header) {
625 pr_err("Unable to register CAPABILITIES sysctl\n");
632 core_initcall(capabilities_register_sysctl);