arch/mips/cavium-octeon/smp.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
   7  */
   8 #include <linux/cpu.h>
   9 #include <linux/delay.h>
  10 #include <linux/smp.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/sched.h>
  14 #include <linux/module.h>
  15
  16 #include <asm/mmu_context.h>
  17 #include <asm/time.h>
  18 #include <asm/setup.h>
  19
  20 #include <asm/octeon/octeon.h>
  21
  22 #include "octeon_boot.h"
  23
  24 volatile unsigned long octeon_processor_boot = 0xff;
  25 volatile unsigned long octeon_processor_sp;
  26 volatile unsigned long octeon_processor_gp;
  27
  28 #ifdef CONFIG_HOTPLUG_CPU
  29 uint64_t octeon_bootloader_entry_addr;
  30 EXPORT_SYMBOL(octeon_bootloader_entry_addr);
  31 #endif
  32
  33 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
  34 {
  35         const int coreid = cvmx_get_core_num();
  36         uint64_t action;
  37
  38         /* Load the mailbox register to figure out what we're supposed to do */
  39         action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
  40
  41         /* Clear the mailbox to clear the interrupt */
  42         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
  43
  44         if (action & SMP_CALL_FUNCTION)
  45                 smp_call_function_interrupt();
  46         if (action & SMP_RESCHEDULE_YOURSELF)
  47                 scheduler_ipi();
  48
  49         /* Check if we've been told to flush the icache */
  50         if (action & SMP_ICACHE_FLUSH)
  51                 asm volatile ("synci 0($0)\n");
  52         return IRQ_HANDLED;
  53 }
  54
  55 /**
  56  * Cause the function described by call_data to be executed on the passed
  57  * cpu.  When the function has finished, increment the finished field of
  58  * call_data.
  59  */
  60 void octeon_send_ipi_single(int cpu, unsigned int action)
  61 {
  62         int coreid = cpu_logical_map(cpu);
  63         /*
  64         pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
  65                coreid, action);
  66         */
  67         cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
  68 }
  69
  70 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
  71                                         unsigned int action)
  72 {
  73         unsigned int i;
  74
  75         for_each_cpu_mask(i, *mask)
  76                 octeon_send_ipi_single(i, action);
  77 }
  78
  79 /**
  80  * Detect available CPUs, populate cpu_possible_mask
  81  */
  82 static void octeon_smp_hotplug_setup(void)
  83 {
  84 #ifdef CONFIG_HOTPLUG_CPU
  85         struct linux_app_boot_info *labi;
  86
  87         if (!setup_max_cpus)
  88                 return;
  89
  90         labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
  91         if (labi->labi_signature != LABI_SIGNATURE) {
  92                 pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
  93                 return;
  94         }
  95
  96         octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
  97 #endif
  98 }
  99
 100 static void octeon_smp_setup(void)
 101 {
 102         const int coreid = cvmx_get_core_num();
 103         int cpus;
 104         int id;
 105         int core_mask = octeon_get_boot_coremask();
 106 #ifdef CONFIG_HOTPLUG_CPU
 107         unsigned int num_cores = cvmx_octeon_num_cores();
 108 #endif
 109
 110         /* The present CPUs are initially just the boot cpu (CPU 0). */
 111         for (id = 0; id < NR_CPUS; id++) {
 112                 set_cpu_possible(id, id == 0);
 113                 set_cpu_present(id, id == 0);
 114         }
 115
 116         __cpu_number_map[coreid] = 0;
 117         __cpu_logical_map[0] = coreid;
 118
 119         /* The present CPUs get the lowest CPU numbers. */
 120         cpus = 1;
 121         for (id = 0; id < NR_CPUS; id++) {
 122                 if ((id != coreid) && (core_mask & (1 << id))) {
 123                         set_cpu_possible(cpus, true);
 124                         set_cpu_present(cpus, true);
 125                         __cpu_number_map[id] = cpus;
 126                         __cpu_logical_map[cpus] = id;
 127                         cpus++;
 128                 }
 129         }
 130
 131 #ifdef CONFIG_HOTPLUG_CPU
 132         /*
 133          * The possible CPUs are all those present on the chip.  We
 134          * will assign CPU numbers for possible cores as well.  Cores
 135          * are always consecutively numberd from 0.
 136          */
 137         for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
 138                      id < num_cores && id < NR_CPUS; id++) {
 139                 if (!(core_mask & (1 << id))) {
 140                         set_cpu_possible(cpus, true);
 141                         __cpu_number_map[id] = cpus;
 142                         __cpu_logical_map[cpus] = id;
 143                         cpus++;
 144                 }
 145         }
 146 #endif
 147
 148         octeon_smp_hotplug_setup();
 149 }
 150
 151 /**
 152  * Firmware CPU startup hook
 153  *
 154  */
 155 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
 156 {
 157         int count;
 158
 159         pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
 160                 cpu_logical_map(cpu));
 161
 162         octeon_processor_sp = __KSTK_TOS(idle);
 163         octeon_processor_gp = (unsigned long)(task_thread_info(idle));
 164         octeon_processor_boot = cpu_logical_map(cpu);
 165         mb();
 166
 167         count = 10000;
 168         while (octeon_processor_sp && count) {
 169                 /* Waiting for processor to get the SP and GP */
 170                 udelay(1);
 171                 count--;
 172         }
 173         if (count == 0)
 174                 pr_err("Secondary boot timeout\n");
 175 }
 176
 177 /**
 178  * After we've done initial boot, this function is called to allow the
 179  * board code to clean up state, if needed
 180  */
 181 static void octeon_init_secondary(void)
 182 {
 183         unsigned int sr;
 184
 185         sr = set_c0_status(ST0_BEV);
 186         write_c0_ebase((u32)ebase);
 187         write_c0_status(sr);
 188
 189         octeon_check_cpu_bist();
 190         octeon_init_cvmcount();
 191
 192         octeon_irq_setup_secondary();
 193 }
 194
 195 /**
 196  * Callout to firmware before smp_init
 197  *
 198  */
 199 void octeon_prepare_cpus(unsigned int max_cpus)
 200 {
 201         /*
 202          * Only the low order mailbox bits are used for IPIs, leave
 203          * the other bits alone.
 204          */
 205         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
 206         if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
 207                         IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
 208                         mailbox_interrupt)) {
 209                 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
 210         }
 211 }
 212
 213 /**
 214  * Last chance for the board code to finish SMP initialization before
 215  * the CPU is "online".
 216  */
 217 static void octeon_smp_finish(void)
 218 {
 219         octeon_user_io_init();
 220
 221         /* to generate the first CPU timer interrupt */
 222         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 223         local_irq_enable();
 224 }
 225
 226 #ifdef CONFIG_HOTPLUG_CPU
 227
 228 /* State of each CPU. */
 229 DEFINE_PER_CPU(int, cpu_state);
 230
 231 static int octeon_cpu_disable(void)
 232 {
 233         unsigned int cpu = smp_processor_id();
 234
 235         if (cpu == 0)
 236                 return -EBUSY;
 237
 238         if (!octeon_bootloader_entry_addr)
 239                 return -ENOTSUPP;
 240
 241         set_cpu_online(cpu, false);
 242         cpu_clear(cpu, cpu_callin_map);
 243         local_irq_disable();
 244         octeon_fixup_irqs();
 245         local_irq_enable();
 246
 247         flush_cache_all();
 248         local_flush_tlb_all();
 249
 250         return 0;
 251 }
 252
 253 static void octeon_cpu_die(unsigned int cpu)
 254 {
 255         int coreid = cpu_logical_map(cpu);
 256         uint32_t mask, new_mask;
 257         const struct cvmx_bootmem_named_block_desc *block_desc;
 258
 259         while (per_cpu(cpu_state, cpu) != CPU_DEAD)
 260                 cpu_relax();
 261
 262         /*
 263          * This is a bit complicated strategics of getting/settig available
 264          * cores mask, copied from bootloader
 265          */
 266
 267         mask = 1 << coreid;
 268         /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
 269         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 270
 271         if (!block_desc) {
 272                 struct linux_app_boot_info *labi;
 273
 274                 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
 275
 276                 labi->avail_coremask |= mask;
 277                 new_mask = labi->avail_coremask;
 278         } else {                       /* alternative, already initialized */
 279                 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
 280                                                                AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
 281                 *p |= mask;
 282                 new_mask = *p;
 283         }
 284
 285         pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
 286         mb();
 287         cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
 288         cvmx_write_csr(CVMX_CIU_PP_RST, 0);
 289 }
 290
 291 void play_dead(void)
 292 {
 293         int cpu = cpu_number_map(cvmx_get_core_num());
 294
 295         idle_task_exit();
 296         octeon_processor_boot = 0xff;
 297         per_cpu(cpu_state, cpu) = CPU_DEAD;
 298
 299         mb();
 300
 301         while (1)       /* core will be reset here */
 302                 ;
 303 }
 304
 305 extern void kernel_entry(unsigned long arg1, ...);
 306
 307 static void start_after_reset(void)
 308 {
 309         kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
 310 }
 311
 312 static int octeon_update_boot_vector(unsigned int cpu)
 313 {
 314
 315         int coreid = cpu_logical_map(cpu);
 316         uint32_t avail_coremask;
 317         const struct cvmx_bootmem_named_block_desc *block_desc;
 318         struct boot_init_vector *boot_vect =
 319                 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
 320
 321         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 322
 323         if (!block_desc) {
 324                 struct linux_app_boot_info *labi;
 325
 326                 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
 327
 328                 avail_coremask = labi->avail_coremask;
 329                 labi->avail_coremask &= ~(1 << coreid);
 330         } else {                       /* alternative, already initialized */
 331                 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
 332                         block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
 333         }
 334
 335         if (!(avail_coremask & (1 << coreid))) {
 336                 /* core not available, assume, that catched by simple-executive */
 337                 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
 338                 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
 339         }
 340
 341         boot_vect[coreid].app_start_func_addr =
 342                 (uint32_t) (unsigned long) start_after_reset;
 343         boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
 344
 345         mb();
 346
 347         cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
 348
 349         return 0;
 350 }
 351
 352 static int octeon_cpu_callback(struct notifier_block *nfb,
 353         unsigned long action, void *hcpu)
 354 {
 355         unsigned int cpu = (unsigned long)hcpu;
 356
 357         switch (action) {
 358         case CPU_UP_PREPARE:
 359                 octeon_update_boot_vector(cpu);
 360                 break;
 361         case CPU_ONLINE:
 362                 pr_info("Cpu %d online\n", cpu);
 363                 break;
 364         case CPU_DEAD:
 365                 break;
 366         }
 367
 368         return NOTIFY_OK;
 369 }
 370
 371 static int register_cavium_notifier(void)
 372 {
 373         hotcpu_notifier(octeon_cpu_callback, 0);
 374         return 0;
 375 }
 376 late_initcall(register_cavium_notifier);
 377
 378 #endif  /* CONFIG_HOTPLUG_CPU */
 379
 380 struct plat_smp_ops octeon_smp_ops = {
 381         .send_ipi_single        = octeon_send_ipi_single,
 382         .send_ipi_mask          = octeon_send_ipi_mask,
 383         .init_secondary         = octeon_init_secondary,
 384         .smp_finish             = octeon_smp_finish,
 385         .boot_secondary         = octeon_boot_secondary,
 386         .smp_setup              = octeon_smp_setup,
 387         .prepare_cpus           = octeon_prepare_cpus,
 388 #ifdef CONFIG_HOTPLUG_CPU
 389         .cpu_disable            = octeon_cpu_disable,
 390         .cpu_die                = octeon_cpu_die,
 391 #endif
 392 };