2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Chris Dearman (chris@mips.com)
7 * Copyright (C) 2007 Mips Technologies, Inc.
8 * Copyright (C) 2014 Imagination Technologies Ltd.
10 #ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
11 #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
14 * Prepare segments for EVA boot:
16 * This is in case the processor boots in legacy configuration
17 * (SI_EVAReset is de-asserted and CONFIG5.K == 0)
19 * On entry, t1 is loaded with CP0_CONFIG
21 * ========================= Mappings =============================
22 * Virtual memory Physical memory Mapping
23 * 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg)
24 * Flat 2GB physical memory
26 * 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0)
27 * 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1)
28 * 0xc0000000 - 0xdfffffff - MK (kseg2)
29 * 0xe0000000 - 0xffffffff - MK (kseg3)
32 * Lowmem is expanded to 2GB
36 * Get Config.K0 value and use it to program
37 * the segmentation registers
39 andi t1, 0x7 /* CCA */
43 li t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \
44 (0 << MIPS_SEGCFG_PA_SHIFT) | \
45 (1 << MIPS_SEGCFG_EU_SHIFT)) | \
46 (((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \
47 (0 << MIPS_SEGCFG_PA_SHIFT) | \
48 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
53 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
54 (0 << MIPS_SEGCFG_PA_SHIFT) | \
55 (2 << MIPS_SEGCFG_C_SHIFT) | \
56 (1 << MIPS_SEGCFG_EU_SHIFT)) | \
57 (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
58 (0 << MIPS_SEGCFG_PA_SHIFT) | \
59 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
64 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
65 (6 << MIPS_SEGCFG_PA_SHIFT) | \
66 (1 << MIPS_SEGCFG_EU_SHIFT)) | \
67 (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
68 (4 << MIPS_SEGCFG_PA_SHIFT) | \
69 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
75 li t2, 0x40000000 /* K bit */
82 .macro kernel_entry_setup
90 mfc0 t0, CP0_CONFIG, 1
92 mfc0 t0, CP0_CONFIG, 2
94 mfc0 t0, CP0_CONFIG, 3
95 sll t0, t0, 6 /* SC bit */
101 /* Assume we came from YAMON... */
102 PTR_LA v0, 0x9fc00534 /* YAMON print */
105 PTR_LA a1, nonsc_processor
108 PTR_LA v0, 0x9fc00520 /* YAMON exit */
117 .asciz "EVA kernel requires a MIPS core with Segment Control implemented\n"
119 #endif /* CONFIG_EVA */
124 * Do SMP slave processor setup necessary before we can safely execute C code.
126 .macro smp_slave_setup
135 #endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */