1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_SLI_DEFS_H__
29 #define __CVMX_SLI_DEFS_H__
31 #define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
32 #define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
33 #define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
34 #define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
35 #define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
36 #define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
37 #define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
38 #define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
39 #define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
40 #define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
41 #define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
42 #define CVMX_SLI_INT_SUM (0x0000000000000330ull)
43 #define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
44 #define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
45 #define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
46 #define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
47 #define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
48 #define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
49 #define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
50 #define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
51 #define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
52 #define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
53 #define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
54 #define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
55 #define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
56 #define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
57 #define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
58 #define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
59 #define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
60 #define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
61 #define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
62 #define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
63 #define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
64 #define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
65 #define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
66 #define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
67 #define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
68 #define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
69 #define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
70 #define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
71 #define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
72 #define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
73 #define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
74 #define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
75 #define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
76 #define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
77 #define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
78 #define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
79 #define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
80 #define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
81 #define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
82 #define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
83 #define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
84 #define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
85 #define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
86 #define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
87 #define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
88 #define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
89 #define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
90 #define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
91 #define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
92 #define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
93 #define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
94 #define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
95 #define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
96 #define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
97 #define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
98 #define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
99 #define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
100 #define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
101 #define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
102 #define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
103 #define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
104 #define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
105 #define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
106 #define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
107 #define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
108 #define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
109 #define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
110 #define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
111 #define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
112 #define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
113 #define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
114 #define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
115 #define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
116 #define CVMX_SLI_STATE1 (0x0000000000000620ull)
117 #define CVMX_SLI_STATE2 (0x0000000000000630ull)
118 #define CVMX_SLI_STATE3 (0x0000000000000640ull)
119 #define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
120 #define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
121 #define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
122 #define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
123 #define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
124 #define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
125 #define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
127 union cvmx_sli_bist_status {
129 struct cvmx_sli_bist_status_s {
130 #ifdef __BIG_ENDIAN_BITFIELD
131 uint64_t reserved_32_63:32;
139 uint64_t reserved_19_24:6;
150 uint64_t reserved_6_8:3;
164 uint64_t reserved_6_8:3;
175 uint64_t reserved_19_24:6;
183 uint64_t reserved_32_63:32;
186 struct cvmx_sli_bist_status_cn61xx {
187 #ifdef __BIG_ENDIAN_BITFIELD
188 uint64_t reserved_31_63:33;
191 uint64_t reserved_27_28:2;
194 uint64_t reserved_19_24:6;
205 uint64_t reserved_6_8:3;
219 uint64_t reserved_6_8:3;
230 uint64_t reserved_19_24:6;
233 uint64_t reserved_27_28:2;
236 uint64_t reserved_31_63:33;
239 struct cvmx_sli_bist_status_cn63xx {
240 #ifdef __BIG_ENDIAN_BITFIELD
241 uint64_t reserved_31_63:33;
248 uint64_t reserved_19_24:6;
259 uint64_t reserved_6_8:3;
273 uint64_t reserved_6_8:3;
284 uint64_t reserved_19_24:6;
291 uint64_t reserved_31_63:33;
294 struct cvmx_sli_bist_status_cn63xx cn63xxp1;
295 struct cvmx_sli_bist_status_cn61xx cn66xx;
296 struct cvmx_sli_bist_status_s cn68xx;
297 struct cvmx_sli_bist_status_s cn68xxp1;
298 struct cvmx_sli_bist_status_cn61xx cnf71xx;
301 union cvmx_sli_ctl_portx {
303 struct cvmx_sli_ctl_portx_s {
304 #ifdef __BIG_ENDIAN_BITFIELD
305 uint64_t reserved_22_63:42;
311 uint64_t waitl_com:1;
317 uint64_t reserved_6_6:1;
319 uint64_t reserved_1_4:4;
323 uint64_t reserved_1_4:4;
325 uint64_t reserved_6_6:1;
331 uint64_t waitl_com:1;
337 uint64_t reserved_22_63:42;
340 struct cvmx_sli_ctl_portx_s cn61xx;
341 struct cvmx_sli_ctl_portx_s cn63xx;
342 struct cvmx_sli_ctl_portx_s cn63xxp1;
343 struct cvmx_sli_ctl_portx_s cn66xx;
344 struct cvmx_sli_ctl_portx_s cn68xx;
345 struct cvmx_sli_ctl_portx_s cn68xxp1;
346 struct cvmx_sli_ctl_portx_s cnf71xx;
349 union cvmx_sli_ctl_status {
351 struct cvmx_sli_ctl_status_s {
352 #ifdef __BIG_ENDIAN_BITFIELD
353 uint64_t reserved_20_63:44;
361 uint64_t reserved_20_63:44;
364 struct cvmx_sli_ctl_status_cn61xx {
365 #ifdef __BIG_ENDIAN_BITFIELD
366 uint64_t reserved_14_63:50;
372 uint64_t reserved_14_63:50;
375 struct cvmx_sli_ctl_status_s cn63xx;
376 struct cvmx_sli_ctl_status_s cn63xxp1;
377 struct cvmx_sli_ctl_status_cn61xx cn66xx;
378 struct cvmx_sli_ctl_status_s cn68xx;
379 struct cvmx_sli_ctl_status_s cn68xxp1;
380 struct cvmx_sli_ctl_status_cn61xx cnf71xx;
383 union cvmx_sli_data_out_cnt {
385 struct cvmx_sli_data_out_cnt_s {
386 #ifdef __BIG_ENDIAN_BITFIELD
387 uint64_t reserved_44_63:20;
397 uint64_t reserved_44_63:20;
400 struct cvmx_sli_data_out_cnt_s cn61xx;
401 struct cvmx_sli_data_out_cnt_s cn63xx;
402 struct cvmx_sli_data_out_cnt_s cn63xxp1;
403 struct cvmx_sli_data_out_cnt_s cn66xx;
404 struct cvmx_sli_data_out_cnt_s cn68xx;
405 struct cvmx_sli_data_out_cnt_s cn68xxp1;
406 struct cvmx_sli_data_out_cnt_s cnf71xx;
409 union cvmx_sli_dbg_data {
411 struct cvmx_sli_dbg_data_s {
412 #ifdef __BIG_ENDIAN_BITFIELD
413 uint64_t reserved_18_63:46;
419 uint64_t reserved_18_63:46;
422 struct cvmx_sli_dbg_data_s cn61xx;
423 struct cvmx_sli_dbg_data_s cn63xx;
424 struct cvmx_sli_dbg_data_s cn63xxp1;
425 struct cvmx_sli_dbg_data_s cn66xx;
426 struct cvmx_sli_dbg_data_s cn68xx;
427 struct cvmx_sli_dbg_data_s cn68xxp1;
428 struct cvmx_sli_dbg_data_s cnf71xx;
431 union cvmx_sli_dbg_select {
433 struct cvmx_sli_dbg_select_s {
434 #ifdef __BIG_ENDIAN_BITFIELD
435 uint64_t reserved_33_63:31;
441 uint64_t reserved_33_63:31;
444 struct cvmx_sli_dbg_select_s cn61xx;
445 struct cvmx_sli_dbg_select_s cn63xx;
446 struct cvmx_sli_dbg_select_s cn63xxp1;
447 struct cvmx_sli_dbg_select_s cn66xx;
448 struct cvmx_sli_dbg_select_s cn68xx;
449 struct cvmx_sli_dbg_select_s cn68xxp1;
450 struct cvmx_sli_dbg_select_s cnf71xx;
453 union cvmx_sli_dmax_cnt {
455 struct cvmx_sli_dmax_cnt_s {
456 #ifdef __BIG_ENDIAN_BITFIELD
457 uint64_t reserved_32_63:32;
461 uint64_t reserved_32_63:32;
464 struct cvmx_sli_dmax_cnt_s cn61xx;
465 struct cvmx_sli_dmax_cnt_s cn63xx;
466 struct cvmx_sli_dmax_cnt_s cn63xxp1;
467 struct cvmx_sli_dmax_cnt_s cn66xx;
468 struct cvmx_sli_dmax_cnt_s cn68xx;
469 struct cvmx_sli_dmax_cnt_s cn68xxp1;
470 struct cvmx_sli_dmax_cnt_s cnf71xx;
473 union cvmx_sli_dmax_int_level {
475 struct cvmx_sli_dmax_int_level_s {
476 #ifdef __BIG_ENDIAN_BITFIELD
484 struct cvmx_sli_dmax_int_level_s cn61xx;
485 struct cvmx_sli_dmax_int_level_s cn63xx;
486 struct cvmx_sli_dmax_int_level_s cn63xxp1;
487 struct cvmx_sli_dmax_int_level_s cn66xx;
488 struct cvmx_sli_dmax_int_level_s cn68xx;
489 struct cvmx_sli_dmax_int_level_s cn68xxp1;
490 struct cvmx_sli_dmax_int_level_s cnf71xx;
493 union cvmx_sli_dmax_tim {
495 struct cvmx_sli_dmax_tim_s {
496 #ifdef __BIG_ENDIAN_BITFIELD
497 uint64_t reserved_32_63:32;
501 uint64_t reserved_32_63:32;
504 struct cvmx_sli_dmax_tim_s cn61xx;
505 struct cvmx_sli_dmax_tim_s cn63xx;
506 struct cvmx_sli_dmax_tim_s cn63xxp1;
507 struct cvmx_sli_dmax_tim_s cn66xx;
508 struct cvmx_sli_dmax_tim_s cn68xx;
509 struct cvmx_sli_dmax_tim_s cn68xxp1;
510 struct cvmx_sli_dmax_tim_s cnf71xx;
513 union cvmx_sli_int_enb_ciu {
515 struct cvmx_sli_int_enb_ciu_s {
516 #ifdef __BIG_ENDIAN_BITFIELD
517 uint64_t reserved_62_63:2;
520 uint64_t sprt3_err:1;
521 uint64_t sprt2_err:1;
522 uint64_t sprt1_err:1;
523 uint64_t sprt0_err:1;
532 uint64_t reserved_38_47:10;
536 uint64_t reserved_28_31:4;
545 uint64_t reserved_18_19:2;
556 uint64_t reserved_6_7:2;
561 uint64_t reserved_1_1:1;
565 uint64_t reserved_1_1:1;
570 uint64_t reserved_6_7:2;
581 uint64_t reserved_18_19:2;
590 uint64_t reserved_28_31:4;
594 uint64_t reserved_38_47:10;
603 uint64_t sprt0_err:1;
604 uint64_t sprt1_err:1;
605 uint64_t sprt2_err:1;
606 uint64_t sprt3_err:1;
609 uint64_t reserved_62_63:2;
612 struct cvmx_sli_int_enb_ciu_cn61xx {
613 #ifdef __BIG_ENDIAN_BITFIELD
614 uint64_t reserved_61_63:3;
616 uint64_t sprt3_err:1;
617 uint64_t sprt2_err:1;
618 uint64_t sprt1_err:1;
619 uint64_t sprt0_err:1;
628 uint64_t reserved_38_47:10;
632 uint64_t reserved_28_31:4;
641 uint64_t reserved_18_19:2;
652 uint64_t reserved_6_7:2;
657 uint64_t reserved_1_1:1;
661 uint64_t reserved_1_1:1;
666 uint64_t reserved_6_7:2;
677 uint64_t reserved_18_19:2;
686 uint64_t reserved_28_31:4;
690 uint64_t reserved_38_47:10;
699 uint64_t sprt0_err:1;
700 uint64_t sprt1_err:1;
701 uint64_t sprt2_err:1;
702 uint64_t sprt3_err:1;
704 uint64_t reserved_61_63:3;
707 struct cvmx_sli_int_enb_ciu_cn63xx {
708 #ifdef __BIG_ENDIAN_BITFIELD
709 uint64_t reserved_61_63:3;
711 uint64_t reserved_58_59:2;
712 uint64_t sprt1_err:1;
713 uint64_t sprt0_err:1;
722 uint64_t reserved_38_47:10;
726 uint64_t reserved_18_31:14;
737 uint64_t reserved_6_7:2;
742 uint64_t reserved_1_1:1;
746 uint64_t reserved_1_1:1;
751 uint64_t reserved_6_7:2;
762 uint64_t reserved_18_31:14;
766 uint64_t reserved_38_47:10;
775 uint64_t sprt0_err:1;
776 uint64_t sprt1_err:1;
777 uint64_t reserved_58_59:2;
779 uint64_t reserved_61_63:3;
782 struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
783 struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
784 struct cvmx_sli_int_enb_ciu_cn68xx {
785 #ifdef __BIG_ENDIAN_BITFIELD
786 uint64_t reserved_62_63:2;
789 uint64_t reserved_58_59:2;
790 uint64_t sprt1_err:1;
791 uint64_t sprt0_err:1;
796 uint64_t reserved_51_51:1;
800 uint64_t reserved_38_47:10;
804 uint64_t reserved_18_31:14;
815 uint64_t reserved_6_7:2;
820 uint64_t reserved_1_1:1;
824 uint64_t reserved_1_1:1;
829 uint64_t reserved_6_7:2;
840 uint64_t reserved_18_31:14;
844 uint64_t reserved_38_47:10;
848 uint64_t reserved_51_51:1;
853 uint64_t sprt0_err:1;
854 uint64_t sprt1_err:1;
855 uint64_t reserved_58_59:2;
858 uint64_t reserved_62_63:2;
861 struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
862 struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx;
865 union cvmx_sli_int_enb_portx {
867 struct cvmx_sli_int_enb_portx_s {
868 #ifdef __BIG_ENDIAN_BITFIELD
869 uint64_t reserved_62_63:2;
872 uint64_t sprt3_err:1;
873 uint64_t sprt2_err:1;
874 uint64_t sprt1_err:1;
875 uint64_t sprt0_err:1;
884 uint64_t reserved_38_47:10;
888 uint64_t reserved_28_31:4;
909 uint64_t reserved_6_7:2;
914 uint64_t reserved_1_1:1;
918 uint64_t reserved_1_1:1;
923 uint64_t reserved_6_7:2;
944 uint64_t reserved_28_31:4;
948 uint64_t reserved_38_47:10;
957 uint64_t sprt0_err:1;
958 uint64_t sprt1_err:1;
959 uint64_t sprt2_err:1;
960 uint64_t sprt3_err:1;
963 uint64_t reserved_62_63:2;
966 struct cvmx_sli_int_enb_portx_cn61xx {
967 #ifdef __BIG_ENDIAN_BITFIELD
968 uint64_t reserved_61_63:3;
970 uint64_t sprt3_err:1;
971 uint64_t sprt2_err:1;
972 uint64_t sprt1_err:1;
973 uint64_t sprt0_err:1;
982 uint64_t reserved_38_47:10;
986 uint64_t reserved_28_31:4;
1000 uint64_t m1_un_b0:1;
1001 uint64_t m1_up_wi:1;
1002 uint64_t m1_up_b0:1;
1003 uint64_t m0_un_wi:1;
1004 uint64_t m0_un_b0:1;
1005 uint64_t m0_up_wi:1;
1006 uint64_t m0_up_b0:1;
1007 uint64_t reserved_6_7:2;
1012 uint64_t reserved_1_1:1;
1016 uint64_t reserved_1_1:1;
1021 uint64_t reserved_6_7:2;
1022 uint64_t m0_up_b0:1;
1023 uint64_t m0_up_wi:1;
1024 uint64_t m0_un_b0:1;
1025 uint64_t m0_un_wi:1;
1026 uint64_t m1_up_b0:1;
1027 uint64_t m1_up_wi:1;
1028 uint64_t m1_un_b0:1;
1029 uint64_t m1_un_wi:1;
1030 uint64_t mio_int0:1;
1031 uint64_t mio_int1:1;
1032 uint64_t mac0_int:1;
1033 uint64_t mac1_int:1;
1034 uint64_t m2_up_b0:1;
1035 uint64_t m2_up_wi:1;
1036 uint64_t m2_un_b0:1;
1037 uint64_t m2_un_wi:1;
1038 uint64_t m3_up_b0:1;
1039 uint64_t m3_up_wi:1;
1040 uint64_t m3_un_b0:1;
1041 uint64_t m3_un_wi:1;
1042 uint64_t reserved_28_31:4;
1046 uint64_t reserved_38_47:10;
1049 uint64_t pout_err:1;
1054 uint64_t pins_err:1;
1055 uint64_t sprt0_err:1;
1056 uint64_t sprt1_err:1;
1057 uint64_t sprt2_err:1;
1058 uint64_t sprt3_err:1;
1060 uint64_t reserved_61_63:3;
1063 struct cvmx_sli_int_enb_portx_cn63xx {
1064 #ifdef __BIG_ENDIAN_BITFIELD
1065 uint64_t reserved_61_63:3;
1067 uint64_t reserved_58_59:2;
1068 uint64_t sprt1_err:1;
1069 uint64_t sprt0_err:1;
1070 uint64_t pins_err:1;
1075 uint64_t pout_err:1;
1078 uint64_t reserved_38_47:10;
1082 uint64_t reserved_20_31:12;
1083 uint64_t mac1_int:1;
1084 uint64_t mac0_int:1;
1085 uint64_t mio_int1:1;
1086 uint64_t mio_int0:1;
1087 uint64_t m1_un_wi:1;
1088 uint64_t m1_un_b0:1;
1089 uint64_t m1_up_wi:1;
1090 uint64_t m1_up_b0:1;
1091 uint64_t m0_un_wi:1;
1092 uint64_t m0_un_b0:1;
1093 uint64_t m0_up_wi:1;
1094 uint64_t m0_up_b0:1;
1095 uint64_t reserved_6_7:2;
1100 uint64_t reserved_1_1:1;
1104 uint64_t reserved_1_1:1;
1109 uint64_t reserved_6_7:2;
1110 uint64_t m0_up_b0:1;
1111 uint64_t m0_up_wi:1;
1112 uint64_t m0_un_b0:1;
1113 uint64_t m0_un_wi:1;
1114 uint64_t m1_up_b0:1;
1115 uint64_t m1_up_wi:1;
1116 uint64_t m1_un_b0:1;
1117 uint64_t m1_un_wi:1;
1118 uint64_t mio_int0:1;
1119 uint64_t mio_int1:1;
1120 uint64_t mac0_int:1;
1121 uint64_t mac1_int:1;
1122 uint64_t reserved_20_31:12;
1126 uint64_t reserved_38_47:10;
1129 uint64_t pout_err:1;
1134 uint64_t pins_err:1;
1135 uint64_t sprt0_err:1;
1136 uint64_t sprt1_err:1;
1137 uint64_t reserved_58_59:2;
1139 uint64_t reserved_61_63:3;
1142 struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
1143 struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
1144 struct cvmx_sli_int_enb_portx_cn68xx {
1145 #ifdef __BIG_ENDIAN_BITFIELD
1146 uint64_t reserved_62_63:2;
1147 uint64_t pipe_err:1;
1149 uint64_t reserved_58_59:2;
1150 uint64_t sprt1_err:1;
1151 uint64_t sprt0_err:1;
1152 uint64_t pins_err:1;
1156 uint64_t reserved_51_51:1;
1157 uint64_t pout_err:1;
1160 uint64_t reserved_38_47:10;
1164 uint64_t reserved_20_31:12;
1165 uint64_t mac1_int:1;
1166 uint64_t mac0_int:1;
1167 uint64_t mio_int1:1;
1168 uint64_t mio_int0:1;
1169 uint64_t m1_un_wi:1;
1170 uint64_t m1_un_b0:1;
1171 uint64_t m1_up_wi:1;
1172 uint64_t m1_up_b0:1;
1173 uint64_t m0_un_wi:1;
1174 uint64_t m0_un_b0:1;
1175 uint64_t m0_up_wi:1;
1176 uint64_t m0_up_b0:1;
1177 uint64_t reserved_6_7:2;
1182 uint64_t reserved_1_1:1;
1186 uint64_t reserved_1_1:1;
1191 uint64_t reserved_6_7:2;
1192 uint64_t m0_up_b0:1;
1193 uint64_t m0_up_wi:1;
1194 uint64_t m0_un_b0:1;
1195 uint64_t m0_un_wi:1;
1196 uint64_t m1_up_b0:1;
1197 uint64_t m1_up_wi:1;
1198 uint64_t m1_un_b0:1;
1199 uint64_t m1_un_wi:1;
1200 uint64_t mio_int0:1;
1201 uint64_t mio_int1:1;
1202 uint64_t mac0_int:1;
1203 uint64_t mac1_int:1;
1204 uint64_t reserved_20_31:12;
1208 uint64_t reserved_38_47:10;
1211 uint64_t pout_err:1;
1212 uint64_t reserved_51_51:1;
1216 uint64_t pins_err:1;
1217 uint64_t sprt0_err:1;
1218 uint64_t sprt1_err:1;
1219 uint64_t reserved_58_59:2;
1221 uint64_t pipe_err:1;
1222 uint64_t reserved_62_63:2;
1225 struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
1226 struct cvmx_sli_int_enb_portx_cn61xx cnf71xx;
1229 union cvmx_sli_int_sum {
1231 struct cvmx_sli_int_sum_s {
1232 #ifdef __BIG_ENDIAN_BITFIELD
1233 uint64_t reserved_62_63:2;
1234 uint64_t pipe_err:1;
1236 uint64_t sprt3_err:1;
1237 uint64_t sprt2_err:1;
1238 uint64_t sprt1_err:1;
1239 uint64_t sprt0_err:1;
1240 uint64_t pins_err:1;
1245 uint64_t pout_err:1;
1248 uint64_t reserved_38_47:10;
1252 uint64_t reserved_28_31:4;
1253 uint64_t m3_un_wi:1;
1254 uint64_t m3_un_b0:1;
1255 uint64_t m3_up_wi:1;
1256 uint64_t m3_up_b0:1;
1257 uint64_t m2_un_wi:1;
1258 uint64_t m2_un_b0:1;
1259 uint64_t m2_up_wi:1;
1260 uint64_t m2_up_b0:1;
1261 uint64_t mac1_int:1;
1262 uint64_t mac0_int:1;
1263 uint64_t mio_int1:1;
1264 uint64_t mio_int0:1;
1265 uint64_t m1_un_wi:1;
1266 uint64_t m1_un_b0:1;
1267 uint64_t m1_up_wi:1;
1268 uint64_t m1_up_b0:1;
1269 uint64_t m0_un_wi:1;
1270 uint64_t m0_un_b0:1;
1271 uint64_t m0_up_wi:1;
1272 uint64_t m0_up_b0:1;
1273 uint64_t reserved_6_7:2;
1278 uint64_t reserved_1_1:1;
1282 uint64_t reserved_1_1:1;
1287 uint64_t reserved_6_7:2;
1288 uint64_t m0_up_b0:1;
1289 uint64_t m0_up_wi:1;
1290 uint64_t m0_un_b0:1;
1291 uint64_t m0_un_wi:1;
1292 uint64_t m1_up_b0:1;
1293 uint64_t m1_up_wi:1;
1294 uint64_t m1_un_b0:1;
1295 uint64_t m1_un_wi:1;
1296 uint64_t mio_int0:1;
1297 uint64_t mio_int1:1;
1298 uint64_t mac0_int:1;
1299 uint64_t mac1_int:1;
1300 uint64_t m2_up_b0:1;
1301 uint64_t m2_up_wi:1;
1302 uint64_t m2_un_b0:1;
1303 uint64_t m2_un_wi:1;
1304 uint64_t m3_up_b0:1;
1305 uint64_t m3_up_wi:1;
1306 uint64_t m3_un_b0:1;
1307 uint64_t m3_un_wi:1;
1308 uint64_t reserved_28_31:4;
1312 uint64_t reserved_38_47:10;
1315 uint64_t pout_err:1;
1320 uint64_t pins_err:1;
1321 uint64_t sprt0_err:1;
1322 uint64_t sprt1_err:1;
1323 uint64_t sprt2_err:1;
1324 uint64_t sprt3_err:1;
1326 uint64_t pipe_err:1;
1327 uint64_t reserved_62_63:2;
1330 struct cvmx_sli_int_sum_cn61xx {
1331 #ifdef __BIG_ENDIAN_BITFIELD
1332 uint64_t reserved_61_63:3;
1334 uint64_t sprt3_err:1;
1335 uint64_t sprt2_err:1;
1336 uint64_t sprt1_err:1;
1337 uint64_t sprt0_err:1;
1338 uint64_t pins_err:1;
1343 uint64_t pout_err:1;
1346 uint64_t reserved_38_47:10;
1350 uint64_t reserved_28_31:4;
1351 uint64_t m3_un_wi:1;
1352 uint64_t m3_un_b0:1;
1353 uint64_t m3_up_wi:1;
1354 uint64_t m3_up_b0:1;
1355 uint64_t m2_un_wi:1;
1356 uint64_t m2_un_b0:1;
1357 uint64_t m2_up_wi:1;
1358 uint64_t m2_up_b0:1;
1359 uint64_t mac1_int:1;
1360 uint64_t mac0_int:1;
1361 uint64_t mio_int1:1;
1362 uint64_t mio_int0:1;
1363 uint64_t m1_un_wi:1;
1364 uint64_t m1_un_b0:1;
1365 uint64_t m1_up_wi:1;
1366 uint64_t m1_up_b0:1;
1367 uint64_t m0_un_wi:1;
1368 uint64_t m0_un_b0:1;
1369 uint64_t m0_up_wi:1;
1370 uint64_t m0_up_b0:1;
1371 uint64_t reserved_6_7:2;
1376 uint64_t reserved_1_1:1;
1380 uint64_t reserved_1_1:1;
1385 uint64_t reserved_6_7:2;
1386 uint64_t m0_up_b0:1;
1387 uint64_t m0_up_wi:1;
1388 uint64_t m0_un_b0:1;
1389 uint64_t m0_un_wi:1;
1390 uint64_t m1_up_b0:1;
1391 uint64_t m1_up_wi:1;
1392 uint64_t m1_un_b0:1;
1393 uint64_t m1_un_wi:1;
1394 uint64_t mio_int0:1;
1395 uint64_t mio_int1:1;
1396 uint64_t mac0_int:1;
1397 uint64_t mac1_int:1;
1398 uint64_t m2_up_b0:1;
1399 uint64_t m2_up_wi:1;
1400 uint64_t m2_un_b0:1;
1401 uint64_t m2_un_wi:1;
1402 uint64_t m3_up_b0:1;
1403 uint64_t m3_up_wi:1;
1404 uint64_t m3_un_b0:1;
1405 uint64_t m3_un_wi:1;
1406 uint64_t reserved_28_31:4;
1410 uint64_t reserved_38_47:10;
1413 uint64_t pout_err:1;
1418 uint64_t pins_err:1;
1419 uint64_t sprt0_err:1;
1420 uint64_t sprt1_err:1;
1421 uint64_t sprt2_err:1;
1422 uint64_t sprt3_err:1;
1424 uint64_t reserved_61_63:3;
1427 struct cvmx_sli_int_sum_cn63xx {
1428 #ifdef __BIG_ENDIAN_BITFIELD
1429 uint64_t reserved_61_63:3;
1431 uint64_t reserved_58_59:2;
1432 uint64_t sprt1_err:1;
1433 uint64_t sprt0_err:1;
1434 uint64_t pins_err:1;
1439 uint64_t pout_err:1;
1442 uint64_t reserved_38_47:10;
1446 uint64_t reserved_20_31:12;
1447 uint64_t mac1_int:1;
1448 uint64_t mac0_int:1;
1449 uint64_t mio_int1:1;
1450 uint64_t mio_int0:1;
1451 uint64_t m1_un_wi:1;
1452 uint64_t m1_un_b0:1;
1453 uint64_t m1_up_wi:1;
1454 uint64_t m1_up_b0:1;
1455 uint64_t m0_un_wi:1;
1456 uint64_t m0_un_b0:1;
1457 uint64_t m0_up_wi:1;
1458 uint64_t m0_up_b0:1;
1459 uint64_t reserved_6_7:2;
1464 uint64_t reserved_1_1:1;
1468 uint64_t reserved_1_1:1;
1473 uint64_t reserved_6_7:2;
1474 uint64_t m0_up_b0:1;
1475 uint64_t m0_up_wi:1;
1476 uint64_t m0_un_b0:1;
1477 uint64_t m0_un_wi:1;
1478 uint64_t m1_up_b0:1;
1479 uint64_t m1_up_wi:1;
1480 uint64_t m1_un_b0:1;
1481 uint64_t m1_un_wi:1;
1482 uint64_t mio_int0:1;
1483 uint64_t mio_int1:1;
1484 uint64_t mac0_int:1;
1485 uint64_t mac1_int:1;
1486 uint64_t reserved_20_31:12;
1490 uint64_t reserved_38_47:10;
1493 uint64_t pout_err:1;
1498 uint64_t pins_err:1;
1499 uint64_t sprt0_err:1;
1500 uint64_t sprt1_err:1;
1501 uint64_t reserved_58_59:2;
1503 uint64_t reserved_61_63:3;
1506 struct cvmx_sli_int_sum_cn63xx cn63xxp1;
1507 struct cvmx_sli_int_sum_cn61xx cn66xx;
1508 struct cvmx_sli_int_sum_cn68xx {
1509 #ifdef __BIG_ENDIAN_BITFIELD
1510 uint64_t reserved_62_63:2;
1511 uint64_t pipe_err:1;
1513 uint64_t reserved_58_59:2;
1514 uint64_t sprt1_err:1;
1515 uint64_t sprt0_err:1;
1516 uint64_t pins_err:1;
1520 uint64_t reserved_51_51:1;
1521 uint64_t pout_err:1;
1524 uint64_t reserved_38_47:10;
1528 uint64_t reserved_20_31:12;
1529 uint64_t mac1_int:1;
1530 uint64_t mac0_int:1;
1531 uint64_t mio_int1:1;
1532 uint64_t mio_int0:1;
1533 uint64_t m1_un_wi:1;
1534 uint64_t m1_un_b0:1;
1535 uint64_t m1_up_wi:1;
1536 uint64_t m1_up_b0:1;
1537 uint64_t m0_un_wi:1;
1538 uint64_t m0_un_b0:1;
1539 uint64_t m0_up_wi:1;
1540 uint64_t m0_up_b0:1;
1541 uint64_t reserved_6_7:2;
1546 uint64_t reserved_1_1:1;
1550 uint64_t reserved_1_1:1;
1555 uint64_t reserved_6_7:2;
1556 uint64_t m0_up_b0:1;
1557 uint64_t m0_up_wi:1;
1558 uint64_t m0_un_b0:1;
1559 uint64_t m0_un_wi:1;
1560 uint64_t m1_up_b0:1;
1561 uint64_t m1_up_wi:1;
1562 uint64_t m1_un_b0:1;
1563 uint64_t m1_un_wi:1;
1564 uint64_t mio_int0:1;
1565 uint64_t mio_int1:1;
1566 uint64_t mac0_int:1;
1567 uint64_t mac1_int:1;
1568 uint64_t reserved_20_31:12;
1572 uint64_t reserved_38_47:10;
1575 uint64_t pout_err:1;
1576 uint64_t reserved_51_51:1;
1580 uint64_t pins_err:1;
1581 uint64_t sprt0_err:1;
1582 uint64_t sprt1_err:1;
1583 uint64_t reserved_58_59:2;
1585 uint64_t pipe_err:1;
1586 uint64_t reserved_62_63:2;
1589 struct cvmx_sli_int_sum_cn68xx cn68xxp1;
1590 struct cvmx_sli_int_sum_cn61xx cnf71xx;
1593 union cvmx_sli_last_win_rdata0 {
1595 struct cvmx_sli_last_win_rdata0_s {
1596 #ifdef __BIG_ENDIAN_BITFIELD
1602 struct cvmx_sli_last_win_rdata0_s cn61xx;
1603 struct cvmx_sli_last_win_rdata0_s cn63xx;
1604 struct cvmx_sli_last_win_rdata0_s cn63xxp1;
1605 struct cvmx_sli_last_win_rdata0_s cn66xx;
1606 struct cvmx_sli_last_win_rdata0_s cn68xx;
1607 struct cvmx_sli_last_win_rdata0_s cn68xxp1;
1608 struct cvmx_sli_last_win_rdata0_s cnf71xx;
1611 union cvmx_sli_last_win_rdata1 {
1613 struct cvmx_sli_last_win_rdata1_s {
1614 #ifdef __BIG_ENDIAN_BITFIELD
1620 struct cvmx_sli_last_win_rdata1_s cn61xx;
1621 struct cvmx_sli_last_win_rdata1_s cn63xx;
1622 struct cvmx_sli_last_win_rdata1_s cn63xxp1;
1623 struct cvmx_sli_last_win_rdata1_s cn66xx;
1624 struct cvmx_sli_last_win_rdata1_s cn68xx;
1625 struct cvmx_sli_last_win_rdata1_s cn68xxp1;
1626 struct cvmx_sli_last_win_rdata1_s cnf71xx;
1629 union cvmx_sli_last_win_rdata2 {
1631 struct cvmx_sli_last_win_rdata2_s {
1632 #ifdef __BIG_ENDIAN_BITFIELD
1638 struct cvmx_sli_last_win_rdata2_s cn61xx;
1639 struct cvmx_sli_last_win_rdata2_s cn66xx;
1640 struct cvmx_sli_last_win_rdata2_s cnf71xx;
1643 union cvmx_sli_last_win_rdata3 {
1645 struct cvmx_sli_last_win_rdata3_s {
1646 #ifdef __BIG_ENDIAN_BITFIELD
1652 struct cvmx_sli_last_win_rdata3_s cn61xx;
1653 struct cvmx_sli_last_win_rdata3_s cn66xx;
1654 struct cvmx_sli_last_win_rdata3_s cnf71xx;
1657 union cvmx_sli_mac_credit_cnt {
1659 struct cvmx_sli_mac_credit_cnt_s {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661 uint64_t reserved_54_63:10;
1687 uint64_t reserved_54_63:10;
1690 struct cvmx_sli_mac_credit_cnt_s cn61xx;
1691 struct cvmx_sli_mac_credit_cnt_s cn63xx;
1692 struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
1693 #ifdef __BIG_ENDIAN_BITFIELD
1694 uint64_t reserved_48_63:16;
1708 uint64_t reserved_48_63:16;
1711 struct cvmx_sli_mac_credit_cnt_s cn66xx;
1712 struct cvmx_sli_mac_credit_cnt_s cn68xx;
1713 struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
1714 struct cvmx_sli_mac_credit_cnt_s cnf71xx;
1717 union cvmx_sli_mac_credit_cnt2 {
1719 struct cvmx_sli_mac_credit_cnt2_s {
1720 #ifdef __BIG_ENDIAN_BITFIELD
1721 uint64_t reserved_54_63:10;
1747 uint64_t reserved_54_63:10;
1750 struct cvmx_sli_mac_credit_cnt2_s cn61xx;
1751 struct cvmx_sli_mac_credit_cnt2_s cn66xx;
1752 struct cvmx_sli_mac_credit_cnt2_s cnf71xx;
1755 union cvmx_sli_mac_number {
1757 struct cvmx_sli_mac_number_s {
1758 #ifdef __BIG_ENDIAN_BITFIELD
1759 uint64_t reserved_9_63:55;
1765 uint64_t reserved_9_63:55;
1768 struct cvmx_sli_mac_number_s cn61xx;
1769 struct cvmx_sli_mac_number_cn63xx {
1770 #ifdef __BIG_ENDIAN_BITFIELD
1771 uint64_t reserved_8_63:56;
1775 uint64_t reserved_8_63:56;
1778 struct cvmx_sli_mac_number_s cn66xx;
1779 struct cvmx_sli_mac_number_cn63xx cn68xx;
1780 struct cvmx_sli_mac_number_cn63xx cn68xxp1;
1781 struct cvmx_sli_mac_number_s cnf71xx;
1784 union cvmx_sli_mem_access_ctl {
1786 struct cvmx_sli_mem_access_ctl_s {
1787 #ifdef __BIG_ENDIAN_BITFIELD
1788 uint64_t reserved_14_63:50;
1789 uint64_t max_word:4;
1793 uint64_t max_word:4;
1794 uint64_t reserved_14_63:50;
1797 struct cvmx_sli_mem_access_ctl_s cn61xx;
1798 struct cvmx_sli_mem_access_ctl_s cn63xx;
1799 struct cvmx_sli_mem_access_ctl_s cn63xxp1;
1800 struct cvmx_sli_mem_access_ctl_s cn66xx;
1801 struct cvmx_sli_mem_access_ctl_s cn68xx;
1802 struct cvmx_sli_mem_access_ctl_s cn68xxp1;
1803 struct cvmx_sli_mem_access_ctl_s cnf71xx;
1806 union cvmx_sli_mem_access_subidx {
1808 struct cvmx_sli_mem_access_subidx_s {
1809 #ifdef __BIG_ENDIAN_BITFIELD
1810 uint64_t reserved_43_63:21;
1818 uint64_t reserved_0_29:30;
1820 uint64_t reserved_0_29:30;
1828 uint64_t reserved_43_63:21;
1831 struct cvmx_sli_mem_access_subidx_cn61xx {
1832 #ifdef __BIG_ENDIAN_BITFIELD
1833 uint64_t reserved_43_63:21;
1851 uint64_t reserved_43_63:21;
1854 struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
1855 struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
1856 struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
1857 struct cvmx_sli_mem_access_subidx_cn68xx {
1858 #ifdef __BIG_ENDIAN_BITFIELD
1859 uint64_t reserved_43_63:21;
1868 uint64_t reserved_0_1:2;
1870 uint64_t reserved_0_1:2;
1879 uint64_t reserved_43_63:21;
1882 struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
1883 struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx;
1886 union cvmx_sli_msi_enb0 {
1888 struct cvmx_sli_msi_enb0_s {
1889 #ifdef __BIG_ENDIAN_BITFIELD
1895 struct cvmx_sli_msi_enb0_s cn61xx;
1896 struct cvmx_sli_msi_enb0_s cn63xx;
1897 struct cvmx_sli_msi_enb0_s cn63xxp1;
1898 struct cvmx_sli_msi_enb0_s cn66xx;
1899 struct cvmx_sli_msi_enb0_s cn68xx;
1900 struct cvmx_sli_msi_enb0_s cn68xxp1;
1901 struct cvmx_sli_msi_enb0_s cnf71xx;
1904 union cvmx_sli_msi_enb1 {
1906 struct cvmx_sli_msi_enb1_s {
1907 #ifdef __BIG_ENDIAN_BITFIELD
1913 struct cvmx_sli_msi_enb1_s cn61xx;
1914 struct cvmx_sli_msi_enb1_s cn63xx;
1915 struct cvmx_sli_msi_enb1_s cn63xxp1;
1916 struct cvmx_sli_msi_enb1_s cn66xx;
1917 struct cvmx_sli_msi_enb1_s cn68xx;
1918 struct cvmx_sli_msi_enb1_s cn68xxp1;
1919 struct cvmx_sli_msi_enb1_s cnf71xx;
1922 union cvmx_sli_msi_enb2 {
1924 struct cvmx_sli_msi_enb2_s {
1925 #ifdef __BIG_ENDIAN_BITFIELD
1931 struct cvmx_sli_msi_enb2_s cn61xx;
1932 struct cvmx_sli_msi_enb2_s cn63xx;
1933 struct cvmx_sli_msi_enb2_s cn63xxp1;
1934 struct cvmx_sli_msi_enb2_s cn66xx;
1935 struct cvmx_sli_msi_enb2_s cn68xx;
1936 struct cvmx_sli_msi_enb2_s cn68xxp1;
1937 struct cvmx_sli_msi_enb2_s cnf71xx;
1940 union cvmx_sli_msi_enb3 {
1942 struct cvmx_sli_msi_enb3_s {
1943 #ifdef __BIG_ENDIAN_BITFIELD
1949 struct cvmx_sli_msi_enb3_s cn61xx;
1950 struct cvmx_sli_msi_enb3_s cn63xx;
1951 struct cvmx_sli_msi_enb3_s cn63xxp1;
1952 struct cvmx_sli_msi_enb3_s cn66xx;
1953 struct cvmx_sli_msi_enb3_s cn68xx;
1954 struct cvmx_sli_msi_enb3_s cn68xxp1;
1955 struct cvmx_sli_msi_enb3_s cnf71xx;
1958 union cvmx_sli_msi_rcv0 {
1960 struct cvmx_sli_msi_rcv0_s {
1961 #ifdef __BIG_ENDIAN_BITFIELD
1967 struct cvmx_sli_msi_rcv0_s cn61xx;
1968 struct cvmx_sli_msi_rcv0_s cn63xx;
1969 struct cvmx_sli_msi_rcv0_s cn63xxp1;
1970 struct cvmx_sli_msi_rcv0_s cn66xx;
1971 struct cvmx_sli_msi_rcv0_s cn68xx;
1972 struct cvmx_sli_msi_rcv0_s cn68xxp1;
1973 struct cvmx_sli_msi_rcv0_s cnf71xx;
1976 union cvmx_sli_msi_rcv1 {
1978 struct cvmx_sli_msi_rcv1_s {
1979 #ifdef __BIG_ENDIAN_BITFIELD
1985 struct cvmx_sli_msi_rcv1_s cn61xx;
1986 struct cvmx_sli_msi_rcv1_s cn63xx;
1987 struct cvmx_sli_msi_rcv1_s cn63xxp1;
1988 struct cvmx_sli_msi_rcv1_s cn66xx;
1989 struct cvmx_sli_msi_rcv1_s cn68xx;
1990 struct cvmx_sli_msi_rcv1_s cn68xxp1;
1991 struct cvmx_sli_msi_rcv1_s cnf71xx;
1994 union cvmx_sli_msi_rcv2 {
1996 struct cvmx_sli_msi_rcv2_s {
1997 #ifdef __BIG_ENDIAN_BITFIELD
2003 struct cvmx_sli_msi_rcv2_s cn61xx;
2004 struct cvmx_sli_msi_rcv2_s cn63xx;
2005 struct cvmx_sli_msi_rcv2_s cn63xxp1;
2006 struct cvmx_sli_msi_rcv2_s cn66xx;
2007 struct cvmx_sli_msi_rcv2_s cn68xx;
2008 struct cvmx_sli_msi_rcv2_s cn68xxp1;
2009 struct cvmx_sli_msi_rcv2_s cnf71xx;
2012 union cvmx_sli_msi_rcv3 {
2014 struct cvmx_sli_msi_rcv3_s {
2015 #ifdef __BIG_ENDIAN_BITFIELD
2021 struct cvmx_sli_msi_rcv3_s cn61xx;
2022 struct cvmx_sli_msi_rcv3_s cn63xx;
2023 struct cvmx_sli_msi_rcv3_s cn63xxp1;
2024 struct cvmx_sli_msi_rcv3_s cn66xx;
2025 struct cvmx_sli_msi_rcv3_s cn68xx;
2026 struct cvmx_sli_msi_rcv3_s cn68xxp1;
2027 struct cvmx_sli_msi_rcv3_s cnf71xx;
2030 union cvmx_sli_msi_rd_map {
2032 struct cvmx_sli_msi_rd_map_s {
2033 #ifdef __BIG_ENDIAN_BITFIELD
2034 uint64_t reserved_16_63:48;
2040 uint64_t reserved_16_63:48;
2043 struct cvmx_sli_msi_rd_map_s cn61xx;
2044 struct cvmx_sli_msi_rd_map_s cn63xx;
2045 struct cvmx_sli_msi_rd_map_s cn63xxp1;
2046 struct cvmx_sli_msi_rd_map_s cn66xx;
2047 struct cvmx_sli_msi_rd_map_s cn68xx;
2048 struct cvmx_sli_msi_rd_map_s cn68xxp1;
2049 struct cvmx_sli_msi_rd_map_s cnf71xx;
2052 union cvmx_sli_msi_w1c_enb0 {
2054 struct cvmx_sli_msi_w1c_enb0_s {
2055 #ifdef __BIG_ENDIAN_BITFIELD
2061 struct cvmx_sli_msi_w1c_enb0_s cn61xx;
2062 struct cvmx_sli_msi_w1c_enb0_s cn63xx;
2063 struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
2064 struct cvmx_sli_msi_w1c_enb0_s cn66xx;
2065 struct cvmx_sli_msi_w1c_enb0_s cn68xx;
2066 struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
2067 struct cvmx_sli_msi_w1c_enb0_s cnf71xx;
2070 union cvmx_sli_msi_w1c_enb1 {
2072 struct cvmx_sli_msi_w1c_enb1_s {
2073 #ifdef __BIG_ENDIAN_BITFIELD
2079 struct cvmx_sli_msi_w1c_enb1_s cn61xx;
2080 struct cvmx_sli_msi_w1c_enb1_s cn63xx;
2081 struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
2082 struct cvmx_sli_msi_w1c_enb1_s cn66xx;
2083 struct cvmx_sli_msi_w1c_enb1_s cn68xx;
2084 struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
2085 struct cvmx_sli_msi_w1c_enb1_s cnf71xx;
2088 union cvmx_sli_msi_w1c_enb2 {
2090 struct cvmx_sli_msi_w1c_enb2_s {
2091 #ifdef __BIG_ENDIAN_BITFIELD
2097 struct cvmx_sli_msi_w1c_enb2_s cn61xx;
2098 struct cvmx_sli_msi_w1c_enb2_s cn63xx;
2099 struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
2100 struct cvmx_sli_msi_w1c_enb2_s cn66xx;
2101 struct cvmx_sli_msi_w1c_enb2_s cn68xx;
2102 struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
2103 struct cvmx_sli_msi_w1c_enb2_s cnf71xx;
2106 union cvmx_sli_msi_w1c_enb3 {
2108 struct cvmx_sli_msi_w1c_enb3_s {
2109 #ifdef __BIG_ENDIAN_BITFIELD
2115 struct cvmx_sli_msi_w1c_enb3_s cn61xx;
2116 struct cvmx_sli_msi_w1c_enb3_s cn63xx;
2117 struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
2118 struct cvmx_sli_msi_w1c_enb3_s cn66xx;
2119 struct cvmx_sli_msi_w1c_enb3_s cn68xx;
2120 struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
2121 struct cvmx_sli_msi_w1c_enb3_s cnf71xx;
2124 union cvmx_sli_msi_w1s_enb0 {
2126 struct cvmx_sli_msi_w1s_enb0_s {
2127 #ifdef __BIG_ENDIAN_BITFIELD
2133 struct cvmx_sli_msi_w1s_enb0_s cn61xx;
2134 struct cvmx_sli_msi_w1s_enb0_s cn63xx;
2135 struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
2136 struct cvmx_sli_msi_w1s_enb0_s cn66xx;
2137 struct cvmx_sli_msi_w1s_enb0_s cn68xx;
2138 struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
2139 struct cvmx_sli_msi_w1s_enb0_s cnf71xx;
2142 union cvmx_sli_msi_w1s_enb1 {
2144 struct cvmx_sli_msi_w1s_enb1_s {
2145 #ifdef __BIG_ENDIAN_BITFIELD
2151 struct cvmx_sli_msi_w1s_enb1_s cn61xx;
2152 struct cvmx_sli_msi_w1s_enb1_s cn63xx;
2153 struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
2154 struct cvmx_sli_msi_w1s_enb1_s cn66xx;
2155 struct cvmx_sli_msi_w1s_enb1_s cn68xx;
2156 struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
2157 struct cvmx_sli_msi_w1s_enb1_s cnf71xx;
2160 union cvmx_sli_msi_w1s_enb2 {
2162 struct cvmx_sli_msi_w1s_enb2_s {
2163 #ifdef __BIG_ENDIAN_BITFIELD
2169 struct cvmx_sli_msi_w1s_enb2_s cn61xx;
2170 struct cvmx_sli_msi_w1s_enb2_s cn63xx;
2171 struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
2172 struct cvmx_sli_msi_w1s_enb2_s cn66xx;
2173 struct cvmx_sli_msi_w1s_enb2_s cn68xx;
2174 struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
2175 struct cvmx_sli_msi_w1s_enb2_s cnf71xx;
2178 union cvmx_sli_msi_w1s_enb3 {
2180 struct cvmx_sli_msi_w1s_enb3_s {
2181 #ifdef __BIG_ENDIAN_BITFIELD
2187 struct cvmx_sli_msi_w1s_enb3_s cn61xx;
2188 struct cvmx_sli_msi_w1s_enb3_s cn63xx;
2189 struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
2190 struct cvmx_sli_msi_w1s_enb3_s cn66xx;
2191 struct cvmx_sli_msi_w1s_enb3_s cn68xx;
2192 struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
2193 struct cvmx_sli_msi_w1s_enb3_s cnf71xx;
2196 union cvmx_sli_msi_wr_map {
2198 struct cvmx_sli_msi_wr_map_s {
2199 #ifdef __BIG_ENDIAN_BITFIELD
2200 uint64_t reserved_16_63:48;
2206 uint64_t reserved_16_63:48;
2209 struct cvmx_sli_msi_wr_map_s cn61xx;
2210 struct cvmx_sli_msi_wr_map_s cn63xx;
2211 struct cvmx_sli_msi_wr_map_s cn63xxp1;
2212 struct cvmx_sli_msi_wr_map_s cn66xx;
2213 struct cvmx_sli_msi_wr_map_s cn68xx;
2214 struct cvmx_sli_msi_wr_map_s cn68xxp1;
2215 struct cvmx_sli_msi_wr_map_s cnf71xx;
2218 union cvmx_sli_pcie_msi_rcv {
2220 struct cvmx_sli_pcie_msi_rcv_s {
2221 #ifdef __BIG_ENDIAN_BITFIELD
2222 uint64_t reserved_8_63:56;
2226 uint64_t reserved_8_63:56;
2229 struct cvmx_sli_pcie_msi_rcv_s cn61xx;
2230 struct cvmx_sli_pcie_msi_rcv_s cn63xx;
2231 struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
2232 struct cvmx_sli_pcie_msi_rcv_s cn66xx;
2233 struct cvmx_sli_pcie_msi_rcv_s cn68xx;
2234 struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
2235 struct cvmx_sli_pcie_msi_rcv_s cnf71xx;
2238 union cvmx_sli_pcie_msi_rcv_b1 {
2240 struct cvmx_sli_pcie_msi_rcv_b1_s {
2241 #ifdef __BIG_ENDIAN_BITFIELD
2242 uint64_t reserved_16_63:48;
2244 uint64_t reserved_0_7:8;
2246 uint64_t reserved_0_7:8;
2248 uint64_t reserved_16_63:48;
2251 struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
2252 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
2253 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
2254 struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
2255 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
2256 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
2257 struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx;
2260 union cvmx_sli_pcie_msi_rcv_b2 {
2262 struct cvmx_sli_pcie_msi_rcv_b2_s {
2263 #ifdef __BIG_ENDIAN_BITFIELD
2264 uint64_t reserved_24_63:40;
2266 uint64_t reserved_0_15:16;
2268 uint64_t reserved_0_15:16;
2270 uint64_t reserved_24_63:40;
2273 struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
2274 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
2275 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
2276 struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
2277 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
2278 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
2279 struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx;
2282 union cvmx_sli_pcie_msi_rcv_b3 {
2284 struct cvmx_sli_pcie_msi_rcv_b3_s {
2285 #ifdef __BIG_ENDIAN_BITFIELD
2286 uint64_t reserved_32_63:32;
2288 uint64_t reserved_0_23:24;
2290 uint64_t reserved_0_23:24;
2292 uint64_t reserved_32_63:32;
2295 struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
2296 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
2297 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
2298 struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
2299 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
2300 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
2301 struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx;
2304 union cvmx_sli_pktx_cnts {
2306 struct cvmx_sli_pktx_cnts_s {
2307 #ifdef __BIG_ENDIAN_BITFIELD
2308 uint64_t reserved_54_63:10;
2314 uint64_t reserved_54_63:10;
2317 struct cvmx_sli_pktx_cnts_s cn61xx;
2318 struct cvmx_sli_pktx_cnts_s cn63xx;
2319 struct cvmx_sli_pktx_cnts_s cn63xxp1;
2320 struct cvmx_sli_pktx_cnts_s cn66xx;
2321 struct cvmx_sli_pktx_cnts_s cn68xx;
2322 struct cvmx_sli_pktx_cnts_s cn68xxp1;
2323 struct cvmx_sli_pktx_cnts_s cnf71xx;
2326 union cvmx_sli_pktx_in_bp {
2328 struct cvmx_sli_pktx_in_bp_s {
2329 #ifdef __BIG_ENDIAN_BITFIELD
2337 struct cvmx_sli_pktx_in_bp_s cn61xx;
2338 struct cvmx_sli_pktx_in_bp_s cn63xx;
2339 struct cvmx_sli_pktx_in_bp_s cn63xxp1;
2340 struct cvmx_sli_pktx_in_bp_s cn66xx;
2341 struct cvmx_sli_pktx_in_bp_s cnf71xx;
2344 union cvmx_sli_pktx_instr_baddr {
2346 struct cvmx_sli_pktx_instr_baddr_s {
2347 #ifdef __BIG_ENDIAN_BITFIELD
2349 uint64_t reserved_0_2:3;
2351 uint64_t reserved_0_2:3;
2355 struct cvmx_sli_pktx_instr_baddr_s cn61xx;
2356 struct cvmx_sli_pktx_instr_baddr_s cn63xx;
2357 struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
2358 struct cvmx_sli_pktx_instr_baddr_s cn66xx;
2359 struct cvmx_sli_pktx_instr_baddr_s cn68xx;
2360 struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
2361 struct cvmx_sli_pktx_instr_baddr_s cnf71xx;
2364 union cvmx_sli_pktx_instr_baoff_dbell {
2366 struct cvmx_sli_pktx_instr_baoff_dbell_s {
2367 #ifdef __BIG_ENDIAN_BITFIELD
2375 struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
2376 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
2377 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
2378 struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
2379 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
2380 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
2381 struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx;
2384 union cvmx_sli_pktx_instr_fifo_rsize {
2386 struct cvmx_sli_pktx_instr_fifo_rsize_s {
2387 #ifdef __BIG_ENDIAN_BITFIELD
2401 struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
2402 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
2403 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
2404 struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
2405 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
2406 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
2407 struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx;
2410 union cvmx_sli_pktx_instr_header {
2412 struct cvmx_sli_pktx_instr_header_s {
2413 #ifdef __BIG_ENDIAN_BITFIELD
2414 uint64_t reserved_44_63:20;
2416 uint64_t reserved_38_42:5;
2417 uint64_t rparmode:2;
2418 uint64_t reserved_35_35:1;
2419 uint64_t rskp_len:7;
2420 uint64_t rngrpext:2;
2425 uint64_t use_ihdr:1;
2426 uint64_t reserved_16_20:5;
2427 uint64_t par_mode:2;
2428 uint64_t reserved_13_13:1;
2442 uint64_t reserved_13_13:1;
2443 uint64_t par_mode:2;
2444 uint64_t reserved_16_20:5;
2445 uint64_t use_ihdr:1;
2450 uint64_t rngrpext:2;
2451 uint64_t rskp_len:7;
2452 uint64_t reserved_35_35:1;
2453 uint64_t rparmode:2;
2454 uint64_t reserved_38_42:5;
2456 uint64_t reserved_44_63:20;
2459 struct cvmx_sli_pktx_instr_header_cn61xx {
2460 #ifdef __BIG_ENDIAN_BITFIELD
2461 uint64_t reserved_44_63:20;
2463 uint64_t reserved_38_42:5;
2464 uint64_t rparmode:2;
2465 uint64_t reserved_35_35:1;
2466 uint64_t rskp_len:7;
2467 uint64_t reserved_26_27:2;
2472 uint64_t use_ihdr:1;
2473 uint64_t reserved_16_20:5;
2474 uint64_t par_mode:2;
2475 uint64_t reserved_13_13:1;
2477 uint64_t reserved_4_5:2;
2487 uint64_t reserved_4_5:2;
2489 uint64_t reserved_13_13:1;
2490 uint64_t par_mode:2;
2491 uint64_t reserved_16_20:5;
2492 uint64_t use_ihdr:1;
2497 uint64_t reserved_26_27:2;
2498 uint64_t rskp_len:7;
2499 uint64_t reserved_35_35:1;
2500 uint64_t rparmode:2;
2501 uint64_t reserved_38_42:5;
2503 uint64_t reserved_44_63:20;
2506 struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
2507 struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
2508 struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
2509 struct cvmx_sli_pktx_instr_header_s cn68xx;
2510 struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
2511 struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx;
2514 union cvmx_sli_pktx_out_size {
2516 struct cvmx_sli_pktx_out_size_s {
2517 #ifdef __BIG_ENDIAN_BITFIELD
2518 uint64_t reserved_23_63:41;
2524 uint64_t reserved_23_63:41;
2527 struct cvmx_sli_pktx_out_size_s cn61xx;
2528 struct cvmx_sli_pktx_out_size_s cn63xx;
2529 struct cvmx_sli_pktx_out_size_s cn63xxp1;
2530 struct cvmx_sli_pktx_out_size_s cn66xx;
2531 struct cvmx_sli_pktx_out_size_s cn68xx;
2532 struct cvmx_sli_pktx_out_size_s cn68xxp1;
2533 struct cvmx_sli_pktx_out_size_s cnf71xx;
2536 union cvmx_sli_pktx_slist_baddr {
2538 struct cvmx_sli_pktx_slist_baddr_s {
2539 #ifdef __BIG_ENDIAN_BITFIELD
2541 uint64_t reserved_0_3:4;
2543 uint64_t reserved_0_3:4;
2547 struct cvmx_sli_pktx_slist_baddr_s cn61xx;
2548 struct cvmx_sli_pktx_slist_baddr_s cn63xx;
2549 struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
2550 struct cvmx_sli_pktx_slist_baddr_s cn66xx;
2551 struct cvmx_sli_pktx_slist_baddr_s cn68xx;
2552 struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
2553 struct cvmx_sli_pktx_slist_baddr_s cnf71xx;
2556 union cvmx_sli_pktx_slist_baoff_dbell {
2558 struct cvmx_sli_pktx_slist_baoff_dbell_s {
2559 #ifdef __BIG_ENDIAN_BITFIELD
2567 struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
2568 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
2569 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
2570 struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
2571 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
2572 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
2573 struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx;
2576 union cvmx_sli_pktx_slist_fifo_rsize {
2578 struct cvmx_sli_pktx_slist_fifo_rsize_s {
2579 #ifdef __BIG_ENDIAN_BITFIELD
2580 uint64_t reserved_32_63:32;
2584 uint64_t reserved_32_63:32;
2587 struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
2588 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
2589 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
2590 struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
2591 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
2592 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
2593 struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx;
2596 union cvmx_sli_pkt_cnt_int {
2598 struct cvmx_sli_pkt_cnt_int_s {
2599 #ifdef __BIG_ENDIAN_BITFIELD
2600 uint64_t reserved_32_63:32;
2604 uint64_t reserved_32_63:32;
2607 struct cvmx_sli_pkt_cnt_int_s cn61xx;
2608 struct cvmx_sli_pkt_cnt_int_s cn63xx;
2609 struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
2610 struct cvmx_sli_pkt_cnt_int_s cn66xx;
2611 struct cvmx_sli_pkt_cnt_int_s cn68xx;
2612 struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
2613 struct cvmx_sli_pkt_cnt_int_s cnf71xx;
2616 union cvmx_sli_pkt_cnt_int_enb {
2618 struct cvmx_sli_pkt_cnt_int_enb_s {
2619 #ifdef __BIG_ENDIAN_BITFIELD
2620 uint64_t reserved_32_63:32;
2624 uint64_t reserved_32_63:32;
2627 struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
2628 struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
2629 struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
2630 struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
2631 struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
2632 struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
2633 struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx;
2636 union cvmx_sli_pkt_ctl {
2638 struct cvmx_sli_pkt_ctl_s {
2639 #ifdef __BIG_ENDIAN_BITFIELD
2640 uint64_t reserved_5_63:59;
2646 uint64_t reserved_5_63:59;
2649 struct cvmx_sli_pkt_ctl_s cn61xx;
2650 struct cvmx_sli_pkt_ctl_s cn63xx;
2651 struct cvmx_sli_pkt_ctl_s cn63xxp1;
2652 struct cvmx_sli_pkt_ctl_s cn66xx;
2653 struct cvmx_sli_pkt_ctl_s cn68xx;
2654 struct cvmx_sli_pkt_ctl_s cn68xxp1;
2655 struct cvmx_sli_pkt_ctl_s cnf71xx;
2658 union cvmx_sli_pkt_data_out_es {
2660 struct cvmx_sli_pkt_data_out_es_s {
2661 #ifdef __BIG_ENDIAN_BITFIELD
2667 struct cvmx_sli_pkt_data_out_es_s cn61xx;
2668 struct cvmx_sli_pkt_data_out_es_s cn63xx;
2669 struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
2670 struct cvmx_sli_pkt_data_out_es_s cn66xx;
2671 struct cvmx_sli_pkt_data_out_es_s cn68xx;
2672 struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
2673 struct cvmx_sli_pkt_data_out_es_s cnf71xx;
2676 union cvmx_sli_pkt_data_out_ns {
2678 struct cvmx_sli_pkt_data_out_ns_s {
2679 #ifdef __BIG_ENDIAN_BITFIELD
2680 uint64_t reserved_32_63:32;
2684 uint64_t reserved_32_63:32;
2687 struct cvmx_sli_pkt_data_out_ns_s cn61xx;
2688 struct cvmx_sli_pkt_data_out_ns_s cn63xx;
2689 struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
2690 struct cvmx_sli_pkt_data_out_ns_s cn66xx;
2691 struct cvmx_sli_pkt_data_out_ns_s cn68xx;
2692 struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
2693 struct cvmx_sli_pkt_data_out_ns_s cnf71xx;
2696 union cvmx_sli_pkt_data_out_ror {
2698 struct cvmx_sli_pkt_data_out_ror_s {
2699 #ifdef __BIG_ENDIAN_BITFIELD
2700 uint64_t reserved_32_63:32;
2704 uint64_t reserved_32_63:32;
2707 struct cvmx_sli_pkt_data_out_ror_s cn61xx;
2708 struct cvmx_sli_pkt_data_out_ror_s cn63xx;
2709 struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
2710 struct cvmx_sli_pkt_data_out_ror_s cn66xx;
2711 struct cvmx_sli_pkt_data_out_ror_s cn68xx;
2712 struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
2713 struct cvmx_sli_pkt_data_out_ror_s cnf71xx;
2716 union cvmx_sli_pkt_dpaddr {
2718 struct cvmx_sli_pkt_dpaddr_s {
2719 #ifdef __BIG_ENDIAN_BITFIELD
2720 uint64_t reserved_32_63:32;
2724 uint64_t reserved_32_63:32;
2727 struct cvmx_sli_pkt_dpaddr_s cn61xx;
2728 struct cvmx_sli_pkt_dpaddr_s cn63xx;
2729 struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
2730 struct cvmx_sli_pkt_dpaddr_s cn66xx;
2731 struct cvmx_sli_pkt_dpaddr_s cn68xx;
2732 struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
2733 struct cvmx_sli_pkt_dpaddr_s cnf71xx;
2736 union cvmx_sli_pkt_in_bp {
2738 struct cvmx_sli_pkt_in_bp_s {
2739 #ifdef __BIG_ENDIAN_BITFIELD
2740 uint64_t reserved_32_63:32;
2744 uint64_t reserved_32_63:32;
2747 struct cvmx_sli_pkt_in_bp_s cn61xx;
2748 struct cvmx_sli_pkt_in_bp_s cn63xx;
2749 struct cvmx_sli_pkt_in_bp_s cn63xxp1;
2750 struct cvmx_sli_pkt_in_bp_s cn66xx;
2751 struct cvmx_sli_pkt_in_bp_s cnf71xx;
2754 union cvmx_sli_pkt_in_donex_cnts {
2756 struct cvmx_sli_pkt_in_donex_cnts_s {
2757 #ifdef __BIG_ENDIAN_BITFIELD
2758 uint64_t reserved_32_63:32;
2762 uint64_t reserved_32_63:32;
2765 struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
2766 struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
2767 struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
2768 struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
2769 struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
2770 struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
2771 struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx;
2774 union cvmx_sli_pkt_in_instr_counts {
2776 struct cvmx_sli_pkt_in_instr_counts_s {
2777 #ifdef __BIG_ENDIAN_BITFIELD
2785 struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
2786 struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
2787 struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
2788 struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
2789 struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
2790 struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
2791 struct cvmx_sli_pkt_in_instr_counts_s cnf71xx;
2794 union cvmx_sli_pkt_in_pcie_port {
2796 struct cvmx_sli_pkt_in_pcie_port_s {
2797 #ifdef __BIG_ENDIAN_BITFIELD
2803 struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
2804 struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
2805 struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
2806 struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
2807 struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
2808 struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
2809 struct cvmx_sli_pkt_in_pcie_port_s cnf71xx;
2812 union cvmx_sli_pkt_input_control {
2814 struct cvmx_sli_pkt_input_control_s {
2815 #ifdef __BIG_ENDIAN_BITFIELD
2816 uint64_t prd_erst:1;
2818 uint64_t gii_erst:1;
2820 uint64_t reserved_41_47:7;
2821 uint64_t prc_idle:1;
2822 uint64_t reserved_24_39:16;
2825 uint64_t pbp_dhi:13;
2841 uint64_t pbp_dhi:13;
2844 uint64_t reserved_24_39:16;
2845 uint64_t prc_idle:1;
2846 uint64_t reserved_41_47:7;
2848 uint64_t gii_erst:1;
2850 uint64_t prd_erst:1;
2853 struct cvmx_sli_pkt_input_control_s cn61xx;
2854 struct cvmx_sli_pkt_input_control_cn63xx {
2855 #ifdef __BIG_ENDIAN_BITFIELD
2856 uint64_t reserved_23_63:41;
2858 uint64_t pbp_dhi:13;
2874 uint64_t pbp_dhi:13;
2876 uint64_t reserved_23_63:41;
2879 struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
2880 struct cvmx_sli_pkt_input_control_s cn66xx;
2881 struct cvmx_sli_pkt_input_control_s cn68xx;
2882 struct cvmx_sli_pkt_input_control_s cn68xxp1;
2883 struct cvmx_sli_pkt_input_control_s cnf71xx;
2886 union cvmx_sli_pkt_instr_enb {
2888 struct cvmx_sli_pkt_instr_enb_s {
2889 #ifdef __BIG_ENDIAN_BITFIELD
2890 uint64_t reserved_32_63:32;
2894 uint64_t reserved_32_63:32;
2897 struct cvmx_sli_pkt_instr_enb_s cn61xx;
2898 struct cvmx_sli_pkt_instr_enb_s cn63xx;
2899 struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
2900 struct cvmx_sli_pkt_instr_enb_s cn66xx;
2901 struct cvmx_sli_pkt_instr_enb_s cn68xx;
2902 struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
2903 struct cvmx_sli_pkt_instr_enb_s cnf71xx;
2906 union cvmx_sli_pkt_instr_rd_size {
2908 struct cvmx_sli_pkt_instr_rd_size_s {
2909 #ifdef __BIG_ENDIAN_BITFIELD
2915 struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
2916 struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
2917 struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
2918 struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
2919 struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
2920 struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
2921 struct cvmx_sli_pkt_instr_rd_size_s cnf71xx;
2924 union cvmx_sli_pkt_instr_size {
2926 struct cvmx_sli_pkt_instr_size_s {
2927 #ifdef __BIG_ENDIAN_BITFIELD
2928 uint64_t reserved_32_63:32;
2932 uint64_t reserved_32_63:32;
2935 struct cvmx_sli_pkt_instr_size_s cn61xx;
2936 struct cvmx_sli_pkt_instr_size_s cn63xx;
2937 struct cvmx_sli_pkt_instr_size_s cn63xxp1;
2938 struct cvmx_sli_pkt_instr_size_s cn66xx;
2939 struct cvmx_sli_pkt_instr_size_s cn68xx;
2940 struct cvmx_sli_pkt_instr_size_s cn68xxp1;
2941 struct cvmx_sli_pkt_instr_size_s cnf71xx;
2944 union cvmx_sli_pkt_int_levels {
2946 struct cvmx_sli_pkt_int_levels_s {
2947 #ifdef __BIG_ENDIAN_BITFIELD
2948 uint64_t reserved_54_63:10;
2954 uint64_t reserved_54_63:10;
2957 struct cvmx_sli_pkt_int_levels_s cn61xx;
2958 struct cvmx_sli_pkt_int_levels_s cn63xx;
2959 struct cvmx_sli_pkt_int_levels_s cn63xxp1;
2960 struct cvmx_sli_pkt_int_levels_s cn66xx;
2961 struct cvmx_sli_pkt_int_levels_s cn68xx;
2962 struct cvmx_sli_pkt_int_levels_s cn68xxp1;
2963 struct cvmx_sli_pkt_int_levels_s cnf71xx;
2966 union cvmx_sli_pkt_iptr {
2968 struct cvmx_sli_pkt_iptr_s {
2969 #ifdef __BIG_ENDIAN_BITFIELD
2970 uint64_t reserved_32_63:32;
2974 uint64_t reserved_32_63:32;
2977 struct cvmx_sli_pkt_iptr_s cn61xx;
2978 struct cvmx_sli_pkt_iptr_s cn63xx;
2979 struct cvmx_sli_pkt_iptr_s cn63xxp1;
2980 struct cvmx_sli_pkt_iptr_s cn66xx;
2981 struct cvmx_sli_pkt_iptr_s cn68xx;
2982 struct cvmx_sli_pkt_iptr_s cn68xxp1;
2983 struct cvmx_sli_pkt_iptr_s cnf71xx;
2986 union cvmx_sli_pkt_out_bmode {
2988 struct cvmx_sli_pkt_out_bmode_s {
2989 #ifdef __BIG_ENDIAN_BITFIELD
2990 uint64_t reserved_32_63:32;
2994 uint64_t reserved_32_63:32;
2997 struct cvmx_sli_pkt_out_bmode_s cn61xx;
2998 struct cvmx_sli_pkt_out_bmode_s cn63xx;
2999 struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
3000 struct cvmx_sli_pkt_out_bmode_s cn66xx;
3001 struct cvmx_sli_pkt_out_bmode_s cn68xx;
3002 struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
3003 struct cvmx_sli_pkt_out_bmode_s cnf71xx;
3006 union cvmx_sli_pkt_out_bp_en {
3008 struct cvmx_sli_pkt_out_bp_en_s {
3009 #ifdef __BIG_ENDIAN_BITFIELD
3010 uint64_t reserved_32_63:32;
3014 uint64_t reserved_32_63:32;
3017 struct cvmx_sli_pkt_out_bp_en_s cn68xx;
3018 struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
3021 union cvmx_sli_pkt_out_enb {
3023 struct cvmx_sli_pkt_out_enb_s {
3024 #ifdef __BIG_ENDIAN_BITFIELD
3025 uint64_t reserved_32_63:32;
3029 uint64_t reserved_32_63:32;
3032 struct cvmx_sli_pkt_out_enb_s cn61xx;
3033 struct cvmx_sli_pkt_out_enb_s cn63xx;
3034 struct cvmx_sli_pkt_out_enb_s cn63xxp1;
3035 struct cvmx_sli_pkt_out_enb_s cn66xx;
3036 struct cvmx_sli_pkt_out_enb_s cn68xx;
3037 struct cvmx_sli_pkt_out_enb_s cn68xxp1;
3038 struct cvmx_sli_pkt_out_enb_s cnf71xx;
3041 union cvmx_sli_pkt_output_wmark {
3043 struct cvmx_sli_pkt_output_wmark_s {
3044 #ifdef __BIG_ENDIAN_BITFIELD
3045 uint64_t reserved_32_63:32;
3049 uint64_t reserved_32_63:32;
3052 struct cvmx_sli_pkt_output_wmark_s cn61xx;
3053 struct cvmx_sli_pkt_output_wmark_s cn63xx;
3054 struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
3055 struct cvmx_sli_pkt_output_wmark_s cn66xx;
3056 struct cvmx_sli_pkt_output_wmark_s cn68xx;
3057 struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
3058 struct cvmx_sli_pkt_output_wmark_s cnf71xx;
3061 union cvmx_sli_pkt_pcie_port {
3063 struct cvmx_sli_pkt_pcie_port_s {
3064 #ifdef __BIG_ENDIAN_BITFIELD
3070 struct cvmx_sli_pkt_pcie_port_s cn61xx;
3071 struct cvmx_sli_pkt_pcie_port_s cn63xx;
3072 struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
3073 struct cvmx_sli_pkt_pcie_port_s cn66xx;
3074 struct cvmx_sli_pkt_pcie_port_s cn68xx;
3075 struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
3076 struct cvmx_sli_pkt_pcie_port_s cnf71xx;
3079 union cvmx_sli_pkt_port_in_rst {
3081 struct cvmx_sli_pkt_port_in_rst_s {
3082 #ifdef __BIG_ENDIAN_BITFIELD
3084 uint64_t out_rst:32;
3086 uint64_t out_rst:32;
3090 struct cvmx_sli_pkt_port_in_rst_s cn61xx;
3091 struct cvmx_sli_pkt_port_in_rst_s cn63xx;
3092 struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
3093 struct cvmx_sli_pkt_port_in_rst_s cn66xx;
3094 struct cvmx_sli_pkt_port_in_rst_s cn68xx;
3095 struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
3096 struct cvmx_sli_pkt_port_in_rst_s cnf71xx;
3099 union cvmx_sli_pkt_slist_es {
3101 struct cvmx_sli_pkt_slist_es_s {
3102 #ifdef __BIG_ENDIAN_BITFIELD
3108 struct cvmx_sli_pkt_slist_es_s cn61xx;
3109 struct cvmx_sli_pkt_slist_es_s cn63xx;
3110 struct cvmx_sli_pkt_slist_es_s cn63xxp1;
3111 struct cvmx_sli_pkt_slist_es_s cn66xx;
3112 struct cvmx_sli_pkt_slist_es_s cn68xx;
3113 struct cvmx_sli_pkt_slist_es_s cn68xxp1;
3114 struct cvmx_sli_pkt_slist_es_s cnf71xx;
3117 union cvmx_sli_pkt_slist_ns {
3119 struct cvmx_sli_pkt_slist_ns_s {
3120 #ifdef __BIG_ENDIAN_BITFIELD
3121 uint64_t reserved_32_63:32;
3125 uint64_t reserved_32_63:32;
3128 struct cvmx_sli_pkt_slist_ns_s cn61xx;
3129 struct cvmx_sli_pkt_slist_ns_s cn63xx;
3130 struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
3131 struct cvmx_sli_pkt_slist_ns_s cn66xx;
3132 struct cvmx_sli_pkt_slist_ns_s cn68xx;
3133 struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
3134 struct cvmx_sli_pkt_slist_ns_s cnf71xx;
3137 union cvmx_sli_pkt_slist_ror {
3139 struct cvmx_sli_pkt_slist_ror_s {
3140 #ifdef __BIG_ENDIAN_BITFIELD
3141 uint64_t reserved_32_63:32;
3145 uint64_t reserved_32_63:32;
3148 struct cvmx_sli_pkt_slist_ror_s cn61xx;
3149 struct cvmx_sli_pkt_slist_ror_s cn63xx;
3150 struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
3151 struct cvmx_sli_pkt_slist_ror_s cn66xx;
3152 struct cvmx_sli_pkt_slist_ror_s cn68xx;
3153 struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
3154 struct cvmx_sli_pkt_slist_ror_s cnf71xx;
3157 union cvmx_sli_pkt_time_int {
3159 struct cvmx_sli_pkt_time_int_s {
3160 #ifdef __BIG_ENDIAN_BITFIELD
3161 uint64_t reserved_32_63:32;
3165 uint64_t reserved_32_63:32;
3168 struct cvmx_sli_pkt_time_int_s cn61xx;
3169 struct cvmx_sli_pkt_time_int_s cn63xx;
3170 struct cvmx_sli_pkt_time_int_s cn63xxp1;
3171 struct cvmx_sli_pkt_time_int_s cn66xx;
3172 struct cvmx_sli_pkt_time_int_s cn68xx;
3173 struct cvmx_sli_pkt_time_int_s cn68xxp1;
3174 struct cvmx_sli_pkt_time_int_s cnf71xx;
3177 union cvmx_sli_pkt_time_int_enb {
3179 struct cvmx_sli_pkt_time_int_enb_s {
3180 #ifdef __BIG_ENDIAN_BITFIELD
3181 uint64_t reserved_32_63:32;
3185 uint64_t reserved_32_63:32;
3188 struct cvmx_sli_pkt_time_int_enb_s cn61xx;
3189 struct cvmx_sli_pkt_time_int_enb_s cn63xx;
3190 struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
3191 struct cvmx_sli_pkt_time_int_enb_s cn66xx;
3192 struct cvmx_sli_pkt_time_int_enb_s cn68xx;
3193 struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
3194 struct cvmx_sli_pkt_time_int_enb_s cnf71xx;
3197 union cvmx_sli_portx_pkind {
3199 struct cvmx_sli_portx_pkind_s {
3200 #ifdef __BIG_ENDIAN_BITFIELD
3201 uint64_t reserved_25_63:39;
3203 uint64_t reserved_22_23:2;
3205 uint64_t reserved_14_15:2;
3207 uint64_t reserved_6_7:2;
3211 uint64_t reserved_6_7:2;
3213 uint64_t reserved_14_15:2;
3215 uint64_t reserved_22_23:2;
3217 uint64_t reserved_25_63:39;
3220 struct cvmx_sli_portx_pkind_s cn68xx;
3221 struct cvmx_sli_portx_pkind_cn68xxp1 {
3222 #ifdef __BIG_ENDIAN_BITFIELD
3223 uint64_t reserved_14_63:50;
3225 uint64_t reserved_6_7:2;
3229 uint64_t reserved_6_7:2;
3231 uint64_t reserved_14_63:50;
3236 union cvmx_sli_s2m_portx_ctl {
3238 struct cvmx_sli_s2m_portx_ctl_s {
3239 #ifdef __BIG_ENDIAN_BITFIELD
3240 uint64_t reserved_5_63:59;
3248 uint64_t reserved_5_63:59;
3251 struct cvmx_sli_s2m_portx_ctl_s cn61xx;
3252 struct cvmx_sli_s2m_portx_ctl_s cn63xx;
3253 struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
3254 struct cvmx_sli_s2m_portx_ctl_s cn66xx;
3255 struct cvmx_sli_s2m_portx_ctl_s cn68xx;
3256 struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
3257 struct cvmx_sli_s2m_portx_ctl_s cnf71xx;
3260 union cvmx_sli_scratch_1 {
3262 struct cvmx_sli_scratch_1_s {
3263 #ifdef __BIG_ENDIAN_BITFIELD
3269 struct cvmx_sli_scratch_1_s cn61xx;
3270 struct cvmx_sli_scratch_1_s cn63xx;
3271 struct cvmx_sli_scratch_1_s cn63xxp1;
3272 struct cvmx_sli_scratch_1_s cn66xx;
3273 struct cvmx_sli_scratch_1_s cn68xx;
3274 struct cvmx_sli_scratch_1_s cn68xxp1;
3275 struct cvmx_sli_scratch_1_s cnf71xx;
3278 union cvmx_sli_scratch_2 {
3280 struct cvmx_sli_scratch_2_s {
3281 #ifdef __BIG_ENDIAN_BITFIELD
3287 struct cvmx_sli_scratch_2_s cn61xx;
3288 struct cvmx_sli_scratch_2_s cn63xx;
3289 struct cvmx_sli_scratch_2_s cn63xxp1;
3290 struct cvmx_sli_scratch_2_s cn66xx;
3291 struct cvmx_sli_scratch_2_s cn68xx;
3292 struct cvmx_sli_scratch_2_s cn68xxp1;
3293 struct cvmx_sli_scratch_2_s cnf71xx;
3296 union cvmx_sli_state1 {
3298 struct cvmx_sli_state1_s {
3299 #ifdef __BIG_ENDIAN_BITFIELD
3311 struct cvmx_sli_state1_s cn61xx;
3312 struct cvmx_sli_state1_s cn63xx;
3313 struct cvmx_sli_state1_s cn63xxp1;
3314 struct cvmx_sli_state1_s cn66xx;
3315 struct cvmx_sli_state1_s cn68xx;
3316 struct cvmx_sli_state1_s cn68xxp1;
3317 struct cvmx_sli_state1_s cnf71xx;
3320 union cvmx_sli_state2 {
3322 struct cvmx_sli_state2_s {
3323 #ifdef __BIG_ENDIAN_BITFIELD
3324 uint64_t reserved_56_63:8;
3326 uint64_t reserved_47_47:1;
3338 uint64_t reserved_47_47:1;
3340 uint64_t reserved_56_63:8;
3343 struct cvmx_sli_state2_s cn61xx;
3344 struct cvmx_sli_state2_s cn63xx;
3345 struct cvmx_sli_state2_s cn63xxp1;
3346 struct cvmx_sli_state2_s cn66xx;
3347 struct cvmx_sli_state2_s cn68xx;
3348 struct cvmx_sli_state2_s cn68xxp1;
3349 struct cvmx_sli_state2_s cnf71xx;
3352 union cvmx_sli_state3 {
3354 struct cvmx_sli_state3_s {
3355 #ifdef __BIG_ENDIAN_BITFIELD
3356 uint64_t reserved_56_63:8;
3366 uint64_t reserved_56_63:8;
3369 struct cvmx_sli_state3_s cn61xx;
3370 struct cvmx_sli_state3_s cn63xx;
3371 struct cvmx_sli_state3_s cn63xxp1;
3372 struct cvmx_sli_state3_s cn66xx;
3373 struct cvmx_sli_state3_s cn68xx;
3374 struct cvmx_sli_state3_s cn68xxp1;
3375 struct cvmx_sli_state3_s cnf71xx;
3378 union cvmx_sli_tx_pipe {
3380 struct cvmx_sli_tx_pipe_s {
3381 #ifdef __BIG_ENDIAN_BITFIELD
3382 uint64_t reserved_24_63:40;
3384 uint64_t reserved_7_15:9;
3388 uint64_t reserved_7_15:9;
3390 uint64_t reserved_24_63:40;
3393 struct cvmx_sli_tx_pipe_s cn68xx;
3394 struct cvmx_sli_tx_pipe_s cn68xxp1;
3397 union cvmx_sli_win_rd_addr {
3399 struct cvmx_sli_win_rd_addr_s {
3400 #ifdef __BIG_ENDIAN_BITFIELD
3401 uint64_t reserved_51_63:13;
3404 uint64_t rd_addr:48;
3406 uint64_t rd_addr:48;
3409 uint64_t reserved_51_63:13;
3412 struct cvmx_sli_win_rd_addr_s cn61xx;
3413 struct cvmx_sli_win_rd_addr_s cn63xx;
3414 struct cvmx_sli_win_rd_addr_s cn63xxp1;
3415 struct cvmx_sli_win_rd_addr_s cn66xx;
3416 struct cvmx_sli_win_rd_addr_s cn68xx;
3417 struct cvmx_sli_win_rd_addr_s cn68xxp1;
3418 struct cvmx_sli_win_rd_addr_s cnf71xx;
3421 union cvmx_sli_win_rd_data {
3423 struct cvmx_sli_win_rd_data_s {
3424 #ifdef __BIG_ENDIAN_BITFIELD
3425 uint64_t rd_data:64;
3427 uint64_t rd_data:64;
3430 struct cvmx_sli_win_rd_data_s cn61xx;
3431 struct cvmx_sli_win_rd_data_s cn63xx;
3432 struct cvmx_sli_win_rd_data_s cn63xxp1;
3433 struct cvmx_sli_win_rd_data_s cn66xx;
3434 struct cvmx_sli_win_rd_data_s cn68xx;
3435 struct cvmx_sli_win_rd_data_s cn68xxp1;
3436 struct cvmx_sli_win_rd_data_s cnf71xx;
3439 union cvmx_sli_win_wr_addr {
3441 struct cvmx_sli_win_wr_addr_s {
3442 #ifdef __BIG_ENDIAN_BITFIELD
3443 uint64_t reserved_49_63:15;
3445 uint64_t wr_addr:45;
3446 uint64_t reserved_0_2:3;
3448 uint64_t reserved_0_2:3;
3449 uint64_t wr_addr:45;
3451 uint64_t reserved_49_63:15;
3454 struct cvmx_sli_win_wr_addr_s cn61xx;
3455 struct cvmx_sli_win_wr_addr_s cn63xx;
3456 struct cvmx_sli_win_wr_addr_s cn63xxp1;
3457 struct cvmx_sli_win_wr_addr_s cn66xx;
3458 struct cvmx_sli_win_wr_addr_s cn68xx;
3459 struct cvmx_sli_win_wr_addr_s cn68xxp1;
3460 struct cvmx_sli_win_wr_addr_s cnf71xx;
3463 union cvmx_sli_win_wr_data {
3465 struct cvmx_sli_win_wr_data_s {
3466 #ifdef __BIG_ENDIAN_BITFIELD
3467 uint64_t wr_data:64;
3469 uint64_t wr_data:64;
3472 struct cvmx_sli_win_wr_data_s cn61xx;
3473 struct cvmx_sli_win_wr_data_s cn63xx;
3474 struct cvmx_sli_win_wr_data_s cn63xxp1;
3475 struct cvmx_sli_win_wr_data_s cn66xx;
3476 struct cvmx_sli_win_wr_data_s cn68xx;
3477 struct cvmx_sli_win_wr_data_s cn68xxp1;
3478 struct cvmx_sli_win_wr_data_s cnf71xx;
3481 union cvmx_sli_win_wr_mask {
3483 struct cvmx_sli_win_wr_mask_s {
3484 #ifdef __BIG_ENDIAN_BITFIELD
3485 uint64_t reserved_8_63:56;
3489 uint64_t reserved_8_63:56;
3492 struct cvmx_sli_win_wr_mask_s cn61xx;
3493 struct cvmx_sli_win_wr_mask_s cn63xx;
3494 struct cvmx_sli_win_wr_mask_s cn63xxp1;
3495 struct cvmx_sli_win_wr_mask_s cn66xx;
3496 struct cvmx_sli_win_wr_mask_s cn68xx;
3497 struct cvmx_sli_win_wr_mask_s cn68xxp1;
3498 struct cvmx_sli_win_wr_mask_s cnf71xx;
3501 union cvmx_sli_window_ctl {
3503 struct cvmx_sli_window_ctl_s {
3504 #ifdef __BIG_ENDIAN_BITFIELD
3505 uint64_t reserved_32_63:32;
3509 uint64_t reserved_32_63:32;
3512 struct cvmx_sli_window_ctl_s cn61xx;
3513 struct cvmx_sli_window_ctl_s cn63xx;
3514 struct cvmx_sli_window_ctl_s cn63xxp1;
3515 struct cvmx_sli_window_ctl_s cn66xx;
3516 struct cvmx_sli_window_ctl_s cn68xx;
3517 struct cvmx_sli_window_ctl_s cn68xxp1;
3518 struct cvmx_sli_window_ctl_s cnf71xx;