arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/module.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/fpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/system.h>
  26 #include <asm/watch.h>
  27 #include <asm/spram.h>
  28 #include <asm/uaccess.h>
  29
  30 /*
  31  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  32  * the implementation of the "wait" feature differs between CPU families. This
  33  * points to the function that implements CPU specific wait.
  34  * The wait instruction stops the pipeline and reduces the power consumption of
  35  * the CPU very much.
  36  */
  37 void (*cpu_wait)(void);
  38 EXPORT_SYMBOL(cpu_wait);
  39
  40 static void r3081_wait(void)
  41 {
  42         unsigned long cfg = read_c0_conf();
  43         write_c0_conf(cfg | R30XX_CONF_HALT);
  44 }
  45
  46 static void r39xx_wait(void)
  47 {
  48         local_irq_disable();
  49         if (!need_resched())
  50                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  51         local_irq_enable();
  52 }
  53
  54 extern void r4k_wait(void);
  55
  56 /*
  57  * This variant is preferable as it allows testing need_resched and going to
  58  * sleep depending on the outcome atomically.  Unfortunately the "It is
  59  * implementation-dependent whether the pipeline restarts when a non-enabled
  60  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  61  * using this version a gamble.
  62  */
  63 void r4k_wait_irqoff(void)
  64 {
  65         local_irq_disable();
  66         if (!need_resched())
  67                 __asm__("       .set    push            \n"
  68                         "       .set    mips3           \n"
  69                         "       wait                    \n"
  70                         "       .set    pop             \n");
  71         local_irq_enable();
  72         __asm__("       .globl __pastwait       \n"
  73                 "__pastwait:                    \n");
  74         return;
  75 }
  76
  77 /*
  78  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  79  * have any pending stores when the WAIT instruction is executed.
  80  */
  81 static void rm7k_wait_irqoff(void)
  82 {
  83         local_irq_disable();
  84         if (!need_resched())
  85                 __asm__(
  86                 "       .set    push                                    \n"
  87                 "       .set    mips3                                   \n"
  88                 "       .set    noat                                    \n"
  89                 "       mfc0    $1, $12                                 \n"
  90                 "       sync                                            \n"
  91                 "       mtc0    $1, $12         # stalls until W stage  \n"
  92                 "       wait                                            \n"
  93                 "       mtc0    $1, $12         # stalls until W stage  \n"
  94                 "       .set    pop                                     \n");
  95         local_irq_enable();
  96 }
  97
  98 /*
  99  * The Au1xxx wait is available only if using 32khz counter or
 100  * external timer source, but specifically not CP0 Counter.
 101  * alchemy/common/time.c may override cpu_wait!
 102  */
 103 static void au1k_wait(void)
 104 {
 105         __asm__("       .set    mips3                   \n"
 106                 "       cache   0x14, 0(%0)             \n"
 107                 "       cache   0x14, 32(%0)            \n"
 108                 "       sync                            \n"
 109                 "       nop                             \n"
 110                 "       wait                            \n"
 111                 "       nop                             \n"
 112                 "       nop                             \n"
 113                 "       nop                             \n"
 114                 "       nop                             \n"
 115                 "       .set    mips0                   \n"
 116                 : : "r" (au1k_wait));
 117 }
 118
 119 static int __initdata nowait;
 120
 121 static int __init wait_disable(char *s)
 122 {
 123         nowait = 1;
 124
 125         return 1;
 126 }
 127
 128 __setup("nowait", wait_disable);
 129
 130 static int __cpuinitdata mips_fpu_disabled;
 131
 132 static int __init fpu_disable(char *s)
 133 {
 134         cpu_data[0].options &= ~MIPS_CPU_FPU;
 135         mips_fpu_disabled = 1;
 136
 137         return 1;
 138 }
 139
 140 __setup("nofpu", fpu_disable);
 141
 142 int __cpuinitdata mips_dsp_disabled;
 143
 144 static int __init dsp_disable(char *s)
 145 {
 146         cpu_data[0].ases &= ~MIPS_ASE_DSP;
 147         mips_dsp_disabled = 1;
 148
 149         return 1;
 150 }
 151
 152 __setup("nodsp", dsp_disable);
 153
 154 void __init check_wait(void)
 155 {
 156         struct cpuinfo_mips *c = &current_cpu_data;
 157
 158         if (nowait) {
 159                 printk("Wait instruction disabled.\n");
 160                 return;
 161         }
 162
 163         switch (c->cputype) {
 164         case CPU_R3081:
 165         case CPU_R3081E:
 166                 cpu_wait = r3081_wait;
 167                 break;
 168         case CPU_TX3927:
 169                 cpu_wait = r39xx_wait;
 170                 break;
 171         case CPU_R4200:
 172 /*      case CPU_R4300: */
 173         case CPU_R4600:
 174         case CPU_R4640:
 175         case CPU_R4650:
 176         case CPU_R4700:
 177         case CPU_R5000:
 178         case CPU_R5500:
 179         case CPU_NEVADA:
 180         case CPU_4KC:
 181         case CPU_4KEC:
 182         case CPU_4KSC:
 183         case CPU_5KC:
 184         case CPU_25KF:
 185         case CPU_PR4450:
 186         case CPU_BMIPS3300:
 187         case CPU_BMIPS4350:
 188         case CPU_BMIPS4380:
 189         case CPU_BMIPS5000:
 190         case CPU_CAVIUM_OCTEON:
 191         case CPU_CAVIUM_OCTEON_PLUS:
 192         case CPU_CAVIUM_OCTEON2:
 193         case CPU_JZRISC:
 194                 cpu_wait = r4k_wait;
 195                 break;
 196
 197         case CPU_RM7000:
 198                 cpu_wait = rm7k_wait_irqoff;
 199                 break;
 200
 201         case CPU_24K:
 202         case CPU_34K:
 203         case CPU_1004K:
 204                 cpu_wait = r4k_wait;
 205                 if (read_c0_config7() & MIPS_CONF7_WII)
 206                         cpu_wait = r4k_wait_irqoff;
 207                 break;
 208
 209         case CPU_74K:
 210                 cpu_wait = r4k_wait;
 211                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 212                         cpu_wait = r4k_wait_irqoff;
 213                 break;
 214
 215         case CPU_TX49XX:
 216                 cpu_wait = r4k_wait_irqoff;
 217                 break;
 218         case CPU_ALCHEMY:
 219                 cpu_wait = au1k_wait;
 220                 break;
 221         case CPU_20KC:
 222                 /*
 223                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 224                  * WAIT on Rev2.0 and Rev3.0 has E16.
 225                  * Rev3.1 WAIT is nop, why bother
 226                  */
 227                 if ((c->processor_id & 0xff) <= 0x64)
 228                         break;
 229
 230                 /*
 231                  * Another rev is incremeting c0_count at a reduced clock
 232                  * rate while in WAIT mode.  So we basically have the choice
 233                  * between using the cp0 timer as clocksource or avoiding
 234                  * the WAIT instruction.  Until more details are known,
 235                  * disable the use of WAIT for 20Kc entirely.
 236                    cpu_wait = r4k_wait;
 237                  */
 238                 break;
 239         case CPU_RM9000:
 240                 if ((c->processor_id & 0x00ff) >= 0x40)
 241                         cpu_wait = r4k_wait;
 242                 break;
 243         default:
 244                 break;
 245         }
 246 }
 247
 248 static inline void check_errata(void)
 249 {
 250         struct cpuinfo_mips *c = &current_cpu_data;
 251
 252         switch (c->cputype) {
 253         case CPU_34K:
 254                 /*
 255                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 256                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 257                  * making use of VPE1 will be responsable for that VPE.
 258                  */
 259                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 260                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 261                 break;
 262         default:
 263                 break;
 264         }
 265 }
 266
 267 void __init check_bugs32(void)
 268 {
 269         check_errata();
 270 }
 271
 272 /*
 273  * Probe whether cpu has config register by trying to play with
 274  * alternate cache bit and see whether it matters.
 275  * It's used by cpu_probe to distinguish between R3000A and R3081.
 276  */
 277 static inline int cpu_has_confreg(void)
 278 {
 279 #ifdef CONFIG_CPU_R3000
 280         extern unsigned long r3k_cache_size(unsigned long);
 281         unsigned long size1, size2;
 282         unsigned long cfg = read_c0_conf();
 283
 284         size1 = r3k_cache_size(ST0_ISC);
 285         write_c0_conf(cfg ^ R30XX_CONF_AC);
 286         size2 = r3k_cache_size(ST0_ISC);
 287         write_c0_conf(cfg);
 288         return size1 != size2;
 289 #else
 290         return 0;
 291 #endif
 292 }
 293
 294 static inline void set_elf_platform(int cpu, const char *plat)
 295 {
 296         if (cpu == 0)
 297                 __elf_platform = plat;
 298 }
 299
 300 /*
 301  * Get the FPU Implementation/Revision.
 302  */
 303 static inline unsigned long cpu_get_fpu_id(void)
 304 {
 305         unsigned long tmp, fpu_id;
 306
 307         tmp = read_c0_status();
 308         __enable_fpu();
 309         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 310         write_c0_status(tmp);
 311         return fpu_id;
 312 }
 313
 314 /*
 315  * Check the CPU has an FPU the official way.
 316  */
 317 static inline int __cpu_has_fpu(void)
 318 {
 319         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 320 }
 321
 322 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 323 {
 324 #ifdef __NEED_VMBITS_PROBE
 325         write_c0_entryhi(0x3fffffffffffe000ULL);
 326         back_to_back_c0_hazard();
 327         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 328 #endif
 329 }
 330
 331 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 332                 | MIPS_CPU_COUNTER)
 333
 334 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 335 {
 336         switch (c->processor_id & 0xff00) {
 337         case PRID_IMP_R2000:
 338                 c->cputype = CPU_R2000;
 339                 __cpu_name[cpu] = "R2000";
 340                 c->isa_level = MIPS_CPU_ISA_I;
 341                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 342                              MIPS_CPU_NOFPUEX;
 343                 if (__cpu_has_fpu())
 344                         c->options |= MIPS_CPU_FPU;
 345                 c->tlbsize = 64;
 346                 break;
 347         case PRID_IMP_R3000:
 348                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 349                         if (cpu_has_confreg()) {
 350                                 c->cputype = CPU_R3081E;
 351                                 __cpu_name[cpu] = "R3081";
 352                         } else {
 353                                 c->cputype = CPU_R3000A;
 354                                 __cpu_name[cpu] = "R3000A";
 355                         }
 356                         break;
 357                 } else {
 358                         c->cputype = CPU_R3000;
 359                         __cpu_name[cpu] = "R3000";
 360                 }
 361                 c->isa_level = MIPS_CPU_ISA_I;
 362                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 363                              MIPS_CPU_NOFPUEX;
 364                 if (__cpu_has_fpu())
 365                         c->options |= MIPS_CPU_FPU;
 366                 c->tlbsize = 64;
 367                 break;
 368         case PRID_IMP_R4000:
 369                 if (read_c0_config() & CONF_SC) {
 370                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 371                                 c->cputype = CPU_R4400PC;
 372                                 __cpu_name[cpu] = "R4400PC";
 373                         } else {
 374                                 c->cputype = CPU_R4000PC;
 375                                 __cpu_name[cpu] = "R4000PC";
 376                         }
 377                 } else {
 378                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 379                                 c->cputype = CPU_R4400SC;
 380                                 __cpu_name[cpu] = "R4400SC";
 381                         } else {
 382                                 c->cputype = CPU_R4000SC;
 383                                 __cpu_name[cpu] = "R4000SC";
 384                         }
 385                 }
 386
 387                 c->isa_level = MIPS_CPU_ISA_III;
 388                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 389                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 390                              MIPS_CPU_LLSC;
 391                 c->tlbsize = 48;
 392                 break;
 393         case PRID_IMP_VR41XX:
 394                 switch (c->processor_id & 0xf0) {
 395                 case PRID_REV_VR4111:
 396                         c->cputype = CPU_VR4111;
 397                         __cpu_name[cpu] = "NEC VR4111";
 398                         break;
 399                 case PRID_REV_VR4121:
 400                         c->cputype = CPU_VR4121;
 401                         __cpu_name[cpu] = "NEC VR4121";
 402                         break;
 403                 case PRID_REV_VR4122:
 404                         if ((c->processor_id & 0xf) < 0x3) {
 405                                 c->cputype = CPU_VR4122;
 406                                 __cpu_name[cpu] = "NEC VR4122";
 407                         } else {
 408                                 c->cputype = CPU_VR4181A;
 409                                 __cpu_name[cpu] = "NEC VR4181A";
 410                         }
 411                         break;
 412                 case PRID_REV_VR4130:
 413                         if ((c->processor_id & 0xf) < 0x4) {
 414                                 c->cputype = CPU_VR4131;
 415                                 __cpu_name[cpu] = "NEC VR4131";
 416                         } else {
 417                                 c->cputype = CPU_VR4133;
 418                                 __cpu_name[cpu] = "NEC VR4133";
 419                         }
 420                         break;
 421                 default:
 422                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 423                         c->cputype = CPU_VR41XX;
 424                         __cpu_name[cpu] = "NEC Vr41xx";
 425                         break;
 426                 }
 427                 c->isa_level = MIPS_CPU_ISA_III;
 428                 c->options = R4K_OPTS;
 429                 c->tlbsize = 32;
 430                 break;
 431         case PRID_IMP_R4300:
 432                 c->cputype = CPU_R4300;
 433                 __cpu_name[cpu] = "R4300";
 434                 c->isa_level = MIPS_CPU_ISA_III;
 435                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 436                              MIPS_CPU_LLSC;
 437                 c->tlbsize = 32;
 438                 break;
 439         case PRID_IMP_R4600:
 440                 c->cputype = CPU_R4600;
 441                 __cpu_name[cpu] = "R4600";
 442                 c->isa_level = MIPS_CPU_ISA_III;
 443                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 444                              MIPS_CPU_LLSC;
 445                 c->tlbsize = 48;
 446                 break;
 447         #if 0
 448         case PRID_IMP_R4650:
 449                 /*
 450                  * This processor doesn't have an MMU, so it's not
 451                  * "real easy" to run Linux on it. It is left purely
 452                  * for documentation.  Commented out because it shares
 453                  * it's c0_prid id number with the TX3900.
 454                  */
 455                 c->cputype = CPU_R4650;
 456                 __cpu_name[cpu] = "R4650";
 457                 c->isa_level = MIPS_CPU_ISA_III;
 458                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 459                 c->tlbsize = 48;
 460                 break;
 461         #endif
 462         case PRID_IMP_TX39:
 463                 c->isa_level = MIPS_CPU_ISA_I;
 464                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 465
 466                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 467                         c->cputype = CPU_TX3927;
 468                         __cpu_name[cpu] = "TX3927";
 469                         c->tlbsize = 64;
 470                 } else {
 471                         switch (c->processor_id & 0xff) {
 472                         case PRID_REV_TX3912:
 473                                 c->cputype = CPU_TX3912;
 474                                 __cpu_name[cpu] = "TX3912";
 475                                 c->tlbsize = 32;
 476                                 break;
 477                         case PRID_REV_TX3922:
 478                                 c->cputype = CPU_TX3922;
 479                                 __cpu_name[cpu] = "TX3922";
 480                                 c->tlbsize = 64;
 481                                 break;
 482                         }
 483                 }
 484                 break;
 485         case PRID_IMP_R4700:
 486                 c->cputype = CPU_R4700;
 487                 __cpu_name[cpu] = "R4700";
 488                 c->isa_level = MIPS_CPU_ISA_III;
 489                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 490                              MIPS_CPU_LLSC;
 491                 c->tlbsize = 48;
 492                 break;
 493         case PRID_IMP_TX49:
 494                 c->cputype = CPU_TX49XX;
 495                 __cpu_name[cpu] = "R49XX";
 496                 c->isa_level = MIPS_CPU_ISA_III;
 497                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 498                 if (!(c->processor_id & 0x08))
 499                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 500                 c->tlbsize = 48;
 501                 break;
 502         case PRID_IMP_R5000:
 503                 c->cputype = CPU_R5000;
 504                 __cpu_name[cpu] = "R5000";
 505                 c->isa_level = MIPS_CPU_ISA_IV;
 506                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 507                              MIPS_CPU_LLSC;
 508                 c->tlbsize = 48;
 509                 break;
 510         case PRID_IMP_R5432:
 511                 c->cputype = CPU_R5432;
 512                 __cpu_name[cpu] = "R5432";
 513                 c->isa_level = MIPS_CPU_ISA_IV;
 514                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 515                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 516                 c->tlbsize = 48;
 517                 break;
 518         case PRID_IMP_R5500:
 519                 c->cputype = CPU_R5500;
 520                 __cpu_name[cpu] = "R5500";
 521                 c->isa_level = MIPS_CPU_ISA_IV;
 522                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 523                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 524                 c->tlbsize = 48;
 525                 break;
 526         case PRID_IMP_NEVADA:
 527                 c->cputype = CPU_NEVADA;
 528                 __cpu_name[cpu] = "Nevada";
 529                 c->isa_level = MIPS_CPU_ISA_IV;
 530                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 531                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 532                 c->tlbsize = 48;
 533                 break;
 534         case PRID_IMP_R6000:
 535                 c->cputype = CPU_R6000;
 536                 __cpu_name[cpu] = "R6000";
 537                 c->isa_level = MIPS_CPU_ISA_II;
 538                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 539                              MIPS_CPU_LLSC;
 540                 c->tlbsize = 32;
 541                 break;
 542         case PRID_IMP_R6000A:
 543                 c->cputype = CPU_R6000A;
 544                 __cpu_name[cpu] = "R6000A";
 545                 c->isa_level = MIPS_CPU_ISA_II;
 546                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 547                              MIPS_CPU_LLSC;
 548                 c->tlbsize = 32;
 549                 break;
 550         case PRID_IMP_RM7000:
 551                 c->cputype = CPU_RM7000;
 552                 __cpu_name[cpu] = "RM7000";
 553                 c->isa_level = MIPS_CPU_ISA_IV;
 554                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 555                              MIPS_CPU_LLSC;
 556                 /*
 557                  * Undocumented RM7000:  Bit 29 in the info register of
 558                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 559                  * entries.
 560                  *
 561                  * 29      1 =>    64 entry JTLB
 562                  *         0 =>    48 entry JTLB
 563                  */
 564                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 565                 break;
 566         case PRID_IMP_RM9000:
 567                 c->cputype = CPU_RM9000;
 568                 __cpu_name[cpu] = "RM9000";
 569                 c->isa_level = MIPS_CPU_ISA_IV;
 570                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 571                              MIPS_CPU_LLSC;
 572                 /*
 573                  * Bit 29 in the info register of the RM9000
 574                  * indicates if the TLB has 48 or 64 entries.
 575                  *
 576                  * 29      1 =>    64 entry JTLB
 577                  *         0 =>    48 entry JTLB
 578                  */
 579                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 580                 break;
 581         case PRID_IMP_R8000:
 582                 c->cputype = CPU_R8000;
 583                 __cpu_name[cpu] = "RM8000";
 584                 c->isa_level = MIPS_CPU_ISA_IV;
 585                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 586                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 587                              MIPS_CPU_LLSC;
 588                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 589                 break;
 590         case PRID_IMP_R10000:
 591                 c->cputype = CPU_R10000;
 592                 __cpu_name[cpu] = "R10000";
 593                 c->isa_level = MIPS_CPU_ISA_IV;
 594                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 595                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 596                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 597                              MIPS_CPU_LLSC;
 598                 c->tlbsize = 64;
 599                 break;
 600         case PRID_IMP_R12000:
 601                 c->cputype = CPU_R12000;
 602                 __cpu_name[cpu] = "R12000";
 603                 c->isa_level = MIPS_CPU_ISA_IV;
 604                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 605                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 606                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 607                              MIPS_CPU_LLSC;
 608                 c->tlbsize = 64;
 609                 break;
 610         case PRID_IMP_R14000:
 611                 c->cputype = CPU_R14000;
 612                 __cpu_name[cpu] = "R14000";
 613                 c->isa_level = MIPS_CPU_ISA_IV;
 614                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 615                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 616                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 617                              MIPS_CPU_LLSC;
 618                 c->tlbsize = 64;
 619                 break;
 620         case PRID_IMP_LOONGSON2:
 621                 c->cputype = CPU_LOONGSON2;
 622                 __cpu_name[cpu] = "ICT Loongson-2";
 623                 c->isa_level = MIPS_CPU_ISA_III;
 624                 c->options = R4K_OPTS |
 625                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 626                              MIPS_CPU_32FPR;
 627                 c->tlbsize = 64;
 628                 break;
 629         }
 630 }
 631
 632 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 633         "Unsupported ISA type, c0.config0: %d.";
 634
 635 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 636 {
 637         unsigned int config0;
 638         int isa;
 639
 640         config0 = read_c0_config();
 641
 642         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 643                 c->options |= MIPS_CPU_TLB;
 644         isa = (config0 & MIPS_CONF_AT) >> 13;
 645         switch (isa) {
 646         case 0:
 647                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 648                 case 0:
 649                         c->isa_level = MIPS_CPU_ISA_M32R1;
 650                         break;
 651                 case 1:
 652                         c->isa_level = MIPS_CPU_ISA_M32R2;
 653                         break;
 654                 default:
 655                         goto unknown;
 656                 }
 657                 break;
 658         case 2:
 659                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 660                 case 0:
 661                         c->isa_level = MIPS_CPU_ISA_M64R1;
 662                         break;
 663                 case 1:
 664                         c->isa_level = MIPS_CPU_ISA_M64R2;
 665                         break;
 666                 default:
 667                         goto unknown;
 668                 }
 669                 break;
 670         default:
 671                 goto unknown;
 672         }
 673
 674         return config0 & MIPS_CONF_M;
 675
 676 unknown:
 677         panic(unknown_isa, config0);
 678 }
 679
 680 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 681 {
 682         unsigned int config1;
 683
 684         config1 = read_c0_config1();
 685
 686         if (config1 & MIPS_CONF1_MD)
 687                 c->ases |= MIPS_ASE_MDMX;
 688         if (config1 & MIPS_CONF1_WR)
 689                 c->options |= MIPS_CPU_WATCH;
 690         if (config1 & MIPS_CONF1_CA)
 691                 c->ases |= MIPS_ASE_MIPS16;
 692         if (config1 & MIPS_CONF1_EP)
 693                 c->options |= MIPS_CPU_EJTAG;
 694         if (config1 & MIPS_CONF1_FP) {
 695                 c->options |= MIPS_CPU_FPU;
 696                 c->options |= MIPS_CPU_32FPR;
 697         }
 698         if (cpu_has_tlb)
 699                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 700
 701         return config1 & MIPS_CONF_M;
 702 }
 703
 704 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 705 {
 706         unsigned int config2;
 707
 708         config2 = read_c0_config2();
 709
 710         if (config2 & MIPS_CONF2_SL)
 711                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 712
 713         return config2 & MIPS_CONF_M;
 714 }
 715
 716 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 717 {
 718         unsigned int config3;
 719
 720         config3 = read_c0_config3();
 721
 722         if (config3 & MIPS_CONF3_SM)
 723                 c->ases |= MIPS_ASE_SMARTMIPS;
 724         if (config3 & MIPS_CONF3_DSP)
 725                 c->ases |= MIPS_ASE_DSP;
 726         if (config3 & MIPS_CONF3_VINT)
 727                 c->options |= MIPS_CPU_VINT;
 728         if (config3 & MIPS_CONF3_VEIC)
 729                 c->options |= MIPS_CPU_VEIC;
 730         if (config3 & MIPS_CONF3_MT)
 731                 c->ases |= MIPS_ASE_MIPSMT;
 732         if (config3 & MIPS_CONF3_ULRI)
 733                 c->options |= MIPS_CPU_ULRI;
 734
 735         return config3 & MIPS_CONF_M;
 736 }
 737
 738 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 739 {
 740         unsigned int config4;
 741
 742         config4 = read_c0_config4();
 743
 744         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 745             && cpu_has_tlb)
 746                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 747
 748         c->kscratch_mask = (config4 >> 16) & 0xff;
 749
 750         return config4 & MIPS_CONF_M;
 751 }
 752
 753 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 754 {
 755         int ok;
 756
 757         /* MIPS32 or MIPS64 compliant CPU.  */
 758         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 759                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 760
 761         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 762
 763         ok = decode_config0(c);                 /* Read Config registers.  */
 764         BUG_ON(!ok);                            /* Arch spec violation!  */
 765         if (ok)
 766                 ok = decode_config1(c);
 767         if (ok)
 768                 ok = decode_config2(c);
 769         if (ok)
 770                 ok = decode_config3(c);
 771         if (ok)
 772                 ok = decode_config4(c);
 773
 774         mips_probe_watch_registers(c);
 775
 776         if (cpu_has_mips_r2)
 777                 c->core = read_c0_ebase() & 0x3ff;
 778 }
 779
 780 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 781 {
 782         decode_configs(c);
 783         switch (c->processor_id & 0xff00) {
 784         case PRID_IMP_4KC:
 785                 c->cputype = CPU_4KC;
 786                 __cpu_name[cpu] = "MIPS 4Kc";
 787                 break;
 788         case PRID_IMP_4KEC:
 789         case PRID_IMP_4KECR2:
 790                 c->cputype = CPU_4KEC;
 791                 __cpu_name[cpu] = "MIPS 4KEc";
 792                 break;
 793         case PRID_IMP_4KSC:
 794         case PRID_IMP_4KSD:
 795                 c->cputype = CPU_4KSC;
 796                 __cpu_name[cpu] = "MIPS 4KSc";
 797                 break;
 798         case PRID_IMP_5KC:
 799                 c->cputype = CPU_5KC;
 800                 __cpu_name[cpu] = "MIPS 5Kc";
 801                 break;
 802         case PRID_IMP_20KC:
 803                 c->cputype = CPU_20KC;
 804                 __cpu_name[cpu] = "MIPS 20Kc";
 805                 break;
 806         case PRID_IMP_24K:
 807         case PRID_IMP_24KE:
 808                 c->cputype = CPU_24K;
 809                 __cpu_name[cpu] = "MIPS 24Kc";
 810                 break;
 811         case PRID_IMP_25KF:
 812                 c->cputype = CPU_25KF;
 813                 __cpu_name[cpu] = "MIPS 25Kc";
 814                 break;
 815         case PRID_IMP_34K:
 816                 c->cputype = CPU_34K;
 817                 __cpu_name[cpu] = "MIPS 34Kc";
 818                 break;
 819         case PRID_IMP_74K:
 820                 c->cputype = CPU_74K;
 821                 __cpu_name[cpu] = "MIPS 74Kc";
 822                 break;
 823         case PRID_IMP_1004K:
 824                 c->cputype = CPU_1004K;
 825                 __cpu_name[cpu] = "MIPS 1004Kc";
 826                 break;
 827         }
 828
 829         spram_config();
 830 }
 831
 832 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 833 {
 834         decode_configs(c);
 835         switch (c->processor_id & 0xff00) {
 836         case PRID_IMP_AU1_REV1:
 837         case PRID_IMP_AU1_REV2:
 838                 c->cputype = CPU_ALCHEMY;
 839                 switch ((c->processor_id >> 24) & 0xff) {
 840                 case 0:
 841                         __cpu_name[cpu] = "Au1000";
 842                         break;
 843                 case 1:
 844                         __cpu_name[cpu] = "Au1500";
 845                         break;
 846                 case 2:
 847                         __cpu_name[cpu] = "Au1100";
 848                         break;
 849                 case 3:
 850                         __cpu_name[cpu] = "Au1550";
 851                         break;
 852                 case 4:
 853                         __cpu_name[cpu] = "Au1200";
 854                         if ((c->processor_id & 0xff) == 2)
 855                                 __cpu_name[cpu] = "Au1250";
 856                         break;
 857                 case 5:
 858                         __cpu_name[cpu] = "Au1210";
 859                         break;
 860                 default:
 861                         __cpu_name[cpu] = "Au1xxx";
 862                         break;
 863                 }
 864                 break;
 865         }
 866 }
 867
 868 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 869 {
 870         decode_configs(c);
 871
 872         switch (c->processor_id & 0xff00) {
 873         case PRID_IMP_SB1:
 874                 c->cputype = CPU_SB1;
 875                 __cpu_name[cpu] = "SiByte SB1";
 876                 /* FPU in pass1 is known to have issues. */
 877                 if ((c->processor_id & 0xff) < 0x02)
 878                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 879                 break;
 880         case PRID_IMP_SB1A:
 881                 c->cputype = CPU_SB1A;
 882                 __cpu_name[cpu] = "SiByte SB1A";
 883                 break;
 884         }
 885 }
 886
 887 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 888 {
 889         decode_configs(c);
 890         switch (c->processor_id & 0xff00) {
 891         case PRID_IMP_SR71000:
 892                 c->cputype = CPU_SR71000;
 893                 __cpu_name[cpu] = "Sandcraft SR71000";
 894                 c->scache.ways = 8;
 895                 c->tlbsize = 64;
 896                 break;
 897         }
 898 }
 899
 900 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 901 {
 902         decode_configs(c);
 903         switch (c->processor_id & 0xff00) {
 904         case PRID_IMP_PR4450:
 905                 c->cputype = CPU_PR4450;
 906                 __cpu_name[cpu] = "Philips PR4450";
 907                 c->isa_level = MIPS_CPU_ISA_M32R1;
 908                 break;
 909         }
 910 }
 911
 912 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 913 {
 914         decode_configs(c);
 915         switch (c->processor_id & 0xff00) {
 916         case PRID_IMP_BMIPS32_REV4:
 917         case PRID_IMP_BMIPS32_REV8:
 918                 c->cputype = CPU_BMIPS32;
 919                 __cpu_name[cpu] = "Broadcom BMIPS32";
 920                 set_elf_platform(cpu, "bmips32");
 921                 break;
 922         case PRID_IMP_BMIPS3300:
 923         case PRID_IMP_BMIPS3300_ALT:
 924         case PRID_IMP_BMIPS3300_BUG:
 925                 c->cputype = CPU_BMIPS3300;
 926                 __cpu_name[cpu] = "Broadcom BMIPS3300";
 927                 set_elf_platform(cpu, "bmips3300");
 928                 break;
 929         case PRID_IMP_BMIPS43XX: {
 930                 int rev = c->processor_id & 0xff;
 931
 932                 if (rev >= PRID_REV_BMIPS4380_LO &&
 933                                 rev <= PRID_REV_BMIPS4380_HI) {
 934                         c->cputype = CPU_BMIPS4380;
 935                         __cpu_name[cpu] = "Broadcom BMIPS4380";
 936                         set_elf_platform(cpu, "bmips4380");
 937                 } else {
 938                         c->cputype = CPU_BMIPS4350;
 939                         __cpu_name[cpu] = "Broadcom BMIPS4350";
 940                         set_elf_platform(cpu, "bmips4350");
 941                 }
 942                 break;
 943         }
 944         case PRID_IMP_BMIPS5000:
 945                 c->cputype = CPU_BMIPS5000;
 946                 __cpu_name[cpu] = "Broadcom BMIPS5000";
 947                 set_elf_platform(cpu, "bmips5000");
 948                 c->options |= MIPS_CPU_ULRI;
 949                 break;
 950         }
 951 }
 952
 953 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 954 {
 955         decode_configs(c);
 956         switch (c->processor_id & 0xff00) {
 957         case PRID_IMP_CAVIUM_CN38XX:
 958         case PRID_IMP_CAVIUM_CN31XX:
 959         case PRID_IMP_CAVIUM_CN30XX:
 960                 c->cputype = CPU_CAVIUM_OCTEON;
 961                 __cpu_name[cpu] = "Cavium Octeon";
 962                 goto platform;
 963         case PRID_IMP_CAVIUM_CN58XX:
 964         case PRID_IMP_CAVIUM_CN56XX:
 965         case PRID_IMP_CAVIUM_CN50XX:
 966         case PRID_IMP_CAVIUM_CN52XX:
 967                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 968                 __cpu_name[cpu] = "Cavium Octeon+";
 969 platform:
 970                 set_elf_platform(cpu, "octeon");
 971                 break;
 972         case PRID_IMP_CAVIUM_CN63XX:
 973                 c->cputype = CPU_CAVIUM_OCTEON2;
 974                 __cpu_name[cpu] = "Cavium Octeon II";
 975                 set_elf_platform(cpu, "octeon2");
 976                 break;
 977         default:
 978                 printk(KERN_INFO "Unknown Octeon chip!\n");
 979                 c->cputype = CPU_UNKNOWN;
 980                 break;
 981         }
 982 }
 983
 984 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 985 {
 986         decode_configs(c);
 987         /* JZRISC does not implement the CP0 counter. */
 988         c->options &= ~MIPS_CPU_COUNTER;
 989         switch (c->processor_id & 0xff00) {
 990         case PRID_IMP_JZRISC:
 991                 c->cputype = CPU_JZRISC;
 992                 __cpu_name[cpu] = "Ingenic JZRISC";
 993                 break;
 994         default:
 995                 panic("Unknown Ingenic Processor ID!");
 996                 break;
 997         }
 998 }
 999
1000 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1001 {
1002         decode_configs(c);
1003
1004         c->options = (MIPS_CPU_TLB       |
1005                         MIPS_CPU_4KEX    |
1006                         MIPS_CPU_COUNTER |
1007                         MIPS_CPU_DIVEC   |
1008                         MIPS_CPU_WATCH   |
1009                         MIPS_CPU_EJTAG   |
1010                         MIPS_CPU_LLSC);
1011
1012         switch (c->processor_id & 0xff00) {
1013         case PRID_IMP_NETLOGIC_XLR732:
1014         case PRID_IMP_NETLOGIC_XLR716:
1015         case PRID_IMP_NETLOGIC_XLR532:
1016         case PRID_IMP_NETLOGIC_XLR308:
1017         case PRID_IMP_NETLOGIC_XLR532C:
1018         case PRID_IMP_NETLOGIC_XLR516C:
1019         case PRID_IMP_NETLOGIC_XLR508C:
1020         case PRID_IMP_NETLOGIC_XLR308C:
1021                 c->cputype = CPU_XLR;
1022                 __cpu_name[cpu] = "Netlogic XLR";
1023                 break;
1024
1025         case PRID_IMP_NETLOGIC_XLS608:
1026         case PRID_IMP_NETLOGIC_XLS408:
1027         case PRID_IMP_NETLOGIC_XLS404:
1028         case PRID_IMP_NETLOGIC_XLS208:
1029         case PRID_IMP_NETLOGIC_XLS204:
1030         case PRID_IMP_NETLOGIC_XLS108:
1031         case PRID_IMP_NETLOGIC_XLS104:
1032         case PRID_IMP_NETLOGIC_XLS616B:
1033         case PRID_IMP_NETLOGIC_XLS608B:
1034         case PRID_IMP_NETLOGIC_XLS416B:
1035         case PRID_IMP_NETLOGIC_XLS412B:
1036         case PRID_IMP_NETLOGIC_XLS408B:
1037         case PRID_IMP_NETLOGIC_XLS404B:
1038                 c->cputype = CPU_XLR;
1039                 __cpu_name[cpu] = "Netlogic XLS";
1040                 break;
1041
1042         default:
1043                 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
1044                        c->processor_id);
1045                 c->cputype = CPU_XLR;
1046                 break;
1047         }
1048
1049         c->isa_level = MIPS_CPU_ISA_M64R1;
1050         c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1051 }
1052
1053 #ifdef CONFIG_64BIT
1054 /* For use by uaccess.h */
1055 u64 __ua_limit;
1056 EXPORT_SYMBOL(__ua_limit);
1057 #endif
1058
1059 const char *__cpu_name[NR_CPUS];
1060 const char *__elf_platform;
1061
1062 __cpuinit void cpu_probe(void)
1063 {
1064         struct cpuinfo_mips *c = &current_cpu_data;
1065         unsigned int cpu = smp_processor_id();
1066
1067         c->processor_id = PRID_IMP_UNKNOWN;
1068         c->fpu_id       = FPIR_IMP_NONE;
1069         c->cputype      = CPU_UNKNOWN;
1070
1071         c->processor_id = read_c0_prid();
1072         switch (c->processor_id & 0xff0000) {
1073         case PRID_COMP_LEGACY:
1074                 cpu_probe_legacy(c, cpu);
1075                 break;
1076         case PRID_COMP_MIPS:
1077                 cpu_probe_mips(c, cpu);
1078                 break;
1079         case PRID_COMP_ALCHEMY:
1080                 cpu_probe_alchemy(c, cpu);
1081                 break;
1082         case PRID_COMP_SIBYTE:
1083                 cpu_probe_sibyte(c, cpu);
1084                 break;
1085         case PRID_COMP_BROADCOM:
1086                 cpu_probe_broadcom(c, cpu);
1087                 break;
1088         case PRID_COMP_SANDCRAFT:
1089                 cpu_probe_sandcraft(c, cpu);
1090                 break;
1091         case PRID_COMP_NXP:
1092                 cpu_probe_nxp(c, cpu);
1093                 break;
1094         case PRID_COMP_CAVIUM:
1095                 cpu_probe_cavium(c, cpu);
1096                 break;
1097         case PRID_COMP_INGENIC:
1098                 cpu_probe_ingenic(c, cpu);
1099                 break;
1100         case PRID_COMP_NETLOGIC:
1101                 cpu_probe_netlogic(c, cpu);
1102                 break;
1103         }
1104
1105         BUG_ON(!__cpu_name[cpu]);
1106         BUG_ON(c->cputype == CPU_UNKNOWN);
1107
1108         /*
1109          * Platform code can force the cpu type to optimize code
1110          * generation. In that case be sure the cpu type is correctly
1111          * manually setup otherwise it could trigger some nasty bugs.
1112          */
1113         BUG_ON(current_cpu_type() != c->cputype);
1114
1115         if (mips_fpu_disabled)
1116                 c->options &= ~MIPS_CPU_FPU;
1117
1118         if (mips_dsp_disabled)
1119                 c->ases &= ~MIPS_ASE_DSP;
1120
1121         if (c->options & MIPS_CPU_FPU) {
1122                 c->fpu_id = cpu_get_fpu_id();
1123
1124                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1125                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1126                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1127                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1128                         if (c->fpu_id & MIPS_FPIR_3D)
1129                                 c->ases |= MIPS_ASE_MIPS3D;
1130                 }
1131         }
1132
1133         if (cpu_has_mips_r2)
1134                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1135         else
1136                 c->srsets = 1;
1137
1138         cpu_probe_vmbits(c);
1139
1140 #ifdef CONFIG_64BIT
1141         if (cpu == 0)
1142                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1143 #endif
1144 }
1145
1146 __cpuinit void cpu_report(void)
1147 {
1148         struct cpuinfo_mips *c = &current_cpu_data;
1149
1150         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1151                c->processor_id, cpu_name_string());
1152         if (c->options & MIPS_CPU_FPU)
1153                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1154 }