arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/fpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/watch.h>
  26 #include <asm/elf.h>
  27 #include <asm/spram.h>
  28 #include <asm/uaccess.h>
  29
  30 static int __cpuinitdata mips_fpu_disabled;
  31
  32 static int __init fpu_disable(char *s)
  33 {
  34         cpu_data[0].options &= ~MIPS_CPU_FPU;
  35         mips_fpu_disabled = 1;
  36
  37         return 1;
  38 }
  39
  40 __setup("nofpu", fpu_disable);
  41
  42 int __cpuinitdata mips_dsp_disabled;
  43
  44 static int __init dsp_disable(char *s)
  45 {
  46         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
  47         mips_dsp_disabled = 1;
  48
  49         return 1;
  50 }
  51
  52 __setup("nodsp", dsp_disable);
  53
  54 static inline void check_errata(void)
  55 {
  56         struct cpuinfo_mips *c = &current_cpu_data;
  57
  58         switch (c->cputype) {
  59         case CPU_34K:
  60                 /*
  61                  * Erratum "RPS May Cause Incorrect Instruction Execution"
  62                  * This code only handles VPE0, any SMP/SMTC/RTOS code
  63                  * making use of VPE1 will be responsable for that VPE.
  64                  */
  65                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
  66                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
  67                 break;
  68         default:
  69                 break;
  70         }
  71 }
  72
  73 void __init check_bugs32(void)
  74 {
  75         check_errata();
  76 }
  77
  78 /*
  79  * Probe whether cpu has config register by trying to play with
  80  * alternate cache bit and see whether it matters.
  81  * It's used by cpu_probe to distinguish between R3000A and R3081.
  82  */
  83 static inline int cpu_has_confreg(void)
  84 {
  85 #ifdef CONFIG_CPU_R3000
  86         extern unsigned long r3k_cache_size(unsigned long);
  87         unsigned long size1, size2;
  88         unsigned long cfg = read_c0_conf();
  89
  90         size1 = r3k_cache_size(ST0_ISC);
  91         write_c0_conf(cfg ^ R30XX_CONF_AC);
  92         size2 = r3k_cache_size(ST0_ISC);
  93         write_c0_conf(cfg);
  94         return size1 != size2;
  95 #else
  96         return 0;
  97 #endif
  98 }
  99
 100 static inline void set_elf_platform(int cpu, const char *plat)
 101 {
 102         if (cpu == 0)
 103                 __elf_platform = plat;
 104 }
 105
 106 /*
 107  * Get the FPU Implementation/Revision.
 108  */
 109 static inline unsigned long cpu_get_fpu_id(void)
 110 {
 111         unsigned long tmp, fpu_id;
 112
 113         tmp = read_c0_status();
 114         __enable_fpu();
 115         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 116         write_c0_status(tmp);
 117         return fpu_id;
 118 }
 119
 120 /*
 121  * Check the CPU has an FPU the official way.
 122  */
 123 static inline int __cpu_has_fpu(void)
 124 {
 125         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 126 }
 127
 128 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 129 {
 130 #ifdef __NEED_VMBITS_PROBE
 131         write_c0_entryhi(0x3fffffffffffe000ULL);
 132         back_to_back_c0_hazard();
 133         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 134 #endif
 135 }
 136
 137 static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
 138 {
 139         switch (isa) {
 140         case MIPS_CPU_ISA_M64R2:
 141                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 142         case MIPS_CPU_ISA_M64R1:
 143                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 144         case MIPS_CPU_ISA_V:
 145                 c->isa_level |= MIPS_CPU_ISA_V;
 146         case MIPS_CPU_ISA_IV:
 147                 c->isa_level |= MIPS_CPU_ISA_IV;
 148         case MIPS_CPU_ISA_III:
 149                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 150                 break;
 151
 152         case MIPS_CPU_ISA_M32R2:
 153                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 154         case MIPS_CPU_ISA_M32R1:
 155                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 156         case MIPS_CPU_ISA_II:
 157                 c->isa_level |= MIPS_CPU_ISA_II;
 158                 break;
 159         }
 160 }
 161
 162 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 163         "Unsupported ISA type, c0.config0: %d.";
 164
 165 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 166 {
 167         unsigned int config0;
 168         int isa;
 169
 170         config0 = read_c0_config();
 171
 172         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 173                 c->options |= MIPS_CPU_TLB;
 174         isa = (config0 & MIPS_CONF_AT) >> 13;
 175         switch (isa) {
 176         case 0:
 177                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 178                 case 0:
 179                         set_isa(c, MIPS_CPU_ISA_M32R1);
 180                         break;
 181                 case 1:
 182                         set_isa(c, MIPS_CPU_ISA_M32R2);
 183                         break;
 184                 default:
 185                         goto unknown;
 186                 }
 187                 break;
 188         case 2:
 189                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 190                 case 0:
 191                         set_isa(c, MIPS_CPU_ISA_M64R1);
 192                         break;
 193                 case 1:
 194                         set_isa(c, MIPS_CPU_ISA_M64R2);
 195                         break;
 196                 default:
 197                         goto unknown;
 198                 }
 199                 break;
 200         default:
 201                 goto unknown;
 202         }
 203
 204         return config0 & MIPS_CONF_M;
 205
 206 unknown:
 207         panic(unknown_isa, config0);
 208 }
 209
 210 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 211 {
 212         unsigned int config1;
 213
 214         config1 = read_c0_config1();
 215
 216         if (config1 & MIPS_CONF1_MD)
 217                 c->ases |= MIPS_ASE_MDMX;
 218         if (config1 & MIPS_CONF1_WR)
 219                 c->options |= MIPS_CPU_WATCH;
 220         if (config1 & MIPS_CONF1_CA)
 221                 c->ases |= MIPS_ASE_MIPS16;
 222         if (config1 & MIPS_CONF1_EP)
 223                 c->options |= MIPS_CPU_EJTAG;
 224         if (config1 & MIPS_CONF1_FP) {
 225                 c->options |= MIPS_CPU_FPU;
 226                 c->options |= MIPS_CPU_32FPR;
 227         }
 228         if (cpu_has_tlb)
 229                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 230
 231         return config1 & MIPS_CONF_M;
 232 }
 233
 234 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 235 {
 236         unsigned int config2;
 237
 238         config2 = read_c0_config2();
 239
 240         if (config2 & MIPS_CONF2_SL)
 241                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 242
 243         return config2 & MIPS_CONF_M;
 244 }
 245
 246 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 247 {
 248         unsigned int config3;
 249
 250         config3 = read_c0_config3();
 251
 252         if (config3 & MIPS_CONF3_SM) {
 253                 c->ases |= MIPS_ASE_SMARTMIPS;
 254                 c->options |= MIPS_CPU_RIXI;
 255         }
 256         if (config3 & MIPS_CONF3_RXI)
 257                 c->options |= MIPS_CPU_RIXI;
 258         if (config3 & MIPS_CONF3_DSP)
 259                 c->ases |= MIPS_ASE_DSP;
 260         if (config3 & MIPS_CONF3_DSP2P)
 261                 c->ases |= MIPS_ASE_DSP2P;
 262         if (config3 & MIPS_CONF3_VINT)
 263                 c->options |= MIPS_CPU_VINT;
 264         if (config3 & MIPS_CONF3_VEIC)
 265                 c->options |= MIPS_CPU_VEIC;
 266         if (config3 & MIPS_CONF3_MT)
 267                 c->ases |= MIPS_ASE_MIPSMT;
 268         if (config3 & MIPS_CONF3_ULRI)
 269                 c->options |= MIPS_CPU_ULRI;
 270         if (config3 & MIPS_CONF3_ISA)
 271                 c->options |= MIPS_CPU_MICROMIPS;
 272         if (config3 & MIPS_CONF3_VZ)
 273                 c->ases |= MIPS_ASE_VZ;
 274
 275         return config3 & MIPS_CONF_M;
 276 }
 277
 278 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 279 {
 280         unsigned int config4;
 281
 282         config4 = read_c0_config4();
 283
 284         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 285             && cpu_has_tlb)
 286                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 287
 288         c->kscratch_mask = (config4 >> 16) & 0xff;
 289
 290         return config4 & MIPS_CONF_M;
 291 }
 292
 293 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 294 {
 295         int ok;
 296
 297         /* MIPS32 or MIPS64 compliant CPU.  */
 298         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 299                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 300
 301         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 302
 303         ok = decode_config0(c);                 /* Read Config registers.  */
 304         BUG_ON(!ok);                            /* Arch spec violation!  */
 305         if (ok)
 306                 ok = decode_config1(c);
 307         if (ok)
 308                 ok = decode_config2(c);
 309         if (ok)
 310                 ok = decode_config3(c);
 311         if (ok)
 312                 ok = decode_config4(c);
 313
 314         mips_probe_watch_registers(c);
 315
 316         if (cpu_has_mips_r2)
 317                 c->core = read_c0_ebase() & 0x3ff;
 318 }
 319
 320 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 321                 | MIPS_CPU_COUNTER)
 322
 323 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 324 {
 325         switch (c->processor_id & 0xff00) {
 326         case PRID_IMP_R2000:
 327                 c->cputype = CPU_R2000;
 328                 __cpu_name[cpu] = "R2000";
 329                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 330                              MIPS_CPU_NOFPUEX;
 331                 if (__cpu_has_fpu())
 332                         c->options |= MIPS_CPU_FPU;
 333                 c->tlbsize = 64;
 334                 break;
 335         case PRID_IMP_R3000:
 336                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 337                         if (cpu_has_confreg()) {
 338                                 c->cputype = CPU_R3081E;
 339                                 __cpu_name[cpu] = "R3081";
 340                         } else {
 341                                 c->cputype = CPU_R3000A;
 342                                 __cpu_name[cpu] = "R3000A";
 343                         }
 344                 } else {
 345                         c->cputype = CPU_R3000;
 346                         __cpu_name[cpu] = "R3000";
 347                 }
 348                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 349                              MIPS_CPU_NOFPUEX;
 350                 if (__cpu_has_fpu())
 351                         c->options |= MIPS_CPU_FPU;
 352                 c->tlbsize = 64;
 353                 break;
 354         case PRID_IMP_R4000:
 355                 if (read_c0_config() & CONF_SC) {
 356                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 357                                 c->cputype = CPU_R4400PC;
 358                                 __cpu_name[cpu] = "R4400PC";
 359                         } else {
 360                                 c->cputype = CPU_R4000PC;
 361                                 __cpu_name[cpu] = "R4000PC";
 362                         }
 363                 } else {
 364                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 365                                 c->cputype = CPU_R4400SC;
 366                                 __cpu_name[cpu] = "R4400SC";
 367                         } else {
 368                                 c->cputype = CPU_R4000SC;
 369                                 __cpu_name[cpu] = "R4000SC";
 370                         }
 371                 }
 372
 373                 set_isa(c, MIPS_CPU_ISA_III);
 374                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 375                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 376                              MIPS_CPU_LLSC;
 377                 c->tlbsize = 48;
 378                 break;
 379         case PRID_IMP_VR41XX:
 380                 set_isa(c, MIPS_CPU_ISA_III);
 381                 c->options = R4K_OPTS;
 382                 c->tlbsize = 32;
 383                 switch (c->processor_id & 0xf0) {
 384                 case PRID_REV_VR4111:
 385                         c->cputype = CPU_VR4111;
 386                         __cpu_name[cpu] = "NEC VR4111";
 387                         break;
 388                 case PRID_REV_VR4121:
 389                         c->cputype = CPU_VR4121;
 390                         __cpu_name[cpu] = "NEC VR4121";
 391                         break;
 392                 case PRID_REV_VR4122:
 393                         if ((c->processor_id & 0xf) < 0x3) {
 394                                 c->cputype = CPU_VR4122;
 395                                 __cpu_name[cpu] = "NEC VR4122";
 396                         } else {
 397                                 c->cputype = CPU_VR4181A;
 398                                 __cpu_name[cpu] = "NEC VR4181A";
 399                         }
 400                         break;
 401                 case PRID_REV_VR4130:
 402                         if ((c->processor_id & 0xf) < 0x4) {
 403                                 c->cputype = CPU_VR4131;
 404                                 __cpu_name[cpu] = "NEC VR4131";
 405                         } else {
 406                                 c->cputype = CPU_VR4133;
 407                                 c->options |= MIPS_CPU_LLSC;
 408                                 __cpu_name[cpu] = "NEC VR4133";
 409                         }
 410                         break;
 411                 default:
 412                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 413                         c->cputype = CPU_VR41XX;
 414                         __cpu_name[cpu] = "NEC Vr41xx";
 415                         break;
 416                 }
 417                 break;
 418         case PRID_IMP_R4300:
 419                 c->cputype = CPU_R4300;
 420                 __cpu_name[cpu] = "R4300";
 421                 set_isa(c, MIPS_CPU_ISA_III);
 422                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 423                              MIPS_CPU_LLSC;
 424                 c->tlbsize = 32;
 425                 break;
 426         case PRID_IMP_R4600:
 427                 c->cputype = CPU_R4600;
 428                 __cpu_name[cpu] = "R4600";
 429                 set_isa(c, MIPS_CPU_ISA_III);
 430                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 431                              MIPS_CPU_LLSC;
 432                 c->tlbsize = 48;
 433                 break;
 434         #if 0
 435         case PRID_IMP_R4650:
 436                 /*
 437                  * This processor doesn't have an MMU, so it's not
 438                  * "real easy" to run Linux on it. It is left purely
 439                  * for documentation.  Commented out because it shares
 440                  * it's c0_prid id number with the TX3900.
 441                  */
 442                 c->cputype = CPU_R4650;
 443                 __cpu_name[cpu] = "R4650";
 444                 set_isa(c, MIPS_CPU_ISA_III);
 445                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 446                 c->tlbsize = 48;
 447                 break;
 448         #endif
 449         case PRID_IMP_TX39:
 450                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 451
 452                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 453                         c->cputype = CPU_TX3927;
 454                         __cpu_name[cpu] = "TX3927";
 455                         c->tlbsize = 64;
 456                 } else {
 457                         switch (c->processor_id & 0xff) {
 458                         case PRID_REV_TX3912:
 459                                 c->cputype = CPU_TX3912;
 460                                 __cpu_name[cpu] = "TX3912";
 461                                 c->tlbsize = 32;
 462                                 break;
 463                         case PRID_REV_TX3922:
 464                                 c->cputype = CPU_TX3922;
 465                                 __cpu_name[cpu] = "TX3922";
 466                                 c->tlbsize = 64;
 467                                 break;
 468                         }
 469                 }
 470                 break;
 471         case PRID_IMP_R4700:
 472                 c->cputype = CPU_R4700;
 473                 __cpu_name[cpu] = "R4700";
 474                 set_isa(c, MIPS_CPU_ISA_III);
 475                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 476                              MIPS_CPU_LLSC;
 477                 c->tlbsize = 48;
 478                 break;
 479         case PRID_IMP_TX49:
 480                 c->cputype = CPU_TX49XX;
 481                 __cpu_name[cpu] = "R49XX";
 482                 set_isa(c, MIPS_CPU_ISA_III);
 483                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 484                 if (!(c->processor_id & 0x08))
 485                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 486                 c->tlbsize = 48;
 487                 break;
 488         case PRID_IMP_R5000:
 489                 c->cputype = CPU_R5000;
 490                 __cpu_name[cpu] = "R5000";
 491                 set_isa(c, MIPS_CPU_ISA_IV);
 492                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 493                              MIPS_CPU_LLSC;
 494                 c->tlbsize = 48;
 495                 break;
 496         case PRID_IMP_R5432:
 497                 c->cputype = CPU_R5432;
 498                 __cpu_name[cpu] = "R5432";
 499                 set_isa(c, MIPS_CPU_ISA_IV);
 500                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 501                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 502                 c->tlbsize = 48;
 503                 break;
 504         case PRID_IMP_R5500:
 505                 c->cputype = CPU_R5500;
 506                 __cpu_name[cpu] = "R5500";
 507                 set_isa(c, MIPS_CPU_ISA_IV);
 508                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 509                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 510                 c->tlbsize = 48;
 511                 break;
 512         case PRID_IMP_NEVADA:
 513                 c->cputype = CPU_NEVADA;
 514                 __cpu_name[cpu] = "Nevada";
 515                 set_isa(c, MIPS_CPU_ISA_IV);
 516                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 517                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 518                 c->tlbsize = 48;
 519                 break;
 520         case PRID_IMP_R6000:
 521                 c->cputype = CPU_R6000;
 522                 __cpu_name[cpu] = "R6000";
 523                 set_isa(c, MIPS_CPU_ISA_II);
 524                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 525                              MIPS_CPU_LLSC;
 526                 c->tlbsize = 32;
 527                 break;
 528         case PRID_IMP_R6000A:
 529                 c->cputype = CPU_R6000A;
 530                 __cpu_name[cpu] = "R6000A";
 531                 set_isa(c, MIPS_CPU_ISA_II);
 532                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 533                              MIPS_CPU_LLSC;
 534                 c->tlbsize = 32;
 535                 break;
 536         case PRID_IMP_RM7000:
 537                 c->cputype = CPU_RM7000;
 538                 __cpu_name[cpu] = "RM7000";
 539                 set_isa(c, MIPS_CPU_ISA_IV);
 540                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 541                              MIPS_CPU_LLSC;
 542                 /*
 543                  * Undocumented RM7000:  Bit 29 in the info register of
 544                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 545                  * entries.
 546                  *
 547                  * 29      1 =>    64 entry JTLB
 548                  *         0 =>    48 entry JTLB
 549                  */
 550                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 551                 break;
 552         case PRID_IMP_RM9000:
 553                 c->cputype = CPU_RM9000;
 554                 __cpu_name[cpu] = "RM9000";
 555                 set_isa(c, MIPS_CPU_ISA_IV);
 556                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 557                              MIPS_CPU_LLSC;
 558                 /*
 559                  * Bit 29 in the info register of the RM9000
 560                  * indicates if the TLB has 48 or 64 entries.
 561                  *
 562                  * 29      1 =>    64 entry JTLB
 563                  *         0 =>    48 entry JTLB
 564                  */
 565                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 566                 break;
 567         case PRID_IMP_R8000:
 568                 c->cputype = CPU_R8000;
 569                 __cpu_name[cpu] = "RM8000";
 570                 set_isa(c, MIPS_CPU_ISA_IV);
 571                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 572                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 573                              MIPS_CPU_LLSC;
 574                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 575                 break;
 576         case PRID_IMP_R10000:
 577                 c->cputype = CPU_R10000;
 578                 __cpu_name[cpu] = "R10000";
 579                 set_isa(c, MIPS_CPU_ISA_IV);
 580                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 581                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 582                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 583                              MIPS_CPU_LLSC;
 584                 c->tlbsize = 64;
 585                 break;
 586         case PRID_IMP_R12000:
 587                 c->cputype = CPU_R12000;
 588                 __cpu_name[cpu] = "R12000";
 589                 set_isa(c, MIPS_CPU_ISA_IV);
 590                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 591                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 592                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 593                              MIPS_CPU_LLSC;
 594                 c->tlbsize = 64;
 595                 break;
 596         case PRID_IMP_R14000:
 597                 c->cputype = CPU_R14000;
 598                 __cpu_name[cpu] = "R14000";
 599                 set_isa(c, MIPS_CPU_ISA_IV);
 600                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 601                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 602                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 603                              MIPS_CPU_LLSC;
 604                 c->tlbsize = 64;
 605                 break;
 606         case PRID_IMP_LOONGSON2:
 607                 c->cputype = CPU_LOONGSON2;
 608                 __cpu_name[cpu] = "ICT Loongson-2";
 609
 610                 switch (c->processor_id & PRID_REV_MASK) {
 611                 case PRID_REV_LOONGSON2E:
 612                         set_elf_platform(cpu, "loongson2e");
 613                         break;
 614                 case PRID_REV_LOONGSON2F:
 615                         set_elf_platform(cpu, "loongson2f");
 616                         break;
 617                 }
 618
 619                 set_isa(c, MIPS_CPU_ISA_III);
 620                 c->options = R4K_OPTS |
 621                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 622                              MIPS_CPU_32FPR;
 623                 c->tlbsize = 64;
 624                 break;
 625         case PRID_IMP_LOONGSON1:
 626                 decode_configs(c);
 627
 628                 c->cputype = CPU_LOONGSON1;
 629
 630                 switch (c->processor_id & PRID_REV_MASK) {
 631                 case PRID_REV_LOONGSON1B:
 632                         __cpu_name[cpu] = "Loongson 1B";
 633                         break;
 634                 }
 635
 636                 break;
 637         }
 638 }
 639
 640 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 641 {
 642         decode_configs(c);
 643         switch (c->processor_id & 0xff00) {
 644         case PRID_IMP_4KC:
 645                 c->cputype = CPU_4KC;
 646                 __cpu_name[cpu] = "MIPS 4Kc";
 647                 break;
 648         case PRID_IMP_4KEC:
 649         case PRID_IMP_4KECR2:
 650                 c->cputype = CPU_4KEC;
 651                 __cpu_name[cpu] = "MIPS 4KEc";
 652                 break;
 653         case PRID_IMP_4KSC:
 654         case PRID_IMP_4KSD:
 655                 c->cputype = CPU_4KSC;
 656                 __cpu_name[cpu] = "MIPS 4KSc";
 657                 break;
 658         case PRID_IMP_5KC:
 659                 c->cputype = CPU_5KC;
 660                 __cpu_name[cpu] = "MIPS 5Kc";
 661                 break;
 662         case PRID_IMP_5KE:
 663                 c->cputype = CPU_5KE;
 664                 __cpu_name[cpu] = "MIPS 5KE";
 665                 break;
 666         case PRID_IMP_20KC:
 667                 c->cputype = CPU_20KC;
 668                 __cpu_name[cpu] = "MIPS 20Kc";
 669                 break;
 670         case PRID_IMP_24K:
 671                 c->cputype = CPU_24K;
 672                 __cpu_name[cpu] = "MIPS 24Kc";
 673                 break;
 674         case PRID_IMP_24KE:
 675                 c->cputype = CPU_24K;
 676                 __cpu_name[cpu] = "MIPS 24KEc";
 677                 break;
 678         case PRID_IMP_25KF:
 679                 c->cputype = CPU_25KF;
 680                 __cpu_name[cpu] = "MIPS 25Kc";
 681                 break;
 682         case PRID_IMP_34K:
 683                 c->cputype = CPU_34K;
 684                 __cpu_name[cpu] = "MIPS 34Kc";
 685                 break;
 686         case PRID_IMP_74K:
 687                 c->cputype = CPU_74K;
 688                 __cpu_name[cpu] = "MIPS 74Kc";
 689                 break;
 690         case PRID_IMP_M14KC:
 691                 c->cputype = CPU_M14KC;
 692                 __cpu_name[cpu] = "MIPS M14Kc";
 693                 break;
 694         case PRID_IMP_M14KEC:
 695                 c->cputype = CPU_M14KEC;
 696                 __cpu_name[cpu] = "MIPS M14KEc";
 697                 break;
 698         case PRID_IMP_1004K:
 699                 c->cputype = CPU_1004K;
 700                 __cpu_name[cpu] = "MIPS 1004Kc";
 701                 break;
 702         case PRID_IMP_1074K:
 703                 c->cputype = CPU_74K;
 704                 __cpu_name[cpu] = "MIPS 1074Kc";
 705                 break;
 706         }
 707
 708         spram_config();
 709 }
 710
 711 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 712 {
 713         decode_configs(c);
 714         switch (c->processor_id & 0xff00) {
 715         case PRID_IMP_AU1_REV1:
 716         case PRID_IMP_AU1_REV2:
 717                 c->cputype = CPU_ALCHEMY;
 718                 switch ((c->processor_id >> 24) & 0xff) {
 719                 case 0:
 720                         __cpu_name[cpu] = "Au1000";
 721                         break;
 722                 case 1:
 723                         __cpu_name[cpu] = "Au1500";
 724                         break;
 725                 case 2:
 726                         __cpu_name[cpu] = "Au1100";
 727                         break;
 728                 case 3:
 729                         __cpu_name[cpu] = "Au1550";
 730                         break;
 731                 case 4:
 732                         __cpu_name[cpu] = "Au1200";
 733                         if ((c->processor_id & 0xff) == 2)
 734                                 __cpu_name[cpu] = "Au1250";
 735                         break;
 736                 case 5:
 737                         __cpu_name[cpu] = "Au1210";
 738                         break;
 739                 default:
 740                         __cpu_name[cpu] = "Au1xxx";
 741                         break;
 742                 }
 743                 break;
 744         }
 745 }
 746
 747 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 748 {
 749         decode_configs(c);
 750
 751         switch (c->processor_id & 0xff00) {
 752         case PRID_IMP_SB1:
 753                 c->cputype = CPU_SB1;
 754                 __cpu_name[cpu] = "SiByte SB1";
 755                 /* FPU in pass1 is known to have issues. */
 756                 if ((c->processor_id & 0xff) < 0x02)
 757                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 758                 break;
 759         case PRID_IMP_SB1A:
 760                 c->cputype = CPU_SB1A;
 761                 __cpu_name[cpu] = "SiByte SB1A";
 762                 break;
 763         }
 764 }
 765
 766 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 767 {
 768         decode_configs(c);
 769         switch (c->processor_id & 0xff00) {
 770         case PRID_IMP_SR71000:
 771                 c->cputype = CPU_SR71000;
 772                 __cpu_name[cpu] = "Sandcraft SR71000";
 773                 c->scache.ways = 8;
 774                 c->tlbsize = 64;
 775                 break;
 776         }
 777 }
 778
 779 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 780 {
 781         decode_configs(c);
 782         switch (c->processor_id & 0xff00) {
 783         case PRID_IMP_PR4450:
 784                 c->cputype = CPU_PR4450;
 785                 __cpu_name[cpu] = "Philips PR4450";
 786                 set_isa(c, MIPS_CPU_ISA_M32R1);
 787                 break;
 788         }
 789 }
 790
 791 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 792 {
 793         decode_configs(c);
 794         switch (c->processor_id & 0xff00) {
 795         case PRID_IMP_BMIPS32_REV4:
 796         case PRID_IMP_BMIPS32_REV8:
 797                 c->cputype = CPU_BMIPS32;
 798                 __cpu_name[cpu] = "Broadcom BMIPS32";
 799                 set_elf_platform(cpu, "bmips32");
 800                 break;
 801         case PRID_IMP_BMIPS3300:
 802         case PRID_IMP_BMIPS3300_ALT:
 803         case PRID_IMP_BMIPS3300_BUG:
 804                 c->cputype = CPU_BMIPS3300;
 805                 __cpu_name[cpu] = "Broadcom BMIPS3300";
 806                 set_elf_platform(cpu, "bmips3300");
 807                 break;
 808         case PRID_IMP_BMIPS43XX: {
 809                 int rev = c->processor_id & 0xff;
 810
 811                 if (rev >= PRID_REV_BMIPS4380_LO &&
 812                                 rev <= PRID_REV_BMIPS4380_HI) {
 813                         c->cputype = CPU_BMIPS4380;
 814                         __cpu_name[cpu] = "Broadcom BMIPS4380";
 815                         set_elf_platform(cpu, "bmips4380");
 816                 } else {
 817                         c->cputype = CPU_BMIPS4350;
 818                         __cpu_name[cpu] = "Broadcom BMIPS4350";
 819                         set_elf_platform(cpu, "bmips4350");
 820                 }
 821                 break;
 822         }
 823         case PRID_IMP_BMIPS5000:
 824                 c->cputype = CPU_BMIPS5000;
 825                 __cpu_name[cpu] = "Broadcom BMIPS5000";
 826                 set_elf_platform(cpu, "bmips5000");
 827                 c->options |= MIPS_CPU_ULRI;
 828                 break;
 829         }
 830 }
 831
 832 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 833 {
 834         decode_configs(c);
 835         switch (c->processor_id & 0xff00) {
 836         case PRID_IMP_CAVIUM_CN38XX:
 837         case PRID_IMP_CAVIUM_CN31XX:
 838         case PRID_IMP_CAVIUM_CN30XX:
 839                 c->cputype = CPU_CAVIUM_OCTEON;
 840                 __cpu_name[cpu] = "Cavium Octeon";
 841                 goto platform;
 842         case PRID_IMP_CAVIUM_CN58XX:
 843         case PRID_IMP_CAVIUM_CN56XX:
 844         case PRID_IMP_CAVIUM_CN50XX:
 845         case PRID_IMP_CAVIUM_CN52XX:
 846                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 847                 __cpu_name[cpu] = "Cavium Octeon+";
 848 platform:
 849                 set_elf_platform(cpu, "octeon");
 850                 break;
 851         case PRID_IMP_CAVIUM_CN61XX:
 852         case PRID_IMP_CAVIUM_CN63XX:
 853         case PRID_IMP_CAVIUM_CN66XX:
 854         case PRID_IMP_CAVIUM_CN68XX:
 855                 c->cputype = CPU_CAVIUM_OCTEON2;
 856                 __cpu_name[cpu] = "Cavium Octeon II";
 857                 set_elf_platform(cpu, "octeon2");
 858                 break;
 859         default:
 860                 printk(KERN_INFO "Unknown Octeon chip!\n");
 861                 c->cputype = CPU_UNKNOWN;
 862                 break;
 863         }
 864 }
 865
 866 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 867 {
 868         decode_configs(c);
 869         /* JZRISC does not implement the CP0 counter. */
 870         c->options &= ~MIPS_CPU_COUNTER;
 871         switch (c->processor_id & 0xff00) {
 872         case PRID_IMP_JZRISC:
 873                 c->cputype = CPU_JZRISC;
 874                 __cpu_name[cpu] = "Ingenic JZRISC";
 875                 break;
 876         default:
 877                 panic("Unknown Ingenic Processor ID!");
 878                 break;
 879         }
 880 }
 881
 882 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
 883 {
 884         decode_configs(c);
 885
 886         if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
 887                 c->cputype = CPU_ALCHEMY;
 888                 __cpu_name[cpu] = "Au1300";
 889                 /* following stuff is not for Alchemy */
 890                 return;
 891         }
 892
 893         c->options = (MIPS_CPU_TLB       |
 894                         MIPS_CPU_4KEX    |
 895                         MIPS_CPU_COUNTER |
 896                         MIPS_CPU_DIVEC   |
 897                         MIPS_CPU_WATCH   |
 898                         MIPS_CPU_EJTAG   |
 899                         MIPS_CPU_LLSC);
 900
 901         switch (c->processor_id & 0xff00) {
 902         case PRID_IMP_NETLOGIC_XLP8XX:
 903         case PRID_IMP_NETLOGIC_XLP3XX:
 904                 c->cputype = CPU_XLP;
 905                 __cpu_name[cpu] = "Netlogic XLP";
 906                 break;
 907
 908         case PRID_IMP_NETLOGIC_XLR732:
 909         case PRID_IMP_NETLOGIC_XLR716:
 910         case PRID_IMP_NETLOGIC_XLR532:
 911         case PRID_IMP_NETLOGIC_XLR308:
 912         case PRID_IMP_NETLOGIC_XLR532C:
 913         case PRID_IMP_NETLOGIC_XLR516C:
 914         case PRID_IMP_NETLOGIC_XLR508C:
 915         case PRID_IMP_NETLOGIC_XLR308C:
 916                 c->cputype = CPU_XLR;
 917                 __cpu_name[cpu] = "Netlogic XLR";
 918                 break;
 919
 920         case PRID_IMP_NETLOGIC_XLS608:
 921         case PRID_IMP_NETLOGIC_XLS408:
 922         case PRID_IMP_NETLOGIC_XLS404:
 923         case PRID_IMP_NETLOGIC_XLS208:
 924         case PRID_IMP_NETLOGIC_XLS204:
 925         case PRID_IMP_NETLOGIC_XLS108:
 926         case PRID_IMP_NETLOGIC_XLS104:
 927         case PRID_IMP_NETLOGIC_XLS616B:
 928         case PRID_IMP_NETLOGIC_XLS608B:
 929         case PRID_IMP_NETLOGIC_XLS416B:
 930         case PRID_IMP_NETLOGIC_XLS412B:
 931         case PRID_IMP_NETLOGIC_XLS408B:
 932         case PRID_IMP_NETLOGIC_XLS404B:
 933                 c->cputype = CPU_XLR;
 934                 __cpu_name[cpu] = "Netlogic XLS";
 935                 break;
 936
 937         default:
 938                 pr_info("Unknown Netlogic chip id [%02x]!\n",
 939                        c->processor_id);
 940                 c->cputype = CPU_XLR;
 941                 break;
 942         }
 943
 944         if (c->cputype == CPU_XLP) {
 945                 set_isa(c, MIPS_CPU_ISA_M64R2);
 946                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
 947                 /* This will be updated again after all threads are woken up */
 948                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
 949         } else {
 950                 set_isa(c, MIPS_CPU_ISA_M64R1);
 951                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
 952         }
 953         c->kscratch_mask = 0xf;
 954 }
 955
 956 #ifdef CONFIG_64BIT
 957 /* For use by uaccess.h */
 958 u64 __ua_limit;
 959 EXPORT_SYMBOL(__ua_limit);
 960 #endif
 961
 962 const char *__cpu_name[NR_CPUS];
 963 const char *__elf_platform;
 964
 965 __cpuinit void cpu_probe(void)
 966 {
 967         struct cpuinfo_mips *c = &current_cpu_data;
 968         unsigned int cpu = smp_processor_id();
 969
 970         c->processor_id = PRID_IMP_UNKNOWN;
 971         c->fpu_id       = FPIR_IMP_NONE;
 972         c->cputype      = CPU_UNKNOWN;
 973
 974         c->processor_id = read_c0_prid();
 975         switch (c->processor_id & 0xff0000) {
 976         case PRID_COMP_LEGACY:
 977                 cpu_probe_legacy(c, cpu);
 978                 break;
 979         case PRID_COMP_MIPS:
 980                 cpu_probe_mips(c, cpu);
 981                 break;
 982         case PRID_COMP_ALCHEMY:
 983                 cpu_probe_alchemy(c, cpu);
 984                 break;
 985         case PRID_COMP_SIBYTE:
 986                 cpu_probe_sibyte(c, cpu);
 987                 break;
 988         case PRID_COMP_BROADCOM:
 989                 cpu_probe_broadcom(c, cpu);
 990                 break;
 991         case PRID_COMP_SANDCRAFT:
 992                 cpu_probe_sandcraft(c, cpu);
 993                 break;
 994         case PRID_COMP_NXP:
 995                 cpu_probe_nxp(c, cpu);
 996                 break;
 997         case PRID_COMP_CAVIUM:
 998                 cpu_probe_cavium(c, cpu);
 999                 break;
1000         case PRID_COMP_INGENIC:
1001                 cpu_probe_ingenic(c, cpu);
1002                 break;
1003         case PRID_COMP_NETLOGIC:
1004                 cpu_probe_netlogic(c, cpu);
1005                 break;
1006         }
1007
1008         BUG_ON(!__cpu_name[cpu]);
1009         BUG_ON(c->cputype == CPU_UNKNOWN);
1010
1011         /*
1012          * Platform code can force the cpu type to optimize code
1013          * generation. In that case be sure the cpu type is correctly
1014          * manually setup otherwise it could trigger some nasty bugs.
1015          */
1016         BUG_ON(current_cpu_type() != c->cputype);
1017
1018         if (mips_fpu_disabled)
1019                 c->options &= ~MIPS_CPU_FPU;
1020
1021         if (mips_dsp_disabled)
1022                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1023
1024         if (c->options & MIPS_CPU_FPU) {
1025                 c->fpu_id = cpu_get_fpu_id();
1026
1027                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1028                                     MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1029                         if (c->fpu_id & MIPS_FPIR_3D)
1030                                 c->ases |= MIPS_ASE_MIPS3D;
1031                 }
1032         }
1033
1034         if (cpu_has_mips_r2) {
1035                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1036                 /* R2 has Performance Counter Interrupt indicator */
1037                 c->options |= MIPS_CPU_PCI;
1038         }
1039         else
1040                 c->srsets = 1;
1041
1042         cpu_probe_vmbits(c);
1043
1044 #ifdef CONFIG_64BIT
1045         if (cpu == 0)
1046                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1047 #endif
1048 }
1049
1050 __cpuinit void cpu_report(void)
1051 {
1052         struct cpuinfo_mips *c = &current_cpu_data;
1053
1054         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1055                c->processor_id, cpu_name_string());
1056         if (c->options & MIPS_CPU_FPU)
1057                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1058 }