arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/fpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/mipsmtregs.h>
  28 #include <asm/msa.h>
  29 #include <asm/watch.h>
  30 #include <asm/elf.h>
  31 #include <asm/pgtable-bits.h>
  32 #include <asm/spram.h>
  33 #include <asm/uaccess.h>
  34
  35 /*
  36  * Get the FPU Implementation/Revision.
  37  */
  38 static inline unsigned long cpu_get_fpu_id(void)
  39 {
  40         unsigned long tmp, fpu_id;
  41
  42         tmp = read_c0_status();
  43         __enable_fpu(FPU_AS_IS);
  44         fpu_id = read_32bit_cp1_register(CP1_REVISION);
  45         write_c0_status(tmp);
  46         return fpu_id;
  47 }
  48
  49 /*
  50  * Check if the CPU has an external FPU.
  51  */
  52 static inline int __cpu_has_fpu(void)
  53 {
  54         return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
  55 }
  56
  57 static inline unsigned long cpu_get_msa_id(void)
  58 {
  59         unsigned long status, msa_id;
  60
  61         status = read_c0_status();
  62         __enable_fpu(FPU_64BIT);
  63         enable_msa();
  64         msa_id = read_msa_ir();
  65         disable_msa();
  66         write_c0_status(status);
  67         return msa_id;
  68 }
  69
  70 /*
  71  * Determine the FCSR mask for FPU hardware.
  72  */
  73 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
  74 {
  75         unsigned long sr, mask, fcsr, fcsr0, fcsr1;
  76
  77         fcsr = c->fpu_csr31;
  78         mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
  79
  80         sr = read_c0_status();
  81         __enable_fpu(FPU_AS_IS);
  82
  83         fcsr0 = fcsr & mask;
  84         write_32bit_cp1_register(CP1_STATUS, fcsr0);
  85         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
  86
  87         fcsr1 = fcsr | ~mask;
  88         write_32bit_cp1_register(CP1_STATUS, fcsr1);
  89         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
  90
  91         write_32bit_cp1_register(CP1_STATUS, fcsr);
  92
  93         write_c0_status(sr);
  94
  95         c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
  96 }
  97
  98 /*
  99  * Set the FIR feature flags for the FPU emulator.
 100  */
 101 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
 102 {
 103         u32 value;
 104
 105         value = 0;
 106         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 107                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 108                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 109                 value |= MIPS_FPIR_D | MIPS_FPIR_S;
 110         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 111                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 112                 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
 113         c->fpu_id = value;
 114 }
 115
 116 /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
 117 static unsigned int mips_nofpu_msk31;
 118
 119 /*
 120  * Set options for FPU hardware.
 121  */
 122 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 123 {
 124         c->fpu_id = cpu_get_fpu_id();
 125         mips_nofpu_msk31 = c->fpu_msk31;
 126
 127         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 128                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 129                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 130                 if (c->fpu_id & MIPS_FPIR_3D)
 131                         c->ases |= MIPS_ASE_MIPS3D;
 132                 if (c->fpu_id & MIPS_FPIR_FREP)
 133                         c->options |= MIPS_CPU_FRE;
 134         }
 135
 136         cpu_set_fpu_fcsr_mask(c);
 137 }
 138
 139 /*
 140  * Set options for the FPU emulator.
 141  */
 142 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 143 {
 144         c->options &= ~MIPS_CPU_FPU;
 145         c->fpu_msk31 = mips_nofpu_msk31;
 146
 147         cpu_set_nofpu_id(c);
 148 }
 149
 150 static int mips_fpu_disabled;
 151
 152 static int __init fpu_disable(char *s)
 153 {
 154         cpu_set_nofpu_opts(&boot_cpu_data);
 155         mips_fpu_disabled = 1;
 156
 157         return 1;
 158 }
 159
 160 __setup("nofpu", fpu_disable);
 161
 162 int mips_dsp_disabled;
 163
 164 static int __init dsp_disable(char *s)
 165 {
 166         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 167         mips_dsp_disabled = 1;
 168
 169         return 1;
 170 }
 171
 172 __setup("nodsp", dsp_disable);
 173
 174 static int mips_htw_disabled;
 175
 176 static int __init htw_disable(char *s)
 177 {
 178         mips_htw_disabled = 1;
 179         cpu_data[0].options &= ~MIPS_CPU_HTW;
 180         write_c0_pwctl(read_c0_pwctl() &
 181                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
 182
 183         return 1;
 184 }
 185
 186 __setup("nohtw", htw_disable);
 187
 188 static int mips_ftlb_disabled;
 189 static int mips_has_ftlb_configured;
 190
 191 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
 192
 193 static int __init ftlb_disable(char *s)
 194 {
 195         unsigned int config4, mmuextdef;
 196
 197         /*
 198          * If the core hasn't done any FTLB configuration, there is nothing
 199          * for us to do here.
 200          */
 201         if (!mips_has_ftlb_configured)
 202                 return 1;
 203
 204         /* Disable it in the boot cpu */
 205         if (set_ftlb_enable(&cpu_data[0], 0)) {
 206                 pr_warn("Can't turn FTLB off\n");
 207                 return 1;
 208         }
 209
 210         back_to_back_c0_hazard();
 211
 212         config4 = read_c0_config4();
 213
 214         /* Check that FTLB has been disabled */
 215         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 216         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 217         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 218                 /* This should never happen */
 219                 pr_warn("FTLB could not be disabled!\n");
 220                 return 1;
 221         }
 222
 223         mips_ftlb_disabled = 1;
 224         mips_has_ftlb_configured = 0;
 225
 226         /*
 227          * noftlb is mainly used for debug purposes so print
 228          * an informative message instead of using pr_debug()
 229          */
 230         pr_info("FTLB has been disabled\n");
 231
 232         /*
 233          * Some of these bits are duplicated in the decode_config4.
 234          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 235          * once FTLB has been disabled so undo what decode_config4 did.
 236          */
 237         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 238                                cpu_data[0].tlbsizeftlbsets;
 239         cpu_data[0].tlbsizeftlbsets = 0;
 240         cpu_data[0].tlbsizeftlbways = 0;
 241
 242         return 1;
 243 }
 244
 245 __setup("noftlb", ftlb_disable);
 246
 247
 248 static inline void check_errata(void)
 249 {
 250         struct cpuinfo_mips *c = &current_cpu_data;
 251
 252         switch (current_cpu_type()) {
 253         case CPU_34K:
 254                 /*
 255                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 256                  * This code only handles VPE0, any SMP/RTOS code
 257                  * making use of VPE1 will be responsable for that VPE.
 258                  */
 259                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 260                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 261                 break;
 262         default:
 263                 break;
 264         }
 265 }
 266
 267 void __init check_bugs32(void)
 268 {
 269         check_errata();
 270 }
 271
 272 /*
 273  * Probe whether cpu has config register by trying to play with
 274  * alternate cache bit and see whether it matters.
 275  * It's used by cpu_probe to distinguish between R3000A and R3081.
 276  */
 277 static inline int cpu_has_confreg(void)
 278 {
 279 #ifdef CONFIG_CPU_R3000
 280         extern unsigned long r3k_cache_size(unsigned long);
 281         unsigned long size1, size2;
 282         unsigned long cfg = read_c0_conf();
 283
 284         size1 = r3k_cache_size(ST0_ISC);
 285         write_c0_conf(cfg ^ R30XX_CONF_AC);
 286         size2 = r3k_cache_size(ST0_ISC);
 287         write_c0_conf(cfg);
 288         return size1 != size2;
 289 #else
 290         return 0;
 291 #endif
 292 }
 293
 294 static inline void set_elf_platform(int cpu, const char *plat)
 295 {
 296         if (cpu == 0)
 297                 __elf_platform = plat;
 298 }
 299
 300 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 301 {
 302 #ifdef __NEED_VMBITS_PROBE
 303         write_c0_entryhi(0x3fffffffffffe000ULL);
 304         back_to_back_c0_hazard();
 305         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 306 #endif
 307 }
 308
 309 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 310 {
 311         switch (isa) {
 312         case MIPS_CPU_ISA_M64R2:
 313                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 314         case MIPS_CPU_ISA_M64R1:
 315                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 316         case MIPS_CPU_ISA_V:
 317                 c->isa_level |= MIPS_CPU_ISA_V;
 318         case MIPS_CPU_ISA_IV:
 319                 c->isa_level |= MIPS_CPU_ISA_IV;
 320         case MIPS_CPU_ISA_III:
 321                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 322                 break;
 323
 324         /* R6 incompatible with everything else */
 325         case MIPS_CPU_ISA_M64R6:
 326                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 327         case MIPS_CPU_ISA_M32R6:
 328                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 329                 /* Break here so we don't add incompatible ISAs */
 330                 break;
 331         case MIPS_CPU_ISA_M32R2:
 332                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 333         case MIPS_CPU_ISA_M32R1:
 334                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 335         case MIPS_CPU_ISA_II:
 336                 c->isa_level |= MIPS_CPU_ISA_II;
 337                 break;
 338         }
 339 }
 340
 341 static char unknown_isa[] = KERN_ERR \
 342         "Unsupported ISA type, c0.config0: %d.";
 343
 344 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 345 {
 346
 347         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 348
 349         /*
 350          * 0 = All TLBWR instructions go to FTLB
 351          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 352          * FTLB and 1 goes to the VTLB.
 353          * 2 = 7:1: As above with 7:1 ratio.
 354          * 3 = 3:1: As above with 3:1 ratio.
 355          *
 356          * Use the linear midpoint as the probability threshold.
 357          */
 358         if (probability >= 12)
 359                 return 1;
 360         else if (probability >= 6)
 361                 return 2;
 362         else
 363                 /*
 364                  * So FTLB is less than 4 times bigger than VTLB.
 365                  * A 3:1 ratio can still be useful though.
 366                  */
 367                 return 3;
 368 }
 369
 370 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 371 {
 372         unsigned int config6;
 373
 374         /* It's implementation dependent how the FTLB can be enabled */
 375         switch (c->cputype) {
 376         case CPU_PROAPTIV:
 377         case CPU_P5600:
 378                 /* proAptiv & related cores use Config6 to enable the FTLB */
 379                 config6 = read_c0_config6();
 380                 /* Clear the old probability value */
 381                 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
 382                 if (enable)
 383                         /* Enable FTLB */
 384                         write_c0_config6(config6 |
 385                                          (calculate_ftlb_probability(c)
 386                                           << MIPS_CONF6_FTLBP_SHIFT)
 387                                          | MIPS_CONF6_FTLBEN);
 388                 else
 389                         /* Disable FTLB */
 390                         write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
 391                 break;
 392         default:
 393                 return 1;
 394         }
 395
 396         return 0;
 397 }
 398
 399 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 400 {
 401         unsigned int config0;
 402         int isa;
 403
 404         config0 = read_c0_config();
 405
 406         /*
 407          * Look for Standard TLB or Dual VTLB and FTLB
 408          */
 409         if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
 410             (((config0 & MIPS_CONF_MT) >> 7) == 4))
 411                 c->options |= MIPS_CPU_TLB;
 412
 413         isa = (config0 & MIPS_CONF_AT) >> 13;
 414         switch (isa) {
 415         case 0:
 416                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 417                 case 0:
 418                         set_isa(c, MIPS_CPU_ISA_M32R1);
 419                         break;
 420                 case 1:
 421                         set_isa(c, MIPS_CPU_ISA_M32R2);
 422                         break;
 423                 case 2:
 424                         set_isa(c, MIPS_CPU_ISA_M32R6);
 425                         break;
 426                 default:
 427                         goto unknown;
 428                 }
 429                 break;
 430         case 2:
 431                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 432                 case 0:
 433                         set_isa(c, MIPS_CPU_ISA_M64R1);
 434                         break;
 435                 case 1:
 436                         set_isa(c, MIPS_CPU_ISA_M64R2);
 437                         break;
 438                 case 2:
 439                         set_isa(c, MIPS_CPU_ISA_M64R6);
 440                         break;
 441                 default:
 442                         goto unknown;
 443                 }
 444                 break;
 445         default:
 446                 goto unknown;
 447         }
 448
 449         return config0 & MIPS_CONF_M;
 450
 451 unknown:
 452         panic(unknown_isa, config0);
 453 }
 454
 455 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 456 {
 457         unsigned int config1;
 458
 459         config1 = read_c0_config1();
 460
 461         if (config1 & MIPS_CONF1_MD)
 462                 c->ases |= MIPS_ASE_MDMX;
 463         if (config1 & MIPS_CONF1_WR)
 464                 c->options |= MIPS_CPU_WATCH;
 465         if (config1 & MIPS_CONF1_CA)
 466                 c->ases |= MIPS_ASE_MIPS16;
 467         if (config1 & MIPS_CONF1_EP)
 468                 c->options |= MIPS_CPU_EJTAG;
 469         if (config1 & MIPS_CONF1_FP) {
 470                 c->options |= MIPS_CPU_FPU;
 471                 c->options |= MIPS_CPU_32FPR;
 472         }
 473         if (cpu_has_tlb) {
 474                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 475                 c->tlbsizevtlb = c->tlbsize;
 476                 c->tlbsizeftlbsets = 0;
 477         }
 478
 479         return config1 & MIPS_CONF_M;
 480 }
 481
 482 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 483 {
 484         unsigned int config2;
 485
 486         config2 = read_c0_config2();
 487
 488         if (config2 & MIPS_CONF2_SL)
 489                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 490
 491         return config2 & MIPS_CONF_M;
 492 }
 493
 494 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 495 {
 496         unsigned int config3;
 497
 498         config3 = read_c0_config3();
 499
 500         if (config3 & MIPS_CONF3_SM) {
 501                 c->ases |= MIPS_ASE_SMARTMIPS;
 502                 c->options |= MIPS_CPU_RIXI;
 503         }
 504         if (config3 & MIPS_CONF3_RXI)
 505                 c->options |= MIPS_CPU_RIXI;
 506         if (config3 & MIPS_CONF3_DSP)
 507                 c->ases |= MIPS_ASE_DSP;
 508         if (config3 & MIPS_CONF3_DSP2P)
 509                 c->ases |= MIPS_ASE_DSP2P;
 510         if (config3 & MIPS_CONF3_VINT)
 511                 c->options |= MIPS_CPU_VINT;
 512         if (config3 & MIPS_CONF3_VEIC)
 513                 c->options |= MIPS_CPU_VEIC;
 514         if (config3 & MIPS_CONF3_MT)
 515                 c->ases |= MIPS_ASE_MIPSMT;
 516         if (config3 & MIPS_CONF3_ULRI)
 517                 c->options |= MIPS_CPU_ULRI;
 518         if (config3 & MIPS_CONF3_ISA)
 519                 c->options |= MIPS_CPU_MICROMIPS;
 520         if (config3 & MIPS_CONF3_VZ)
 521                 c->ases |= MIPS_ASE_VZ;
 522         if (config3 & MIPS_CONF3_SC)
 523                 c->options |= MIPS_CPU_SEGMENTS;
 524         if (config3 & MIPS_CONF3_MSA)
 525                 c->ases |= MIPS_ASE_MSA;
 526         /* Only tested on 32-bit cores */
 527         if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
 528                 c->htw_seq = 0;
 529                 c->options |= MIPS_CPU_HTW;
 530         }
 531         if (config3 & MIPS_CONF3_CDMM)
 532                 c->options |= MIPS_CPU_CDMM;
 533
 534         return config3 & MIPS_CONF_M;
 535 }
 536
 537 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 538 {
 539         unsigned int config4;
 540         unsigned int newcf4;
 541         unsigned int mmuextdef;
 542         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 543
 544         config4 = read_c0_config4();
 545
 546         if (cpu_has_tlb) {
 547                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 548                         c->options |= MIPS_CPU_TLBINV;
 549                 /*
 550                  * This is a bit ugly. R6 has dropped that field from
 551                  * config4 and the only valid configuration is VTLB+FTLB so
 552                  * set a good value for mmuextdef for that case.
 553                  */
 554                 if (cpu_has_mips_r6)
 555                         mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
 556                 else
 557                         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 558
 559                 switch (mmuextdef) {
 560                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 561                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 562                         c->tlbsizevtlb = c->tlbsize;
 563                         break;
 564                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 565                         c->tlbsizevtlb +=
 566                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 567                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 568                         c->tlbsize = c->tlbsizevtlb;
 569                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 570                         /* fall through */
 571                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 572                         if (mips_ftlb_disabled)
 573                                 break;
 574                         newcf4 = (config4 & ~ftlb_page) |
 575                                 (page_size_ftlb(mmuextdef) <<
 576                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 577                         write_c0_config4(newcf4);
 578                         back_to_back_c0_hazard();
 579                         config4 = read_c0_config4();
 580                         if (config4 != newcf4) {
 581                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 582                                        PAGE_SIZE, config4);
 583                                 /* Switch FTLB off */
 584                                 set_ftlb_enable(c, 0);
 585                                 break;
 586                         }
 587                         c->tlbsizeftlbsets = 1 <<
 588                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 589                                  MIPS_CONF4_FTLBSETS_SHIFT);
 590                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 591                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 592                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 593                         mips_has_ftlb_configured = 1;
 594                         break;
 595                 }
 596         }
 597
 598         c->kscratch_mask = (config4 >> 16) & 0xff;
 599
 600         return config4 & MIPS_CONF_M;
 601 }
 602
 603 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 604 {
 605         unsigned int config5;
 606
 607         config5 = read_c0_config5();
 608         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 609         write_c0_config5(config5);
 610
 611         if (config5 & MIPS_CONF5_EVA)
 612                 c->options |= MIPS_CPU_EVA;
 613         if (config5 & MIPS_CONF5_MRP)
 614                 c->options |= MIPS_CPU_MAAR;
 615         if (config5 & MIPS_CONF5_LLB)
 616                 c->options |= MIPS_CPU_RW_LLB;
 617 #ifdef CONFIG_XPA
 618         if (config5 & MIPS_CONF5_MVH)
 619                 c->options |= MIPS_CPU_XPA;
 620 #endif
 621
 622         return config5 & MIPS_CONF_M;
 623 }
 624
 625 static void decode_configs(struct cpuinfo_mips *c)
 626 {
 627         int ok;
 628
 629         /* MIPS32 or MIPS64 compliant CPU.  */
 630         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 631                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 632
 633         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 634
 635         /* Enable FTLB if present and not disabled */
 636         set_ftlb_enable(c, !mips_ftlb_disabled);
 637
 638         ok = decode_config0(c);                 /* Read Config registers.  */
 639         BUG_ON(!ok);                            /* Arch spec violation!  */
 640         if (ok)
 641                 ok = decode_config1(c);
 642         if (ok)
 643                 ok = decode_config2(c);
 644         if (ok)
 645                 ok = decode_config3(c);
 646         if (ok)
 647                 ok = decode_config4(c);
 648         if (ok)
 649                 ok = decode_config5(c);
 650
 651         mips_probe_watch_registers(c);
 652
 653         if (cpu_has_rixi) {
 654                 /* Enable the RIXI exceptions */
 655                 set_c0_pagegrain(PG_IEC);
 656                 back_to_back_c0_hazard();
 657                 /* Verify the IEC bit is set */
 658                 if (read_c0_pagegrain() & PG_IEC)
 659                         c->options |= MIPS_CPU_RIXIEX;
 660         }
 661
 662 #ifndef CONFIG_MIPS_CPS
 663         if (cpu_has_mips_r2_r6) {
 664                 c->core = get_ebase_cpunum();
 665                 if (cpu_has_mipsmt)
 666                         c->core >>= fls(core_nvpes()) - 1;
 667         }
 668 #endif
 669 }
 670
 671 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 672                 | MIPS_CPU_COUNTER)
 673
 674 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 675 {
 676         switch (c->processor_id & PRID_IMP_MASK) {
 677         case PRID_IMP_R2000:
 678                 c->cputype = CPU_R2000;
 679                 __cpu_name[cpu] = "R2000";
 680                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 681                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 682                              MIPS_CPU_NOFPUEX;
 683                 if (__cpu_has_fpu())
 684                         c->options |= MIPS_CPU_FPU;
 685                 c->tlbsize = 64;
 686                 break;
 687         case PRID_IMP_R3000:
 688                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
 689                         if (cpu_has_confreg()) {
 690                                 c->cputype = CPU_R3081E;
 691                                 __cpu_name[cpu] = "R3081";
 692                         } else {
 693                                 c->cputype = CPU_R3000A;
 694                                 __cpu_name[cpu] = "R3000A";
 695                         }
 696                 } else {
 697                         c->cputype = CPU_R3000;
 698                         __cpu_name[cpu] = "R3000";
 699                 }
 700                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 701                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 702                              MIPS_CPU_NOFPUEX;
 703                 if (__cpu_has_fpu())
 704                         c->options |= MIPS_CPU_FPU;
 705                 c->tlbsize = 64;
 706                 break;
 707         case PRID_IMP_R4000:
 708                 if (read_c0_config() & CONF_SC) {
 709                         if ((c->processor_id & PRID_REV_MASK) >=
 710                             PRID_REV_R4400) {
 711                                 c->cputype = CPU_R4400PC;
 712                                 __cpu_name[cpu] = "R4400PC";
 713                         } else {
 714                                 c->cputype = CPU_R4000PC;
 715                                 __cpu_name[cpu] = "R4000PC";
 716                         }
 717                 } else {
 718                         int cca = read_c0_config() & CONF_CM_CMASK;
 719                         int mc;
 720
 721                         /*
 722                          * SC and MC versions can't be reliably told apart,
 723                          * but only the latter support coherent caching
 724                          * modes so assume the firmware has set the KSEG0
 725                          * coherency attribute reasonably (if uncached, we
 726                          * assume SC).
 727                          */
 728                         switch (cca) {
 729                         case CONF_CM_CACHABLE_CE:
 730                         case CONF_CM_CACHABLE_COW:
 731                         case CONF_CM_CACHABLE_CUW:
 732                                 mc = 1;
 733                                 break;
 734                         default:
 735                                 mc = 0;
 736                                 break;
 737                         }
 738                         if ((c->processor_id & PRID_REV_MASK) >=
 739                             PRID_REV_R4400) {
 740                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
 741                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
 742                         } else {
 743                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
 744                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
 745                         }
 746                 }
 747
 748                 set_isa(c, MIPS_CPU_ISA_III);
 749                 c->fpu_msk31 |= FPU_CSR_CONDX;
 750                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 751                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 752                              MIPS_CPU_LLSC;
 753                 c->tlbsize = 48;
 754                 break;
 755         case PRID_IMP_VR41XX:
 756                 set_isa(c, MIPS_CPU_ISA_III);
 757                 c->fpu_msk31 |= FPU_CSR_CONDX;
 758                 c->options = R4K_OPTS;
 759                 c->tlbsize = 32;
 760                 switch (c->processor_id & 0xf0) {
 761                 case PRID_REV_VR4111:
 762                         c->cputype = CPU_VR4111;
 763                         __cpu_name[cpu] = "NEC VR4111";
 764                         break;
 765                 case PRID_REV_VR4121:
 766                         c->cputype = CPU_VR4121;
 767                         __cpu_name[cpu] = "NEC VR4121";
 768                         break;
 769                 case PRID_REV_VR4122:
 770                         if ((c->processor_id & 0xf) < 0x3) {
 771                                 c->cputype = CPU_VR4122;
 772                                 __cpu_name[cpu] = "NEC VR4122";
 773                         } else {
 774                                 c->cputype = CPU_VR4181A;
 775                                 __cpu_name[cpu] = "NEC VR4181A";
 776                         }
 777                         break;
 778                 case PRID_REV_VR4130:
 779                         if ((c->processor_id & 0xf) < 0x4) {
 780                                 c->cputype = CPU_VR4131;
 781                                 __cpu_name[cpu] = "NEC VR4131";
 782                         } else {
 783                                 c->cputype = CPU_VR4133;
 784                                 c->options |= MIPS_CPU_LLSC;
 785                                 __cpu_name[cpu] = "NEC VR4133";
 786                         }
 787                         break;
 788                 default:
 789                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 790                         c->cputype = CPU_VR41XX;
 791                         __cpu_name[cpu] = "NEC Vr41xx";
 792                         break;
 793                 }
 794                 break;
 795         case PRID_IMP_R4300:
 796                 c->cputype = CPU_R4300;
 797                 __cpu_name[cpu] = "R4300";
 798                 set_isa(c, MIPS_CPU_ISA_III);
 799                 c->fpu_msk31 |= FPU_CSR_CONDX;
 800                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 801                              MIPS_CPU_LLSC;
 802                 c->tlbsize = 32;
 803                 break;
 804         case PRID_IMP_R4600:
 805                 c->cputype = CPU_R4600;
 806                 __cpu_name[cpu] = "R4600";
 807                 set_isa(c, MIPS_CPU_ISA_III);
 808                 c->fpu_msk31 |= FPU_CSR_CONDX;
 809                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 810                              MIPS_CPU_LLSC;
 811                 c->tlbsize = 48;
 812                 break;
 813         #if 0
 814         case PRID_IMP_R4650:
 815                 /*
 816                  * This processor doesn't have an MMU, so it's not
 817                  * "real easy" to run Linux on it. It is left purely
 818                  * for documentation.  Commented out because it shares
 819                  * it's c0_prid id number with the TX3900.
 820                  */
 821                 c->cputype = CPU_R4650;
 822                 __cpu_name[cpu] = "R4650";
 823                 set_isa(c, MIPS_CPU_ISA_III);
 824                 c->fpu_msk31 |= FPU_CSR_CONDX;
 825                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 826                 c->tlbsize = 48;
 827                 break;
 828         #endif
 829         case PRID_IMP_TX39:
 830                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 831                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 832
 833                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 834                         c->cputype = CPU_TX3927;
 835                         __cpu_name[cpu] = "TX3927";
 836                         c->tlbsize = 64;
 837                 } else {
 838                         switch (c->processor_id & PRID_REV_MASK) {
 839                         case PRID_REV_TX3912:
 840                                 c->cputype = CPU_TX3912;
 841                                 __cpu_name[cpu] = "TX3912";
 842                                 c->tlbsize = 32;
 843                                 break;
 844                         case PRID_REV_TX3922:
 845                                 c->cputype = CPU_TX3922;
 846                                 __cpu_name[cpu] = "TX3922";
 847                                 c->tlbsize = 64;
 848                                 break;
 849                         }
 850                 }
 851                 break;
 852         case PRID_IMP_R4700:
 853                 c->cputype = CPU_R4700;
 854                 __cpu_name[cpu] = "R4700";
 855                 set_isa(c, MIPS_CPU_ISA_III);
 856                 c->fpu_msk31 |= FPU_CSR_CONDX;
 857                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 858                              MIPS_CPU_LLSC;
 859                 c->tlbsize = 48;
 860                 break;
 861         case PRID_IMP_TX49:
 862                 c->cputype = CPU_TX49XX;
 863                 __cpu_name[cpu] = "R49XX";
 864                 set_isa(c, MIPS_CPU_ISA_III);
 865                 c->fpu_msk31 |= FPU_CSR_CONDX;
 866                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 867                 if (!(c->processor_id & 0x08))
 868                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 869                 c->tlbsize = 48;
 870                 break;
 871         case PRID_IMP_R5000:
 872                 c->cputype = CPU_R5000;
 873                 __cpu_name[cpu] = "R5000";
 874                 set_isa(c, MIPS_CPU_ISA_IV);
 875                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 876                              MIPS_CPU_LLSC;
 877                 c->tlbsize = 48;
 878                 break;
 879         case PRID_IMP_R5432:
 880                 c->cputype = CPU_R5432;
 881                 __cpu_name[cpu] = "R5432";
 882                 set_isa(c, MIPS_CPU_ISA_IV);
 883                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 884                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 885                 c->tlbsize = 48;
 886                 break;
 887         case PRID_IMP_R5500:
 888                 c->cputype = CPU_R5500;
 889                 __cpu_name[cpu] = "R5500";
 890                 set_isa(c, MIPS_CPU_ISA_IV);
 891                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 892                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 893                 c->tlbsize = 48;
 894                 break;
 895         case PRID_IMP_NEVADA:
 896                 c->cputype = CPU_NEVADA;
 897                 __cpu_name[cpu] = "Nevada";
 898                 set_isa(c, MIPS_CPU_ISA_IV);
 899                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 900                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 901                 c->tlbsize = 48;
 902                 break;
 903         case PRID_IMP_R6000:
 904                 c->cputype = CPU_R6000;
 905                 __cpu_name[cpu] = "R6000";
 906                 set_isa(c, MIPS_CPU_ISA_II);
 907                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 908                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 909                              MIPS_CPU_LLSC;
 910                 c->tlbsize = 32;
 911                 break;
 912         case PRID_IMP_R6000A:
 913                 c->cputype = CPU_R6000A;
 914                 __cpu_name[cpu] = "R6000A";
 915                 set_isa(c, MIPS_CPU_ISA_II);
 916                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 917                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 918                              MIPS_CPU_LLSC;
 919                 c->tlbsize = 32;
 920                 break;
 921         case PRID_IMP_RM7000:
 922                 c->cputype = CPU_RM7000;
 923                 __cpu_name[cpu] = "RM7000";
 924                 set_isa(c, MIPS_CPU_ISA_IV);
 925                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 926                              MIPS_CPU_LLSC;
 927                 /*
 928                  * Undocumented RM7000:  Bit 29 in the info register of
 929                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 930                  * entries.
 931                  *
 932                  * 29      1 =>    64 entry JTLB
 933                  *         0 =>    48 entry JTLB
 934                  */
 935                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 936                 break;
 937         case PRID_IMP_R8000:
 938                 c->cputype = CPU_R8000;
 939                 __cpu_name[cpu] = "RM8000";
 940                 set_isa(c, MIPS_CPU_ISA_IV);
 941                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 942                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 943                              MIPS_CPU_LLSC;
 944                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 945                 break;
 946         case PRID_IMP_R10000:
 947                 c->cputype = CPU_R10000;
 948                 __cpu_name[cpu] = "R10000";
 949                 set_isa(c, MIPS_CPU_ISA_IV);
 950                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 951                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 952                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 953                              MIPS_CPU_LLSC;
 954                 c->tlbsize = 64;
 955                 break;
 956         case PRID_IMP_R12000:
 957                 c->cputype = CPU_R12000;
 958                 __cpu_name[cpu] = "R12000";
 959                 set_isa(c, MIPS_CPU_ISA_IV);
 960                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 961                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 962                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 963                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
 964                 c->tlbsize = 64;
 965                 break;
 966         case PRID_IMP_R14000:
 967                 if (((c->processor_id >> 4) & 0x0f) > 2) {
 968                         c->cputype = CPU_R16000;
 969                         __cpu_name[cpu] = "R16000";
 970                 } else {
 971                         c->cputype = CPU_R14000;
 972                         __cpu_name[cpu] = "R14000";
 973                 }
 974                 set_isa(c, MIPS_CPU_ISA_IV);
 975                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 976                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 977                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 978                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
 979                 c->tlbsize = 64;
 980                 break;
 981         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
 982                 switch (c->processor_id & PRID_REV_MASK) {
 983                 case PRID_REV_LOONGSON2E:
 984                         c->cputype = CPU_LOONGSON2;
 985                         __cpu_name[cpu] = "ICT Loongson-2";
 986                         set_elf_platform(cpu, "loongson2e");
 987                         set_isa(c, MIPS_CPU_ISA_III);
 988                         c->fpu_msk31 |= FPU_CSR_CONDX;
 989                         break;
 990                 case PRID_REV_LOONGSON2F:
 991                         c->cputype = CPU_LOONGSON2;
 992                         __cpu_name[cpu] = "ICT Loongson-2";
 993                         set_elf_platform(cpu, "loongson2f");
 994                         set_isa(c, MIPS_CPU_ISA_III);
 995                         c->fpu_msk31 |= FPU_CSR_CONDX;
 996                         break;
 997                 case PRID_REV_LOONGSON3A:
 998                         c->cputype = CPU_LOONGSON3;
 999                         __cpu_name[cpu] = "ICT Loongson-3";
1000                         set_elf_platform(cpu, "loongson3a");
1001                         set_isa(c, MIPS_CPU_ISA_M64R1);
1002                         break;
1003                 case PRID_REV_LOONGSON3B_R1:
1004                 case PRID_REV_LOONGSON3B_R2:
1005                         c->cputype = CPU_LOONGSON3;
1006                         __cpu_name[cpu] = "ICT Loongson-3";
1007                         set_elf_platform(cpu, "loongson3b");
1008                         set_isa(c, MIPS_CPU_ISA_M64R1);
1009                         break;
1010                 }
1011
1012                 c->options = R4K_OPTS |
1013                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
1014                              MIPS_CPU_32FPR;
1015                 c->tlbsize = 64;
1016                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1017                 break;
1018         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1019                 decode_configs(c);
1020
1021                 c->cputype = CPU_LOONGSON1;
1022
1023                 switch (c->processor_id & PRID_REV_MASK) {
1024                 case PRID_REV_LOONGSON1B:
1025                         __cpu_name[cpu] = "Loongson 1B";
1026                         break;
1027                 }
1028
1029                 break;
1030         }
1031 }
1032
1033 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1034 {
1035         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1036         switch (c->processor_id & PRID_IMP_MASK) {
1037         case PRID_IMP_QEMU_GENERIC:
1038                 c->writecombine = _CACHE_UNCACHED;
1039                 c->cputype = CPU_QEMU_GENERIC;
1040                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1041                 break;
1042         case PRID_IMP_4KC:
1043                 c->cputype = CPU_4KC;
1044                 c->writecombine = _CACHE_UNCACHED;
1045                 __cpu_name[cpu] = "MIPS 4Kc";
1046                 break;
1047         case PRID_IMP_4KEC:
1048         case PRID_IMP_4KECR2:
1049                 c->cputype = CPU_4KEC;
1050                 c->writecombine = _CACHE_UNCACHED;
1051                 __cpu_name[cpu] = "MIPS 4KEc";
1052                 break;
1053         case PRID_IMP_4KSC:
1054         case PRID_IMP_4KSD:
1055                 c->cputype = CPU_4KSC;
1056                 c->writecombine = _CACHE_UNCACHED;
1057                 __cpu_name[cpu] = "MIPS 4KSc";
1058                 break;
1059         case PRID_IMP_5KC:
1060                 c->cputype = CPU_5KC;
1061                 c->writecombine = _CACHE_UNCACHED;
1062                 __cpu_name[cpu] = "MIPS 5Kc";
1063                 break;
1064         case PRID_IMP_5KE:
1065                 c->cputype = CPU_5KE;
1066                 c->writecombine = _CACHE_UNCACHED;
1067                 __cpu_name[cpu] = "MIPS 5KE";
1068                 break;
1069         case PRID_IMP_20KC:
1070                 c->cputype = CPU_20KC;
1071                 c->writecombine = _CACHE_UNCACHED;
1072                 __cpu_name[cpu] = "MIPS 20Kc";
1073                 break;
1074         case PRID_IMP_24K:
1075                 c->cputype = CPU_24K;
1076                 c->writecombine = _CACHE_UNCACHED;
1077                 __cpu_name[cpu] = "MIPS 24Kc";
1078                 break;
1079         case PRID_IMP_24KE:
1080                 c->cputype = CPU_24K;
1081                 c->writecombine = _CACHE_UNCACHED;
1082                 __cpu_name[cpu] = "MIPS 24KEc";
1083                 break;
1084         case PRID_IMP_25KF:
1085                 c->cputype = CPU_25KF;
1086                 c->writecombine = _CACHE_UNCACHED;
1087                 __cpu_name[cpu] = "MIPS 25Kc";
1088                 break;
1089         case PRID_IMP_34K:
1090                 c->cputype = CPU_34K;
1091                 c->writecombine = _CACHE_UNCACHED;
1092                 __cpu_name[cpu] = "MIPS 34Kc";
1093                 break;
1094         case PRID_IMP_74K:
1095                 c->cputype = CPU_74K;
1096                 c->writecombine = _CACHE_UNCACHED;
1097                 __cpu_name[cpu] = "MIPS 74Kc";
1098                 break;
1099         case PRID_IMP_M14KC:
1100                 c->cputype = CPU_M14KC;
1101                 c->writecombine = _CACHE_UNCACHED;
1102                 __cpu_name[cpu] = "MIPS M14Kc";
1103                 break;
1104         case PRID_IMP_M14KEC:
1105                 c->cputype = CPU_M14KEC;
1106                 c->writecombine = _CACHE_UNCACHED;
1107                 __cpu_name[cpu] = "MIPS M14KEc";
1108                 break;
1109         case PRID_IMP_1004K:
1110                 c->cputype = CPU_1004K;
1111                 c->writecombine = _CACHE_UNCACHED;
1112                 __cpu_name[cpu] = "MIPS 1004Kc";
1113                 break;
1114         case PRID_IMP_1074K:
1115                 c->cputype = CPU_1074K;
1116                 c->writecombine = _CACHE_UNCACHED;
1117                 __cpu_name[cpu] = "MIPS 1074Kc";
1118                 break;
1119         case PRID_IMP_INTERAPTIV_UP:
1120                 c->cputype = CPU_INTERAPTIV;
1121                 __cpu_name[cpu] = "MIPS interAptiv";
1122                 break;
1123         case PRID_IMP_INTERAPTIV_MP:
1124                 c->cputype = CPU_INTERAPTIV;
1125                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1126                 break;
1127         case PRID_IMP_PROAPTIV_UP:
1128                 c->cputype = CPU_PROAPTIV;
1129                 __cpu_name[cpu] = "MIPS proAptiv";
1130                 break;
1131         case PRID_IMP_PROAPTIV_MP:
1132                 c->cputype = CPU_PROAPTIV;
1133                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1134                 break;
1135         case PRID_IMP_P5600:
1136                 c->cputype = CPU_P5600;
1137                 __cpu_name[cpu] = "MIPS P5600";
1138                 break;
1139         case PRID_IMP_I6400:
1140                 c->cputype = CPU_I6400;
1141                 __cpu_name[cpu] = "MIPS I6400";
1142                 break;
1143         case PRID_IMP_M5150:
1144                 c->cputype = CPU_M5150;
1145                 __cpu_name[cpu] = "MIPS M5150";
1146                 break;
1147         }
1148
1149         decode_configs(c);
1150
1151         spram_config();
1152 }
1153
1154 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1155 {
1156         decode_configs(c);
1157         switch (c->processor_id & PRID_IMP_MASK) {
1158         case PRID_IMP_AU1_REV1:
1159         case PRID_IMP_AU1_REV2:
1160                 c->cputype = CPU_ALCHEMY;
1161                 switch ((c->processor_id >> 24) & 0xff) {
1162                 case 0:
1163                         __cpu_name[cpu] = "Au1000";
1164                         break;
1165                 case 1:
1166                         __cpu_name[cpu] = "Au1500";
1167                         break;
1168                 case 2:
1169                         __cpu_name[cpu] = "Au1100";
1170                         break;
1171                 case 3:
1172                         __cpu_name[cpu] = "Au1550";
1173                         break;
1174                 case 4:
1175                         __cpu_name[cpu] = "Au1200";
1176                         if ((c->processor_id & PRID_REV_MASK) == 2)
1177                                 __cpu_name[cpu] = "Au1250";
1178                         break;
1179                 case 5:
1180                         __cpu_name[cpu] = "Au1210";
1181                         break;
1182                 default:
1183                         __cpu_name[cpu] = "Au1xxx";
1184                         break;
1185                 }
1186                 break;
1187         }
1188 }
1189
1190 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1191 {
1192         decode_configs(c);
1193
1194         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1195         switch (c->processor_id & PRID_IMP_MASK) {
1196         case PRID_IMP_SB1:
1197                 c->cputype = CPU_SB1;
1198                 __cpu_name[cpu] = "SiByte SB1";
1199                 /* FPU in pass1 is known to have issues. */
1200                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1201                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1202                 break;
1203         case PRID_IMP_SB1A:
1204                 c->cputype = CPU_SB1A;
1205                 __cpu_name[cpu] = "SiByte SB1A";
1206                 break;
1207         }
1208 }
1209
1210 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1211 {
1212         decode_configs(c);
1213         switch (c->processor_id & PRID_IMP_MASK) {
1214         case PRID_IMP_SR71000:
1215                 c->cputype = CPU_SR71000;
1216                 __cpu_name[cpu] = "Sandcraft SR71000";
1217                 c->scache.ways = 8;
1218                 c->tlbsize = 64;
1219                 break;
1220         }
1221 }
1222
1223 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1224 {
1225         decode_configs(c);
1226         switch (c->processor_id & PRID_IMP_MASK) {
1227         case PRID_IMP_PR4450:
1228                 c->cputype = CPU_PR4450;
1229                 __cpu_name[cpu] = "Philips PR4450";
1230                 set_isa(c, MIPS_CPU_ISA_M32R1);
1231                 break;
1232         }
1233 }
1234
1235 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1236 {
1237         decode_configs(c);
1238         switch (c->processor_id & PRID_IMP_MASK) {
1239         case PRID_IMP_BMIPS32_REV4:
1240         case PRID_IMP_BMIPS32_REV8:
1241                 c->cputype = CPU_BMIPS32;
1242                 __cpu_name[cpu] = "Broadcom BMIPS32";
1243                 set_elf_platform(cpu, "bmips32");
1244                 break;
1245         case PRID_IMP_BMIPS3300:
1246         case PRID_IMP_BMIPS3300_ALT:
1247         case PRID_IMP_BMIPS3300_BUG:
1248                 c->cputype = CPU_BMIPS3300;
1249                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1250                 set_elf_platform(cpu, "bmips3300");
1251                 break;
1252         case PRID_IMP_BMIPS43XX: {
1253                 int rev = c->processor_id & PRID_REV_MASK;
1254
1255                 if (rev >= PRID_REV_BMIPS4380_LO &&
1256                                 rev <= PRID_REV_BMIPS4380_HI) {
1257                         c->cputype = CPU_BMIPS4380;
1258                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1259                         set_elf_platform(cpu, "bmips4380");
1260                 } else {
1261                         c->cputype = CPU_BMIPS4350;
1262                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1263                         set_elf_platform(cpu, "bmips4350");
1264                 }
1265                 break;
1266         }
1267         case PRID_IMP_BMIPS5000:
1268         case PRID_IMP_BMIPS5200:
1269                 c->cputype = CPU_BMIPS5000;
1270                 __cpu_name[cpu] = "Broadcom BMIPS5000";
1271                 set_elf_platform(cpu, "bmips5000");
1272                 c->options |= MIPS_CPU_ULRI;
1273                 break;
1274         }
1275 }
1276
1277 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1278 {
1279         decode_configs(c);
1280         switch (c->processor_id & PRID_IMP_MASK) {
1281         case PRID_IMP_CAVIUM_CN38XX:
1282         case PRID_IMP_CAVIUM_CN31XX:
1283         case PRID_IMP_CAVIUM_CN30XX:
1284                 c->cputype = CPU_CAVIUM_OCTEON;
1285                 __cpu_name[cpu] = "Cavium Octeon";
1286                 goto platform;
1287         case PRID_IMP_CAVIUM_CN58XX:
1288         case PRID_IMP_CAVIUM_CN56XX:
1289         case PRID_IMP_CAVIUM_CN50XX:
1290         case PRID_IMP_CAVIUM_CN52XX:
1291                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1292                 __cpu_name[cpu] = "Cavium Octeon+";
1293 platform:
1294                 set_elf_platform(cpu, "octeon");
1295                 break;
1296         case PRID_IMP_CAVIUM_CN61XX:
1297         case PRID_IMP_CAVIUM_CN63XX:
1298         case PRID_IMP_CAVIUM_CN66XX:
1299         case PRID_IMP_CAVIUM_CN68XX:
1300         case PRID_IMP_CAVIUM_CNF71XX:
1301                 c->cputype = CPU_CAVIUM_OCTEON2;
1302                 __cpu_name[cpu] = "Cavium Octeon II";
1303                 set_elf_platform(cpu, "octeon2");
1304                 break;
1305         case PRID_IMP_CAVIUM_CN70XX:
1306         case PRID_IMP_CAVIUM_CN78XX:
1307                 c->cputype = CPU_CAVIUM_OCTEON3;
1308                 __cpu_name[cpu] = "Cavium Octeon III";
1309                 set_elf_platform(cpu, "octeon3");
1310                 break;
1311         default:
1312                 printk(KERN_INFO "Unknown Octeon chip!\n");
1313                 c->cputype = CPU_UNKNOWN;
1314                 break;
1315         }
1316 }
1317
1318 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1319 {
1320         decode_configs(c);
1321         /* JZRISC does not implement the CP0 counter. */
1322         c->options &= ~MIPS_CPU_COUNTER;
1323         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1324         switch (c->processor_id & PRID_IMP_MASK) {
1325         case PRID_IMP_JZRISC:
1326                 c->cputype = CPU_JZRISC;
1327                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1328                 __cpu_name[cpu] = "Ingenic JZRISC";
1329                 break;
1330         default:
1331                 panic("Unknown Ingenic Processor ID!");
1332                 break;
1333         }
1334 }
1335
1336 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1337 {
1338         decode_configs(c);
1339
1340         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1341                 c->cputype = CPU_ALCHEMY;
1342                 __cpu_name[cpu] = "Au1300";
1343                 /* following stuff is not for Alchemy */
1344                 return;
1345         }
1346
1347         c->options = (MIPS_CPU_TLB       |
1348                         MIPS_CPU_4KEX    |
1349                         MIPS_CPU_COUNTER |
1350                         MIPS_CPU_DIVEC   |
1351                         MIPS_CPU_WATCH   |
1352                         MIPS_CPU_EJTAG   |
1353                         MIPS_CPU_LLSC);
1354
1355         switch (c->processor_id & PRID_IMP_MASK) {
1356         case PRID_IMP_NETLOGIC_XLP2XX:
1357         case PRID_IMP_NETLOGIC_XLP9XX:
1358         case PRID_IMP_NETLOGIC_XLP5XX:
1359                 c->cputype = CPU_XLP;
1360                 __cpu_name[cpu] = "Broadcom XLPII";
1361                 break;
1362
1363         case PRID_IMP_NETLOGIC_XLP8XX:
1364         case PRID_IMP_NETLOGIC_XLP3XX:
1365                 c->cputype = CPU_XLP;
1366                 __cpu_name[cpu] = "Netlogic XLP";
1367                 break;
1368
1369         case PRID_IMP_NETLOGIC_XLR732:
1370         case PRID_IMP_NETLOGIC_XLR716:
1371         case PRID_IMP_NETLOGIC_XLR532:
1372         case PRID_IMP_NETLOGIC_XLR308:
1373         case PRID_IMP_NETLOGIC_XLR532C:
1374         case PRID_IMP_NETLOGIC_XLR516C:
1375         case PRID_IMP_NETLOGIC_XLR508C:
1376         case PRID_IMP_NETLOGIC_XLR308C:
1377                 c->cputype = CPU_XLR;
1378                 __cpu_name[cpu] = "Netlogic XLR";
1379                 break;
1380
1381         case PRID_IMP_NETLOGIC_XLS608:
1382         case PRID_IMP_NETLOGIC_XLS408:
1383         case PRID_IMP_NETLOGIC_XLS404:
1384         case PRID_IMP_NETLOGIC_XLS208:
1385         case PRID_IMP_NETLOGIC_XLS204:
1386         case PRID_IMP_NETLOGIC_XLS108:
1387         case PRID_IMP_NETLOGIC_XLS104:
1388         case PRID_IMP_NETLOGIC_XLS616B:
1389         case PRID_IMP_NETLOGIC_XLS608B:
1390         case PRID_IMP_NETLOGIC_XLS416B:
1391         case PRID_IMP_NETLOGIC_XLS412B:
1392         case PRID_IMP_NETLOGIC_XLS408B:
1393         case PRID_IMP_NETLOGIC_XLS404B:
1394                 c->cputype = CPU_XLR;
1395                 __cpu_name[cpu] = "Netlogic XLS";
1396                 break;
1397
1398         default:
1399                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1400                        c->processor_id);
1401                 c->cputype = CPU_XLR;
1402                 break;
1403         }
1404
1405         if (c->cputype == CPU_XLP) {
1406                 set_isa(c, MIPS_CPU_ISA_M64R2);
1407                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1408                 /* This will be updated again after all threads are woken up */
1409                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1410         } else {
1411                 set_isa(c, MIPS_CPU_ISA_M64R1);
1412                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1413         }
1414         c->kscratch_mask = 0xf;
1415 }
1416
1417 #ifdef CONFIG_64BIT
1418 /* For use by uaccess.h */
1419 u64 __ua_limit;
1420 EXPORT_SYMBOL(__ua_limit);
1421 #endif
1422
1423 const char *__cpu_name[NR_CPUS];
1424 const char *__elf_platform;
1425
1426 void cpu_probe(void)
1427 {
1428         struct cpuinfo_mips *c = &current_cpu_data;
1429         unsigned int cpu = smp_processor_id();
1430
1431         c->processor_id = PRID_IMP_UNKNOWN;
1432         c->fpu_id       = FPIR_IMP_NONE;
1433         c->cputype      = CPU_UNKNOWN;
1434         c->writecombine = _CACHE_UNCACHED;
1435
1436         c->fpu_csr31    = FPU_CSR_RN;
1437         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1438
1439         c->processor_id = read_c0_prid();
1440         switch (c->processor_id & PRID_COMP_MASK) {
1441         case PRID_COMP_LEGACY:
1442                 cpu_probe_legacy(c, cpu);
1443                 break;
1444         case PRID_COMP_MIPS:
1445                 cpu_probe_mips(c, cpu);
1446                 break;
1447         case PRID_COMP_ALCHEMY:
1448                 cpu_probe_alchemy(c, cpu);
1449                 break;
1450         case PRID_COMP_SIBYTE:
1451                 cpu_probe_sibyte(c, cpu);
1452                 break;
1453         case PRID_COMP_BROADCOM:
1454                 cpu_probe_broadcom(c, cpu);
1455                 break;
1456         case PRID_COMP_SANDCRAFT:
1457                 cpu_probe_sandcraft(c, cpu);
1458                 break;
1459         case PRID_COMP_NXP:
1460                 cpu_probe_nxp(c, cpu);
1461                 break;
1462         case PRID_COMP_CAVIUM:
1463                 cpu_probe_cavium(c, cpu);
1464                 break;
1465         case PRID_COMP_INGENIC_D0:
1466         case PRID_COMP_INGENIC_D1:
1467         case PRID_COMP_INGENIC_E1:
1468                 cpu_probe_ingenic(c, cpu);
1469                 break;
1470         case PRID_COMP_NETLOGIC:
1471                 cpu_probe_netlogic(c, cpu);
1472                 break;
1473         }
1474
1475         BUG_ON(!__cpu_name[cpu]);
1476         BUG_ON(c->cputype == CPU_UNKNOWN);
1477
1478         /*
1479          * Platform code can force the cpu type to optimize code
1480          * generation. In that case be sure the cpu type is correctly
1481          * manually setup otherwise it could trigger some nasty bugs.
1482          */
1483         BUG_ON(current_cpu_type() != c->cputype);
1484
1485         if (mips_fpu_disabled)
1486                 c->options &= ~MIPS_CPU_FPU;
1487
1488         if (mips_dsp_disabled)
1489                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1490
1491         if (mips_htw_disabled) {
1492                 c->options &= ~MIPS_CPU_HTW;
1493                 write_c0_pwctl(read_c0_pwctl() &
1494                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1495         }
1496
1497         if (c->options & MIPS_CPU_FPU)
1498                 cpu_set_fpu_opts(c);
1499         else
1500                 cpu_set_nofpu_opts(c);
1501
1502         if (cpu_has_bp_ghist)
1503                 write_c0_r10k_diag(read_c0_r10k_diag() |
1504                                    R10K_DIAG_E_GHIST);
1505
1506         if (cpu_has_mips_r2_r6) {
1507                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1508                 /* R2 has Performance Counter Interrupt indicator */
1509                 c->options |= MIPS_CPU_PCI;
1510         }
1511         else
1512                 c->srsets = 1;
1513
1514         if (cpu_has_msa) {
1515                 c->msa_id = cpu_get_msa_id();
1516                 WARN(c->msa_id & MSA_IR_WRPF,
1517                      "Vector register partitioning unimplemented!");
1518         }
1519
1520         cpu_probe_vmbits(c);
1521
1522 #ifdef CONFIG_64BIT
1523         if (cpu == 0)
1524                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1525 #endif
1526 }
1527
1528 void cpu_report(void)
1529 {
1530         struct cpuinfo_mips *c = &current_cpu_data;
1531
1532         pr_info("CPU%d revision is: %08x (%s)\n",
1533                 smp_processor_id(), c->processor_id, cpu_name_string());
1534         if (c->options & MIPS_CPU_FPU)
1535                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1536         if (cpu_has_msa)
1537                 pr_info("MSA revision is: %08x\n", c->msa_id);
1538 }