arch/mips/kernel/smp-bmips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
   7  *
   8  * SMP support for BMIPS
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/sched.h>
  13 #include <linux/mm.h>
  14 #include <linux/delay.h>
  15 #include <linux/smp.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/cpu.h>
  19 #include <linux/cpumask.h>
  20 #include <linux/reboot.h>
  21 #include <linux/io.h>
  22 #include <linux/compiler.h>
  23 #include <linux/linkage.h>
  24 #include <linux/bug.h>
  25 #include <linux/kernel.h>
  26
  27 #include <asm/time.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/processor.h>
  30 #include <asm/bootinfo.h>
  31 #include <asm/pmon.h>
  32 #include <asm/cacheflush.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/mipsregs.h>
  35 #include <asm/bmips.h>
  36 #include <asm/traps.h>
  37 #include <asm/barrier.h>
  38 #include <asm/cpu-features.h>
  39
  40 static int __maybe_unused max_cpus = 1;
  41
  42 /* these may be configured by the platform code */
  43 int bmips_smp_enabled = 1;
  44 int bmips_cpu_offset;
  45 cpumask_t bmips_booted_mask;
  46
  47 #define RESET_FROM_KSEG0                0x80080800
  48 #define RESET_FROM_KSEG1                0xa0080800
  49
  50 static void bmips_set_reset_vec(int cpu, u32 val);
  51
  52 #ifdef CONFIG_SMP
  53
  54 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
  55 unsigned long bmips_smp_boot_sp;
  56 unsigned long bmips_smp_boot_gp;
  57
  58 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
  59 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
  60 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
  61 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
  62
  63 /* SW interrupts 0,1 are used for interprocessor signaling */
  64 #define IPI0_IRQ                        (MIPS_CPU_IRQ_BASE + 0)
  65 #define IPI1_IRQ                        (MIPS_CPU_IRQ_BASE + 1)
  66
  67 #define CPUNUM(cpu, shift)              (((cpu) + bmips_cpu_offset) << (shift))
  68 #define ACTION_CLR_IPI(cpu, ipi)        (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  69 #define ACTION_SET_IPI(cpu, ipi)        (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  70 #define ACTION_BOOT_THREAD(cpu)         (0x08 | CPUNUM(cpu, 0))
  71
  72 static void __init bmips_smp_setup(void)
  73 {
  74         int i, cpu = 1, boot_cpu = 0;
  75         int cpu_hw_intr;
  76
  77         switch (current_cpu_type()) {
  78         case CPU_BMIPS4350:
  79         case CPU_BMIPS4380:
  80                 /* arbitration priority */
  81                 clear_c0_brcm_cmt_ctrl(0x30);
  82
  83                 /* NBK and weak order flags */
  84                 set_c0_brcm_config_0(0x30000);
  85
  86                 /* Find out if we are running on TP0 or TP1 */
  87                 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
  88
  89                 /*
  90                  * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
  91                  * thread
  92                  * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
  93                  * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
  94                  */
  95                 if (boot_cpu == 0)
  96                         cpu_hw_intr = 0x02;
  97                 else
  98                         cpu_hw_intr = 0x1d;
  99
 100                 change_c0_brcm_cmt_intr(0xf8018000,
 101                                         (cpu_hw_intr << 27) | (0x03 << 15));
 102
 103                 /* single core, 2 threads (2 pipelines) */
 104                 max_cpus = 2;
 105
 106                 break;
 107         case CPU_BMIPS5000:
 108                 /* enable raceless SW interrupts */
 109                 set_c0_brcm_config(0x03 << 22);
 110
 111                 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
 112                 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
 113
 114                 /* N cores, 2 threads per core */
 115                 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
 116
 117                 /* clear any pending SW interrupts */
 118                 for (i = 0; i < max_cpus; i++) {
 119                         write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
 120                         write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
 121                 }
 122
 123                 break;
 124         default:
 125                 max_cpus = 1;
 126         }
 127
 128         if (!bmips_smp_enabled)
 129                 max_cpus = 1;
 130
 131         /* this can be overridden by the BSP */
 132         if (!board_ebase_setup)
 133                 board_ebase_setup = &bmips_ebase_setup;
 134
 135         __cpu_number_map[boot_cpu] = 0;
 136         __cpu_logical_map[0] = boot_cpu;
 137
 138         for (i = 0; i < max_cpus; i++) {
 139                 if (i != boot_cpu) {
 140                         __cpu_number_map[i] = cpu;
 141                         __cpu_logical_map[cpu] = i;
 142                         cpu++;
 143                 }
 144                 set_cpu_possible(i, 1);
 145                 set_cpu_present(i, 1);
 146         }
 147 }
 148
 149 /*
 150  * IPI IRQ setup - runs on CPU0
 151  */
 152 static void bmips_prepare_cpus(unsigned int max_cpus)
 153 {
 154         irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
 155
 156         switch (current_cpu_type()) {
 157         case CPU_BMIPS4350:
 158         case CPU_BMIPS4380:
 159                 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
 160                 break;
 161         case CPU_BMIPS5000:
 162                 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
 163                 break;
 164         default:
 165                 return;
 166         }
 167
 168         if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
 169                         "smp_ipi0", NULL))
 170                 panic("Can't request IPI0 interrupt");
 171         if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
 172                         "smp_ipi1", NULL))
 173                 panic("Can't request IPI1 interrupt");
 174 }
 175
 176 /*
 177  * Tell the hardware to boot CPUx - runs on CPU0
 178  */
 179 static void bmips_boot_secondary(int cpu, struct task_struct *idle)
 180 {
 181         bmips_smp_boot_sp = __KSTK_TOS(idle);
 182         bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
 183         mb();
 184
 185         /*
 186          * Initial boot sequence for secondary CPU:
 187          *   bmips_reset_nmi_vec @ a000_0000 ->
 188          *   bmips_smp_entry ->
 189          *   plat_wired_tlb_setup (cached function call; optional) ->
 190          *   start_secondary (cached jump)
 191          *
 192          * Warm restart sequence:
 193          *   play_dead WAIT loop ->
 194          *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
 195          *   eret to play_dead ->
 196          *   bmips_secondary_reentry ->
 197          *   start_secondary
 198          */
 199
 200         pr_info("SMP: Booting CPU%d...\n", cpu);
 201
 202         if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
 203                 /* kseg1 might not exist if this CPU enabled XKS01 */
 204                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
 205
 206                 switch (current_cpu_type()) {
 207                 case CPU_BMIPS4350:
 208                 case CPU_BMIPS4380:
 209                         bmips43xx_send_ipi_single(cpu, 0);
 210                         break;
 211                 case CPU_BMIPS5000:
 212                         bmips5000_send_ipi_single(cpu, 0);
 213                         break;
 214                 }
 215         } else {
 216                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
 217
 218                 switch (current_cpu_type()) {
 219                 case CPU_BMIPS4350:
 220                 case CPU_BMIPS4380:
 221                         /* Reset slave TP1 if booting from TP0 */
 222                         if (cpu_logical_map(cpu) == 1)
 223                                 set_c0_brcm_cmt_ctrl(0x01);
 224                         break;
 225                 case CPU_BMIPS5000:
 226                         write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
 227                         break;
 228                 }
 229                 cpumask_set_cpu(cpu, &bmips_booted_mask);
 230         }
 231 }
 232
 233 /*
 234  * Early setup - runs on secondary CPU after cache probe
 235  */
 236 static void bmips_init_secondary(void)
 237 {
 238         switch (current_cpu_type()) {
 239         case CPU_BMIPS4350:
 240         case CPU_BMIPS4380:
 241                 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
 242                 break;
 243         case CPU_BMIPS5000:
 244                 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
 245                 break;
 246         }
 247 }
 248
 249 /*
 250  * Late setup - runs on secondary CPU before entering the idle loop
 251  */
 252 static void bmips_smp_finish(void)
 253 {
 254         pr_info("SMP: CPU%d is running\n", smp_processor_id());
 255
 256         /* make sure there won't be a timer interrupt for a little while */
 257         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 258
 259         irq_enable_hazard();
 260         set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
 261         irq_enable_hazard();
 262 }
 263
 264 /*
 265  * BMIPS5000 raceless IPIs
 266  *
 267  * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
 268  * IPI0 is used for SMP_RESCHEDULE_YOURSELF
 269  * IPI1 is used for SMP_CALL_FUNCTION
 270  */
 271
 272 static void bmips5000_send_ipi_single(int cpu, unsigned int action)
 273 {
 274         write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
 275 }
 276
 277 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
 278 {
 279         int action = irq - IPI0_IRQ;
 280
 281         write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
 282
 283         if (action == 0)
 284                 scheduler_ipi();
 285         else
 286                 smp_call_function_interrupt();
 287
 288         return IRQ_HANDLED;
 289 }
 290
 291 static void bmips5000_send_ipi_mask(const struct cpumask *mask,
 292         unsigned int action)
 293 {
 294         unsigned int i;
 295
 296         for_each_cpu(i, mask)
 297                 bmips5000_send_ipi_single(i, action);
 298 }
 299
 300 /*
 301  * BMIPS43xx racey IPIs
 302  *
 303  * We use one inbound SW IRQ for each CPU.
 304  *
 305  * A spinlock must be held in order to keep CPUx from accidentally clearing
 306  * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy.  The
 307  * same spinlock is used to protect the action masks.
 308  */
 309
 310 static DEFINE_SPINLOCK(ipi_lock);
 311 static DEFINE_PER_CPU(int, ipi_action_mask);
 312
 313 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
 314 {
 315         unsigned long flags;
 316
 317         spin_lock_irqsave(&ipi_lock, flags);
 318         set_c0_cause(cpu ? C_SW1 : C_SW0);
 319         per_cpu(ipi_action_mask, cpu) |= action;
 320         irq_enable_hazard();
 321         spin_unlock_irqrestore(&ipi_lock, flags);
 322 }
 323
 324 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
 325 {
 326         unsigned long flags;
 327         int action, cpu = irq - IPI0_IRQ;
 328
 329         spin_lock_irqsave(&ipi_lock, flags);
 330         action = __this_cpu_read(ipi_action_mask);
 331         per_cpu(ipi_action_mask, cpu) = 0;
 332         clear_c0_cause(cpu ? C_SW1 : C_SW0);
 333         spin_unlock_irqrestore(&ipi_lock, flags);
 334
 335         if (action & SMP_RESCHEDULE_YOURSELF)
 336                 scheduler_ipi();
 337         if (action & SMP_CALL_FUNCTION)
 338                 smp_call_function_interrupt();
 339
 340         return IRQ_HANDLED;
 341 }
 342
 343 static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
 344         unsigned int action)
 345 {
 346         unsigned int i;
 347
 348         for_each_cpu(i, mask)
 349                 bmips43xx_send_ipi_single(i, action);
 350 }
 351
 352 #ifdef CONFIG_HOTPLUG_CPU
 353
 354 static int bmips_cpu_disable(void)
 355 {
 356         unsigned int cpu = smp_processor_id();
 357
 358         if (cpu == 0)
 359                 return -EBUSY;
 360
 361         pr_info("SMP: CPU%d is offline\n", cpu);
 362
 363         set_cpu_online(cpu, false);
 364         cpu_clear(cpu, cpu_callin_map);
 365         clear_c0_status(IE_IRQ5);
 366
 367         local_flush_tlb_all();
 368         local_flush_icache_range(0, ~0);
 369
 370         return 0;
 371 }
 372
 373 static void bmips_cpu_die(unsigned int cpu)
 374 {
 375 }
 376
 377 void __ref play_dead(void)
 378 {
 379         idle_task_exit();
 380
 381         /* flush data cache */
 382         _dma_cache_wback_inv(0, ~0);
 383
 384         /*
 385          * Wakeup is on SW0 or SW1; disable everything else
 386          * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
 387          * IRQ handlers; this clears ST0_IE and returns immediately.
 388          */
 389         clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
 390         change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
 391                 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
 392         irq_disable_hazard();
 393
 394         /*
 395          * wait for SW interrupt from bmips_boot_secondary(), then jump
 396          * back to start_secondary()
 397          */
 398         __asm__ __volatile__(
 399         "       wait\n"
 400         "       j       bmips_secondary_reentry\n"
 401         : : : "memory");
 402 }
 403
 404 #endif /* CONFIG_HOTPLUG_CPU */
 405
 406 struct plat_smp_ops bmips43xx_smp_ops = {
 407         .smp_setup              = bmips_smp_setup,
 408         .prepare_cpus           = bmips_prepare_cpus,
 409         .boot_secondary         = bmips_boot_secondary,
 410         .smp_finish             = bmips_smp_finish,
 411         .init_secondary         = bmips_init_secondary,
 412         .send_ipi_single        = bmips43xx_send_ipi_single,
 413         .send_ipi_mask          = bmips43xx_send_ipi_mask,
 414 #ifdef CONFIG_HOTPLUG_CPU
 415         .cpu_disable            = bmips_cpu_disable,
 416         .cpu_die                = bmips_cpu_die,
 417 #endif
 418 };
 419
 420 struct plat_smp_ops bmips5000_smp_ops = {
 421         .smp_setup              = bmips_smp_setup,
 422         .prepare_cpus           = bmips_prepare_cpus,
 423         .boot_secondary         = bmips_boot_secondary,
 424         .smp_finish             = bmips_smp_finish,
 425         .init_secondary         = bmips_init_secondary,
 426         .send_ipi_single        = bmips5000_send_ipi_single,
 427         .send_ipi_mask          = bmips5000_send_ipi_mask,
 428 #ifdef CONFIG_HOTPLUG_CPU
 429         .cpu_disable            = bmips_cpu_disable,
 430         .cpu_die                = bmips_cpu_die,
 431 #endif
 432 };
 433
 434 #endif /* CONFIG_SMP */
 435
 436 /***********************************************************************
 437  * BMIPS vector relocation
 438  * This is primarily used for SMP boot, but it is applicable to some
 439  * UP BMIPS systems as well.
 440  ***********************************************************************/
 441
 442 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
 443 {
 444         memcpy((void *)dst, start, end - start);
 445         dma_cache_wback((unsigned long)start, end - start);
 446         local_flush_icache_range(dst, dst + (end - start));
 447         instruction_hazard();
 448 }
 449
 450 static inline void bmips_nmi_handler_setup(void)
 451 {
 452         bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
 453                 &bmips_reset_nmi_vec_end);
 454         bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
 455                 &bmips_smp_int_vec_end);
 456 }
 457
 458 struct reset_vec_info {
 459         int cpu;
 460         u32 val;
 461 };
 462
 463 static void bmips_set_reset_vec_remote(void *vinfo)
 464 {
 465         struct reset_vec_info *info = vinfo;
 466         int shift = info->cpu & 0x01 ? 16 : 0;
 467         u32 mask = ~(0xffff << shift), val = info->val >> 16;
 468
 469         preempt_disable();
 470         if (smp_processor_id() > 0) {
 471                 smp_call_function_single(0, &bmips_set_reset_vec_remote,
 472                                          info, 1);
 473         } else {
 474                 if (info->cpu & 0x02) {
 475                         /* BMIPS5200 "should" use mask/shift, but it's buggy */
 476                         bmips_write_zscm_reg(0xa0, (val << 16) | val);
 477                         bmips_read_zscm_reg(0xa0);
 478                 } else {
 479                         write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
 480                                               (val << shift));
 481                 }
 482         }
 483         preempt_enable();
 484 }
 485
 486 static void bmips_set_reset_vec(int cpu, u32 val)
 487 {
 488         struct reset_vec_info info;
 489
 490         if (current_cpu_type() == CPU_BMIPS5000) {
 491                 /* this needs to run from CPU0 (which is always online) */
 492                 info.cpu = cpu;
 493                 info.val = val;
 494                 bmips_set_reset_vec_remote(&info);
 495         } else {
 496                 void __iomem *cbr = BMIPS_GET_CBR();
 497
 498                 if (cpu == 0)
 499                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
 500                 else {
 501                         if (current_cpu_type() != CPU_BMIPS4380)
 502                                 return;
 503                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
 504                 }
 505         }
 506         __sync();
 507         back_to_back_c0_hazard();
 508 }
 509
 510 void bmips_ebase_setup(void)
 511 {
 512         unsigned long new_ebase = ebase;
 513
 514         BUG_ON(ebase != CKSEG0);
 515
 516         switch (current_cpu_type()) {
 517         case CPU_BMIPS4350:
 518                 /*
 519                  * BMIPS4350 cannot relocate the normal vectors, but it
 520                  * can relocate the BEV=1 vectors.  So CPU1 starts up at
 521                  * the relocated BEV=1, IV=0 general exception vector @
 522                  * 0xa000_0380.
 523                  *
 524                  * set_uncached_handler() is used here because:
 525                  *  - CPU1 will run this from uncached space
 526                  *  - None of the cacheflush functions are set up yet
 527                  */
 528                 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
 529                         &bmips_smp_int_vec, 0x80);
 530                 __sync();
 531                 return;
 532         case CPU_BMIPS3300:
 533         case CPU_BMIPS4380:
 534                 /*
 535                  * 0x8000_0000: reset/NMI (initially in kseg1)
 536                  * 0x8000_0400: normal vectors
 537                  */
 538                 new_ebase = 0x80000400;
 539                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 540                 break;
 541         case CPU_BMIPS5000:
 542                 /*
 543                  * 0x8000_0000: reset/NMI (initially in kseg1)
 544                  * 0x8000_1000: normal vectors
 545                  */
 546                 new_ebase = 0x80001000;
 547                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 548                 write_c0_ebase(new_ebase);
 549                 break;
 550         default:
 551                 return;
 552         }
 553
 554         board_nmi_handler_setup = &bmips_nmi_handler_setup;
 555         ebase = new_ebase;
 556 }
 557
 558 asmlinkage void __weak plat_wired_tlb_setup(void)
 559 {
 560         /*
 561          * Called when starting/restarting a secondary CPU.
 562          * Kernel stacks and other important data might only be accessible
 563          * once the wired entries are present.
 564          */
 565 }