arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/kdebug.h>
  15 #include <linux/module.h>
  16 #include <linux/vmalloc.h>
  17 #include <linux/fs.h>
  18 #include <linux/bootmem.h>
  19 #include <asm/fpu.h>
  20 #include <asm/page.h>
  21 #include <asm/cacheflush.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/pgtable.h>
  24
  25 #include <linux/kvm_host.h>
  26
  27 #include "interrupt.h"
  28 #include "commpage.h"
  29
  30 #define CREATE_TRACE_POINTS
  31 #include "trace.h"
  32
  33 #ifndef VECTORSPACING
  34 #define VECTORSPACING 0x100     /* for EI/VI mode */
  35 #endif
  36
  37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  38 struct kvm_stats_debugfs_item debugfs_entries[] = {
  39         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  40         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  41         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  42         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  43         { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  44         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  45         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  46         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  47         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  48         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  49         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  50         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  51         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  52         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  53         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  54         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  55         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  56         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  57         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  58         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  59         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  60         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  61         {NULL}
  62 };
  63
  64 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
  65 {
  66         int i;
  67
  68         for_each_possible_cpu(i) {
  69                 vcpu->arch.guest_kernel_asid[i] = 0;
  70                 vcpu->arch.guest_user_asid[i] = 0;
  71         }
  72
  73         return 0;
  74 }
  75
  76 /*
  77  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  78  * Config7, so we are "runnable" if interrupts are pending
  79  */
  80 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  81 {
  82         return !!(vcpu->arch.pending_exceptions);
  83 }
  84
  85 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
  86 {
  87         return 1;
  88 }
  89
  90 int kvm_arch_hardware_enable(void)
  91 {
  92         return 0;
  93 }
  94
  95 int kvm_arch_hardware_setup(void)
  96 {
  97         return 0;
  98 }
  99
 100 void kvm_arch_check_processor_compat(void *rtn)
 101 {
 102         *(int *)rtn = 0;
 103 }
 104
 105 static void kvm_mips_init_tlbs(struct kvm *kvm)
 106 {
 107         unsigned long wired;
 108
 109         /*
 110          * Add a wired entry to the TLB, it is used to map the commpage to
 111          * the Guest kernel
 112          */
 113         wired = read_c0_wired();
 114         write_c0_wired(wired + 1);
 115         mtc0_tlbw_hazard();
 116         kvm->arch.commpage_tlb = wired;
 117
 118         kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
 119                   kvm->arch.commpage_tlb);
 120 }
 121
 122 static void kvm_mips_init_vm_percpu(void *arg)
 123 {
 124         struct kvm *kvm = (struct kvm *)arg;
 125
 126         kvm_mips_init_tlbs(kvm);
 127         kvm_mips_callbacks->vm_init(kvm);
 128
 129 }
 130
 131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 132 {
 133         if (atomic_inc_return(&kvm_mips_instance) == 1) {
 134                 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
 135                           __func__);
 136                 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
 137         }
 138
 139         return 0;
 140 }
 141
 142 void kvm_mips_free_vcpus(struct kvm *kvm)
 143 {
 144         unsigned int i;
 145         struct kvm_vcpu *vcpu;
 146
 147         /* Put the pages we reserved for the guest pmap */
 148         for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
 149                 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
 150                         kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
 151         }
 152         kfree(kvm->arch.guest_pmap);
 153
 154         kvm_for_each_vcpu(i, vcpu, kvm) {
 155                 kvm_arch_vcpu_free(vcpu);
 156         }
 157
 158         mutex_lock(&kvm->lock);
 159
 160         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 161                 kvm->vcpus[i] = NULL;
 162
 163         atomic_set(&kvm->online_vcpus, 0);
 164
 165         mutex_unlock(&kvm->lock);
 166 }
 167
 168 static void kvm_mips_uninit_tlbs(void *arg)
 169 {
 170         /* Restore wired count */
 171         write_c0_wired(0);
 172         mtc0_tlbw_hazard();
 173         /* Clear out all the TLBs */
 174         kvm_local_flush_tlb_all();
 175 }
 176
 177 void kvm_arch_destroy_vm(struct kvm *kvm)
 178 {
 179         kvm_mips_free_vcpus(kvm);
 180
 181         /* If this is the last instance, restore wired count */
 182         if (atomic_dec_return(&kvm_mips_instance) == 0) {
 183                 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
 184                           __func__);
 185                 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
 186         }
 187 }
 188
 189 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 190                         unsigned long arg)
 191 {
 192         return -ENOIOCTLCMD;
 193 }
 194
 195 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 196                             unsigned long npages)
 197 {
 198         return 0;
 199 }
 200
 201 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 202                                    struct kvm_memory_slot *memslot,
 203                                    const struct kvm_userspace_memory_region *mem,
 204                                    enum kvm_mr_change change)
 205 {
 206         return 0;
 207 }
 208
 209 void kvm_arch_commit_memory_region(struct kvm *kvm,
 210                                    const struct kvm_userspace_memory_region *mem,
 211                                    const struct kvm_memory_slot *old,
 212                                    const struct kvm_memory_slot *new,
 213                                    enum kvm_mr_change change)
 214 {
 215         unsigned long npages = 0;
 216         int i;
 217
 218         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 219                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 220                   mem->memory_size, mem->userspace_addr);
 221
 222         /* Setup Guest PMAP table */
 223         if (!kvm->arch.guest_pmap) {
 224                 if (mem->slot == 0)
 225                         npages = mem->memory_size >> PAGE_SHIFT;
 226
 227                 if (npages) {
 228                         kvm->arch.guest_pmap_npages = npages;
 229                         kvm->arch.guest_pmap =
 230                             kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
 231
 232                         if (!kvm->arch.guest_pmap) {
 233                                 kvm_err("Failed to allocate guest PMAP\n");
 234                                 return;
 235                         }
 236
 237                         kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
 238                                   npages, kvm->arch.guest_pmap);
 239
 240                         /* Now setup the page table */
 241                         for (i = 0; i < npages; i++)
 242                                 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
 243                 }
 244         }
 245 }
 246
 247 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 248 {
 249         int err, size, offset;
 250         void *gebase;
 251         int i;
 252
 253         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 254
 255         if (!vcpu) {
 256                 err = -ENOMEM;
 257                 goto out;
 258         }
 259
 260         err = kvm_vcpu_init(vcpu, kvm, id);
 261
 262         if (err)
 263                 goto out_free_cpu;
 264
 265         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 266
 267         /*
 268          * Allocate space for host mode exception handlers that handle
 269          * guest mode exits
 270          */
 271         if (cpu_has_veic || cpu_has_vint)
 272                 size = 0x200 + VECTORSPACING * 64;
 273         else
 274                 size = 0x4000;
 275
 276         /* Save Linux EBASE */
 277         vcpu->arch.host_ebase = (void *)read_c0_ebase();
 278
 279         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 280
 281         if (!gebase) {
 282                 err = -ENOMEM;
 283                 goto out_uninit_cpu;
 284         }
 285         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 286                   ALIGN(size, PAGE_SIZE), gebase);
 287
 288         /* Save new ebase */
 289         vcpu->arch.guest_ebase = gebase;
 290
 291         /* Copy L1 Guest Exception handler to correct offset */
 292
 293         /* TLB Refill, EXL = 0 */
 294         memcpy(gebase, mips32_exception,
 295                mips32_exceptionEnd - mips32_exception);
 296
 297         /* General Exception Entry point */
 298         memcpy(gebase + 0x180, mips32_exception,
 299                mips32_exceptionEnd - mips32_exception);
 300
 301         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 302         for (i = 0; i < 8; i++) {
 303                 kvm_debug("L1 Vectored handler @ %p\n",
 304                           gebase + 0x200 + (i * VECTORSPACING));
 305                 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
 306                        mips32_exceptionEnd - mips32_exception);
 307         }
 308
 309         /* General handler, relocate to unmapped space for sanity's sake */
 310         offset = 0x2000;
 311         kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
 312                   gebase + offset,
 313                   mips32_GuestExceptionEnd - mips32_GuestException);
 314
 315         memcpy(gebase + offset, mips32_GuestException,
 316                mips32_GuestExceptionEnd - mips32_GuestException);
 317
 318         /* Invalidate the icache for these ranges */
 319         local_flush_icache_range((unsigned long)gebase,
 320                                 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 321
 322         /*
 323          * Allocate comm page for guest kernel, a TLB will be reserved for
 324          * mapping GVA @ 0xFFFF8000 to this page
 325          */
 326         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 327
 328         if (!vcpu->arch.kseg0_commpage) {
 329                 err = -ENOMEM;
 330                 goto out_free_gebase;
 331         }
 332
 333         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 334         kvm_mips_commpage_init(vcpu);
 335
 336         /* Init */
 337         vcpu->arch.last_sched_cpu = -1;
 338
 339         /* Start off the timer */
 340         kvm_mips_init_count(vcpu);
 341
 342         return vcpu;
 343
 344 out_free_gebase:
 345         kfree(gebase);
 346
 347 out_uninit_cpu:
 348         kvm_vcpu_uninit(vcpu);
 349
 350 out_free_cpu:
 351         kfree(vcpu);
 352
 353 out:
 354         return ERR_PTR(err);
 355 }
 356
 357 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 358 {
 359         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 360
 361         kvm_vcpu_uninit(vcpu);
 362
 363         kvm_mips_dump_stats(vcpu);
 364
 365         kfree(vcpu->arch.guest_ebase);
 366         kfree(vcpu->arch.kseg0_commpage);
 367         kfree(vcpu);
 368 }
 369
 370 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 371 {
 372         kvm_arch_vcpu_free(vcpu);
 373 }
 374
 375 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 376                                         struct kvm_guest_debug *dbg)
 377 {
 378         return -ENOIOCTLCMD;
 379 }
 380
 381 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 382 {
 383         int r = 0;
 384         sigset_t sigsaved;
 385
 386         if (vcpu->sigset_active)
 387                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 388
 389         if (vcpu->mmio_needed) {
 390                 if (!vcpu->mmio_is_write)
 391                         kvm_mips_complete_mmio_load(vcpu, run);
 392                 vcpu->mmio_needed = 0;
 393         }
 394
 395         lose_fpu(1);
 396
 397         local_irq_disable();
 398         /* Check if we have any exceptions/interrupts pending */
 399         kvm_mips_deliver_interrupts(vcpu,
 400                                     kvm_read_c0_guest_cause(vcpu->arch.cop0));
 401
 402         __kvm_guest_enter();
 403
 404         /* Disable hardware page table walking while in guest */
 405         htw_stop();
 406
 407         r = __kvm_mips_vcpu_run(run, vcpu);
 408
 409         /* Re-enable HTW before enabling interrupts */
 410         htw_start();
 411
 412         __kvm_guest_exit();
 413         local_irq_enable();
 414
 415         if (vcpu->sigset_active)
 416                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 417
 418         return r;
 419 }
 420
 421 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 422                              struct kvm_mips_interrupt *irq)
 423 {
 424         int intr = (int)irq->irq;
 425         struct kvm_vcpu *dvcpu = NULL;
 426
 427         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 428                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 429                           (int)intr);
 430
 431         if (irq->cpu == -1)
 432                 dvcpu = vcpu;
 433         else
 434                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 435
 436         if (intr == 2 || intr == 3 || intr == 4) {
 437                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 438
 439         } else if (intr == -2 || intr == -3 || intr == -4) {
 440                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 441         } else {
 442                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 443                         irq->cpu, irq->irq);
 444                 return -EINVAL;
 445         }
 446
 447         dvcpu->arch.wait = 0;
 448
 449         if (swait_active(&dvcpu->wq))
 450                 swake_up(&dvcpu->wq);
 451
 452         return 0;
 453 }
 454
 455 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 456                                     struct kvm_mp_state *mp_state)
 457 {
 458         return -ENOIOCTLCMD;
 459 }
 460
 461 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 462                                     struct kvm_mp_state *mp_state)
 463 {
 464         return -ENOIOCTLCMD;
 465 }
 466
 467 static u64 kvm_mips_get_one_regs[] = {
 468         KVM_REG_MIPS_R0,
 469         KVM_REG_MIPS_R1,
 470         KVM_REG_MIPS_R2,
 471         KVM_REG_MIPS_R3,
 472         KVM_REG_MIPS_R4,
 473         KVM_REG_MIPS_R5,
 474         KVM_REG_MIPS_R6,
 475         KVM_REG_MIPS_R7,
 476         KVM_REG_MIPS_R8,
 477         KVM_REG_MIPS_R9,
 478         KVM_REG_MIPS_R10,
 479         KVM_REG_MIPS_R11,
 480         KVM_REG_MIPS_R12,
 481         KVM_REG_MIPS_R13,
 482         KVM_REG_MIPS_R14,
 483         KVM_REG_MIPS_R15,
 484         KVM_REG_MIPS_R16,
 485         KVM_REG_MIPS_R17,
 486         KVM_REG_MIPS_R18,
 487         KVM_REG_MIPS_R19,
 488         KVM_REG_MIPS_R20,
 489         KVM_REG_MIPS_R21,
 490         KVM_REG_MIPS_R22,
 491         KVM_REG_MIPS_R23,
 492         KVM_REG_MIPS_R24,
 493         KVM_REG_MIPS_R25,
 494         KVM_REG_MIPS_R26,
 495         KVM_REG_MIPS_R27,
 496         KVM_REG_MIPS_R28,
 497         KVM_REG_MIPS_R29,
 498         KVM_REG_MIPS_R30,
 499         KVM_REG_MIPS_R31,
 500
 501         KVM_REG_MIPS_HI,
 502         KVM_REG_MIPS_LO,
 503         KVM_REG_MIPS_PC,
 504
 505         KVM_REG_MIPS_CP0_INDEX,
 506         KVM_REG_MIPS_CP0_CONTEXT,
 507         KVM_REG_MIPS_CP0_USERLOCAL,
 508         KVM_REG_MIPS_CP0_PAGEMASK,
 509         KVM_REG_MIPS_CP0_WIRED,
 510         KVM_REG_MIPS_CP0_HWRENA,
 511         KVM_REG_MIPS_CP0_BADVADDR,
 512         KVM_REG_MIPS_CP0_COUNT,
 513         KVM_REG_MIPS_CP0_ENTRYHI,
 514         KVM_REG_MIPS_CP0_COMPARE,
 515         KVM_REG_MIPS_CP0_STATUS,
 516         KVM_REG_MIPS_CP0_CAUSE,
 517         KVM_REG_MIPS_CP0_EPC,
 518         KVM_REG_MIPS_CP0_PRID,
 519         KVM_REG_MIPS_CP0_CONFIG,
 520         KVM_REG_MIPS_CP0_CONFIG1,
 521         KVM_REG_MIPS_CP0_CONFIG2,
 522         KVM_REG_MIPS_CP0_CONFIG3,
 523         KVM_REG_MIPS_CP0_CONFIG4,
 524         KVM_REG_MIPS_CP0_CONFIG5,
 525         KVM_REG_MIPS_CP0_CONFIG7,
 526         KVM_REG_MIPS_CP0_ERROREPC,
 527
 528         KVM_REG_MIPS_COUNT_CTL,
 529         KVM_REG_MIPS_COUNT_RESUME,
 530         KVM_REG_MIPS_COUNT_HZ,
 531 };
 532
 533 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 534                             const struct kvm_one_reg *reg)
 535 {
 536         struct mips_coproc *cop0 = vcpu->arch.cop0;
 537         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 538         int ret;
 539         s64 v;
 540         s64 vs[2];
 541         unsigned int idx;
 542
 543         switch (reg->id) {
 544         /* General purpose registers */
 545         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 546                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 547                 break;
 548         case KVM_REG_MIPS_HI:
 549                 v = (long)vcpu->arch.hi;
 550                 break;
 551         case KVM_REG_MIPS_LO:
 552                 v = (long)vcpu->arch.lo;
 553                 break;
 554         case KVM_REG_MIPS_PC:
 555                 v = (long)vcpu->arch.pc;
 556                 break;
 557
 558         /* Floating point registers */
 559         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 560                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 561                         return -EINVAL;
 562                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 563                 /* Odd singles in top of even double when FR=0 */
 564                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 565                         v = get_fpr32(&fpu->fpr[idx], 0);
 566                 else
 567                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 568                 break;
 569         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 570                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 571                         return -EINVAL;
 572                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 573                 /* Can't access odd doubles in FR=0 mode */
 574                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 575                         return -EINVAL;
 576                 v = get_fpr64(&fpu->fpr[idx], 0);
 577                 break;
 578         case KVM_REG_MIPS_FCR_IR:
 579                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 580                         return -EINVAL;
 581                 v = boot_cpu_data.fpu_id;
 582                 break;
 583         case KVM_REG_MIPS_FCR_CSR:
 584                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 585                         return -EINVAL;
 586                 v = fpu->fcr31;
 587                 break;
 588
 589         /* MIPS SIMD Architecture (MSA) registers */
 590         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 591                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 592                         return -EINVAL;
 593                 /* Can't access MSA registers in FR=0 mode */
 594                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 595                         return -EINVAL;
 596                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 597 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 598                 /* least significant byte first */
 599                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 600                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 601 #else
 602                 /* most significant byte first */
 603                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 604                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 605 #endif
 606                 break;
 607         case KVM_REG_MIPS_MSA_IR:
 608                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 609                         return -EINVAL;
 610                 v = boot_cpu_data.msa_id;
 611                 break;
 612         case KVM_REG_MIPS_MSA_CSR:
 613                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 614                         return -EINVAL;
 615                 v = fpu->msacsr;
 616                 break;
 617
 618         /* Co-processor 0 registers */
 619         case KVM_REG_MIPS_CP0_INDEX:
 620                 v = (long)kvm_read_c0_guest_index(cop0);
 621                 break;
 622         case KVM_REG_MIPS_CP0_CONTEXT:
 623                 v = (long)kvm_read_c0_guest_context(cop0);
 624                 break;
 625         case KVM_REG_MIPS_CP0_USERLOCAL:
 626                 v = (long)kvm_read_c0_guest_userlocal(cop0);
 627                 break;
 628         case KVM_REG_MIPS_CP0_PAGEMASK:
 629                 v = (long)kvm_read_c0_guest_pagemask(cop0);
 630                 break;
 631         case KVM_REG_MIPS_CP0_WIRED:
 632                 v = (long)kvm_read_c0_guest_wired(cop0);
 633                 break;
 634         case KVM_REG_MIPS_CP0_HWRENA:
 635                 v = (long)kvm_read_c0_guest_hwrena(cop0);
 636                 break;
 637         case KVM_REG_MIPS_CP0_BADVADDR:
 638                 v = (long)kvm_read_c0_guest_badvaddr(cop0);
 639                 break;
 640         case KVM_REG_MIPS_CP0_ENTRYHI:
 641                 v = (long)kvm_read_c0_guest_entryhi(cop0);
 642                 break;
 643         case KVM_REG_MIPS_CP0_COMPARE:
 644                 v = (long)kvm_read_c0_guest_compare(cop0);
 645                 break;
 646         case KVM_REG_MIPS_CP0_STATUS:
 647                 v = (long)kvm_read_c0_guest_status(cop0);
 648                 break;
 649         case KVM_REG_MIPS_CP0_CAUSE:
 650                 v = (long)kvm_read_c0_guest_cause(cop0);
 651                 break;
 652         case KVM_REG_MIPS_CP0_EPC:
 653                 v = (long)kvm_read_c0_guest_epc(cop0);
 654                 break;
 655         case KVM_REG_MIPS_CP0_PRID:
 656                 v = (long)kvm_read_c0_guest_prid(cop0);
 657                 break;
 658         case KVM_REG_MIPS_CP0_CONFIG:
 659                 v = (long)kvm_read_c0_guest_config(cop0);
 660                 break;
 661         case KVM_REG_MIPS_CP0_CONFIG1:
 662                 v = (long)kvm_read_c0_guest_config1(cop0);
 663                 break;
 664         case KVM_REG_MIPS_CP0_CONFIG2:
 665                 v = (long)kvm_read_c0_guest_config2(cop0);
 666                 break;
 667         case KVM_REG_MIPS_CP0_CONFIG3:
 668                 v = (long)kvm_read_c0_guest_config3(cop0);
 669                 break;
 670         case KVM_REG_MIPS_CP0_CONFIG4:
 671                 v = (long)kvm_read_c0_guest_config4(cop0);
 672                 break;
 673         case KVM_REG_MIPS_CP0_CONFIG5:
 674                 v = (long)kvm_read_c0_guest_config5(cop0);
 675                 break;
 676         case KVM_REG_MIPS_CP0_CONFIG7:
 677                 v = (long)kvm_read_c0_guest_config7(cop0);
 678                 break;
 679         case KVM_REG_MIPS_CP0_ERROREPC:
 680                 v = (long)kvm_read_c0_guest_errorepc(cop0);
 681                 break;
 682         /* registers to be handled specially */
 683         case KVM_REG_MIPS_CP0_COUNT:
 684         case KVM_REG_MIPS_COUNT_CTL:
 685         case KVM_REG_MIPS_COUNT_RESUME:
 686         case KVM_REG_MIPS_COUNT_HZ:
 687                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 688                 if (ret)
 689                         return ret;
 690                 break;
 691         default:
 692                 return -EINVAL;
 693         }
 694         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 695                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 696
 697                 return put_user(v, uaddr64);
 698         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 699                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 700                 u32 v32 = (u32)v;
 701
 702                 return put_user(v32, uaddr32);
 703         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 704                 void __user *uaddr = (void __user *)(long)reg->addr;
 705
 706                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 707         } else {
 708                 return -EINVAL;
 709         }
 710 }
 711
 712 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 713                             const struct kvm_one_reg *reg)
 714 {
 715         struct mips_coproc *cop0 = vcpu->arch.cop0;
 716         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 717         s64 v;
 718         s64 vs[2];
 719         unsigned int idx;
 720
 721         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 722                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 723
 724                 if (get_user(v, uaddr64) != 0)
 725                         return -EFAULT;
 726         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 727                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 728                 s32 v32;
 729
 730                 if (get_user(v32, uaddr32) != 0)
 731                         return -EFAULT;
 732                 v = (s64)v32;
 733         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 734                 void __user *uaddr = (void __user *)(long)reg->addr;
 735
 736                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 737         } else {
 738                 return -EINVAL;
 739         }
 740
 741         switch (reg->id) {
 742         /* General purpose registers */
 743         case KVM_REG_MIPS_R0:
 744                 /* Silently ignore requests to set $0 */
 745                 break;
 746         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 747                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 748                 break;
 749         case KVM_REG_MIPS_HI:
 750                 vcpu->arch.hi = v;
 751                 break;
 752         case KVM_REG_MIPS_LO:
 753                 vcpu->arch.lo = v;
 754                 break;
 755         case KVM_REG_MIPS_PC:
 756                 vcpu->arch.pc = v;
 757                 break;
 758
 759         /* Floating point registers */
 760         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 761                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 762                         return -EINVAL;
 763                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 764                 /* Odd singles in top of even double when FR=0 */
 765                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 766                         set_fpr32(&fpu->fpr[idx], 0, v);
 767                 else
 768                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 769                 break;
 770         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 771                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 772                         return -EINVAL;
 773                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 774                 /* Can't access odd doubles in FR=0 mode */
 775                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 776                         return -EINVAL;
 777                 set_fpr64(&fpu->fpr[idx], 0, v);
 778                 break;
 779         case KVM_REG_MIPS_FCR_IR:
 780                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 781                         return -EINVAL;
 782                 /* Read-only */
 783                 break;
 784         case KVM_REG_MIPS_FCR_CSR:
 785                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 786                         return -EINVAL;
 787                 fpu->fcr31 = v;
 788                 break;
 789
 790         /* MIPS SIMD Architecture (MSA) registers */
 791         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 792                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 793                         return -EINVAL;
 794                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 795 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 796                 /* least significant byte first */
 797                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 798                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 799 #else
 800                 /* most significant byte first */
 801                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 802                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 803 #endif
 804                 break;
 805         case KVM_REG_MIPS_MSA_IR:
 806                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 807                         return -EINVAL;
 808                 /* Read-only */
 809                 break;
 810         case KVM_REG_MIPS_MSA_CSR:
 811                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 812                         return -EINVAL;
 813                 fpu->msacsr = v;
 814                 break;
 815
 816         /* Co-processor 0 registers */
 817         case KVM_REG_MIPS_CP0_INDEX:
 818                 kvm_write_c0_guest_index(cop0, v);
 819                 break;
 820         case KVM_REG_MIPS_CP0_CONTEXT:
 821                 kvm_write_c0_guest_context(cop0, v);
 822                 break;
 823         case KVM_REG_MIPS_CP0_USERLOCAL:
 824                 kvm_write_c0_guest_userlocal(cop0, v);
 825                 break;
 826         case KVM_REG_MIPS_CP0_PAGEMASK:
 827                 kvm_write_c0_guest_pagemask(cop0, v);
 828                 break;
 829         case KVM_REG_MIPS_CP0_WIRED:
 830                 kvm_write_c0_guest_wired(cop0, v);
 831                 break;
 832         case KVM_REG_MIPS_CP0_HWRENA:
 833                 kvm_write_c0_guest_hwrena(cop0, v);
 834                 break;
 835         case KVM_REG_MIPS_CP0_BADVADDR:
 836                 kvm_write_c0_guest_badvaddr(cop0, v);
 837                 break;
 838         case KVM_REG_MIPS_CP0_ENTRYHI:
 839                 kvm_write_c0_guest_entryhi(cop0, v);
 840                 break;
 841         case KVM_REG_MIPS_CP0_STATUS:
 842                 kvm_write_c0_guest_status(cop0, v);
 843                 break;
 844         case KVM_REG_MIPS_CP0_EPC:
 845                 kvm_write_c0_guest_epc(cop0, v);
 846                 break;
 847         case KVM_REG_MIPS_CP0_PRID:
 848                 kvm_write_c0_guest_prid(cop0, v);
 849                 break;
 850         case KVM_REG_MIPS_CP0_ERROREPC:
 851                 kvm_write_c0_guest_errorepc(cop0, v);
 852                 break;
 853         /* registers to be handled specially */
 854         case KVM_REG_MIPS_CP0_COUNT:
 855         case KVM_REG_MIPS_CP0_COMPARE:
 856         case KVM_REG_MIPS_CP0_CAUSE:
 857         case KVM_REG_MIPS_CP0_CONFIG:
 858         case KVM_REG_MIPS_CP0_CONFIG1:
 859         case KVM_REG_MIPS_CP0_CONFIG2:
 860         case KVM_REG_MIPS_CP0_CONFIG3:
 861         case KVM_REG_MIPS_CP0_CONFIG4:
 862         case KVM_REG_MIPS_CP0_CONFIG5:
 863         case KVM_REG_MIPS_COUNT_CTL:
 864         case KVM_REG_MIPS_COUNT_RESUME:
 865         case KVM_REG_MIPS_COUNT_HZ:
 866                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 867         default:
 868                 return -EINVAL;
 869         }
 870         return 0;
 871 }
 872
 873 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 874                                      struct kvm_enable_cap *cap)
 875 {
 876         int r = 0;
 877
 878         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 879                 return -EINVAL;
 880         if (cap->flags)
 881                 return -EINVAL;
 882         if (cap->args[0])
 883                 return -EINVAL;
 884
 885         switch (cap->cap) {
 886         case KVM_CAP_MIPS_FPU:
 887                 vcpu->arch.fpu_enabled = true;
 888                 break;
 889         case KVM_CAP_MIPS_MSA:
 890                 vcpu->arch.msa_enabled = true;
 891                 break;
 892         default:
 893                 r = -EINVAL;
 894                 break;
 895         }
 896
 897         return r;
 898 }
 899
 900 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 901                          unsigned long arg)
 902 {
 903         struct kvm_vcpu *vcpu = filp->private_data;
 904         void __user *argp = (void __user *)arg;
 905         long r;
 906
 907         switch (ioctl) {
 908         case KVM_SET_ONE_REG:
 909         case KVM_GET_ONE_REG: {
 910                 struct kvm_one_reg reg;
 911
 912                 if (copy_from_user(&reg, argp, sizeof(reg)))
 913                         return -EFAULT;
 914                 if (ioctl == KVM_SET_ONE_REG)
 915                         return kvm_mips_set_reg(vcpu, &reg);
 916                 else
 917                         return kvm_mips_get_reg(vcpu, &reg);
 918         }
 919         case KVM_GET_REG_LIST: {
 920                 struct kvm_reg_list __user *user_list = argp;
 921                 u64 __user *reg_dest;
 922                 struct kvm_reg_list reg_list;
 923                 unsigned n;
 924
 925                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 926                         return -EFAULT;
 927                 n = reg_list.n;
 928                 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
 929                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 930                         return -EFAULT;
 931                 if (n < reg_list.n)
 932                         return -E2BIG;
 933                 reg_dest = user_list->reg;
 934                 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
 935                                  sizeof(kvm_mips_get_one_regs)))
 936                         return -EFAULT;
 937                 return 0;
 938         }
 939         case KVM_NMI:
 940                 /* Treat the NMI as a CPU reset */
 941                 r = kvm_mips_reset_vcpu(vcpu);
 942                 break;
 943         case KVM_INTERRUPT:
 944                 {
 945                         struct kvm_mips_interrupt irq;
 946
 947                         r = -EFAULT;
 948                         if (copy_from_user(&irq, argp, sizeof(irq)))
 949                                 goto out;
 950
 951                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 952                                   irq.irq);
 953
 954                         r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 955                         break;
 956                 }
 957         case KVM_ENABLE_CAP: {
 958                 struct kvm_enable_cap cap;
 959
 960                 r = -EFAULT;
 961                 if (copy_from_user(&cap, argp, sizeof(cap)))
 962                         goto out;
 963                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 964                 break;
 965         }
 966         default:
 967                 r = -ENOIOCTLCMD;
 968         }
 969
 970 out:
 971         return r;
 972 }
 973
 974 /* Get (and clear) the dirty memory log for a memory slot. */
 975 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
 976 {
 977         struct kvm_memslots *slots;
 978         struct kvm_memory_slot *memslot;
 979         unsigned long ga, ga_end;
 980         int is_dirty = 0;
 981         int r;
 982         unsigned long n;
 983
 984         mutex_lock(&kvm->slots_lock);
 985
 986         r = kvm_get_dirty_log(kvm, log, &is_dirty);
 987         if (r)
 988                 goto out;
 989
 990         /* If nothing is dirty, don't bother messing with page tables. */
 991         if (is_dirty) {
 992                 slots = kvm_memslots(kvm);
 993                 memslot = id_to_memslot(slots, log->slot);
 994
 995                 ga = memslot->base_gfn << PAGE_SHIFT;
 996                 ga_end = ga + (memslot->npages << PAGE_SHIFT);
 997
 998                 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
 999                          ga_end);
1000
1001                 n = kvm_dirty_bitmap_bytes(memslot);
1002                 memset(memslot->dirty_bitmap, 0, n);
1003         }
1004
1005         r = 0;
1006 out:
1007         mutex_unlock(&kvm->slots_lock);
1008         return r;
1009
1010 }
1011
1012 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1013 {
1014         long r;
1015
1016         switch (ioctl) {
1017         default:
1018                 r = -ENOIOCTLCMD;
1019         }
1020
1021         return r;
1022 }
1023
1024 int kvm_arch_init(void *opaque)
1025 {
1026         if (kvm_mips_callbacks) {
1027                 kvm_err("kvm: module already exists\n");
1028                 return -EEXIST;
1029         }
1030
1031         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1032 }
1033
1034 void kvm_arch_exit(void)
1035 {
1036         kvm_mips_callbacks = NULL;
1037 }
1038
1039 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1040                                   struct kvm_sregs *sregs)
1041 {
1042         return -ENOIOCTLCMD;
1043 }
1044
1045 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1046                                   struct kvm_sregs *sregs)
1047 {
1048         return -ENOIOCTLCMD;
1049 }
1050
1051 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1052 {
1053 }
1054
1055 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1056 {
1057         return -ENOIOCTLCMD;
1058 }
1059
1060 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1061 {
1062         return -ENOIOCTLCMD;
1063 }
1064
1065 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1066 {
1067         return VM_FAULT_SIGBUS;
1068 }
1069
1070 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1071 {
1072         int r;
1073
1074         switch (ext) {
1075         case KVM_CAP_ONE_REG:
1076         case KVM_CAP_ENABLE_CAP:
1077                 r = 1;
1078                 break;
1079         case KVM_CAP_COALESCED_MMIO:
1080                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1081                 break;
1082         case KVM_CAP_MIPS_FPU:
1083                 /* We don't handle systems with inconsistent cpu_has_fpu */
1084                 r = !!raw_cpu_has_fpu;
1085                 break;
1086         case KVM_CAP_MIPS_MSA:
1087                 /*
1088                  * We don't support MSA vector partitioning yet:
1089                  * 1) It would require explicit support which can't be tested
1090                  *    yet due to lack of support in current hardware.
1091                  * 2) It extends the state that would need to be saved/restored
1092                  *    by e.g. QEMU for migration.
1093                  *
1094                  * When vector partitioning hardware becomes available, support
1095                  * could be added by requiring a flag when enabling
1096                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1097                  * to save/restore the appropriate extra state.
1098                  */
1099                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1100                 break;
1101         default:
1102                 r = 0;
1103                 break;
1104         }
1105         return r;
1106 }
1107
1108 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1109 {
1110         return kvm_mips_pending_timer(vcpu);
1111 }
1112
1113 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1114 {
1115         int i;
1116         struct mips_coproc *cop0;
1117
1118         if (!vcpu)
1119                 return -1;
1120
1121         kvm_debug("VCPU Register Dump:\n");
1122         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1123         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1124
1125         for (i = 0; i < 32; i += 4) {
1126                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1127                        vcpu->arch.gprs[i],
1128                        vcpu->arch.gprs[i + 1],
1129                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1130         }
1131         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1132         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1133
1134         cop0 = vcpu->arch.cop0;
1135         kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1136                   kvm_read_c0_guest_status(cop0),
1137                   kvm_read_c0_guest_cause(cop0));
1138
1139         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1140
1141         return 0;
1142 }
1143
1144 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1145 {
1146         int i;
1147
1148         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1149                 vcpu->arch.gprs[i] = regs->gpr[i];
1150         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1151         vcpu->arch.hi = regs->hi;
1152         vcpu->arch.lo = regs->lo;
1153         vcpu->arch.pc = regs->pc;
1154
1155         return 0;
1156 }
1157
1158 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1159 {
1160         int i;
1161
1162         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1163                 regs->gpr[i] = vcpu->arch.gprs[i];
1164
1165         regs->hi = vcpu->arch.hi;
1166         regs->lo = vcpu->arch.lo;
1167         regs->pc = vcpu->arch.pc;
1168
1169         return 0;
1170 }
1171
1172 static void kvm_mips_comparecount_func(unsigned long data)
1173 {
1174         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1175
1176         kvm_mips_callbacks->queue_timer_int(vcpu);
1177
1178         vcpu->arch.wait = 0;
1179         if (swait_active(&vcpu->wq))
1180                 swake_up(&vcpu->wq);
1181 }
1182
1183 /* low level hrtimer wake routine */
1184 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1185 {
1186         struct kvm_vcpu *vcpu;
1187
1188         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1189         kvm_mips_comparecount_func((unsigned long) vcpu);
1190         return kvm_mips_count_timeout(vcpu);
1191 }
1192
1193 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1194 {
1195         kvm_mips_callbacks->vcpu_init(vcpu);
1196         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1197                      HRTIMER_MODE_REL);
1198         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1199         return 0;
1200 }
1201
1202 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1203                                   struct kvm_translation *tr)
1204 {
1205         return 0;
1206 }
1207
1208 /* Initial guest state */
1209 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1210 {
1211         return kvm_mips_callbacks->vcpu_setup(vcpu);
1212 }
1213
1214 static void kvm_mips_set_c0_status(void)
1215 {
1216         uint32_t status = read_c0_status();
1217
1218         if (cpu_has_dsp)
1219                 status |= (ST0_MX);
1220
1221         write_c0_status(status);
1222         ehb();
1223 }
1224
1225 /*
1226  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1227  */
1228 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1229 {
1230         uint32_t cause = vcpu->arch.host_cp0_cause;
1231         uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1232         uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
1233         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1234         enum emulation_result er = EMULATE_DONE;
1235         int ret = RESUME_GUEST;
1236
1237         /* re-enable HTW before enabling interrupts */
1238         htw_start();
1239
1240         /* Set a default exit reason */
1241         run->exit_reason = KVM_EXIT_UNKNOWN;
1242         run->ready_for_interrupt_injection = 1;
1243
1244         /*
1245          * Set the appropriate status bits based on host CPU features,
1246          * before we hit the scheduler
1247          */
1248         kvm_mips_set_c0_status();
1249
1250         local_irq_enable();
1251
1252         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1253                         cause, opc, run, vcpu);
1254
1255         /*
1256          * Do a privilege check, if in UM most of these exit conditions end up
1257          * causing an exception to be delivered to the Guest Kernel
1258          */
1259         er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1260         if (er == EMULATE_PRIV_FAIL) {
1261                 goto skip_emul;
1262         } else if (er == EMULATE_FAIL) {
1263                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1264                 ret = RESUME_HOST;
1265                 goto skip_emul;
1266         }
1267
1268         switch (exccode) {
1269         case EXCCODE_INT:
1270                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1271
1272                 ++vcpu->stat.int_exits;
1273                 trace_kvm_exit(vcpu, INT_EXITS);
1274
1275                 if (need_resched())
1276                         cond_resched();
1277
1278                 ret = RESUME_GUEST;
1279                 break;
1280
1281         case EXCCODE_CPU:
1282                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1283
1284                 ++vcpu->stat.cop_unusable_exits;
1285                 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1286                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1287                 /* XXXKYMA: Might need to return to user space */
1288                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1289                         ret = RESUME_HOST;
1290                 break;
1291
1292         case EXCCODE_MOD:
1293                 ++vcpu->stat.tlbmod_exits;
1294                 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1295                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1296                 break;
1297
1298         case EXCCODE_TLBS:
1299                 kvm_debug("TLB ST fault:  cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1300                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1301                           badvaddr);
1302
1303                 ++vcpu->stat.tlbmiss_st_exits;
1304                 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1305                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1306                 break;
1307
1308         case EXCCODE_TLBL:
1309                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1310                           cause, opc, badvaddr);
1311
1312                 ++vcpu->stat.tlbmiss_ld_exits;
1313                 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1314                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1315                 break;
1316
1317         case EXCCODE_ADES:
1318                 ++vcpu->stat.addrerr_st_exits;
1319                 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1320                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1321                 break;
1322
1323         case EXCCODE_ADEL:
1324                 ++vcpu->stat.addrerr_ld_exits;
1325                 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1326                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1327                 break;
1328
1329         case EXCCODE_SYS:
1330                 ++vcpu->stat.syscall_exits;
1331                 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1332                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1333                 break;
1334
1335         case EXCCODE_RI:
1336                 ++vcpu->stat.resvd_inst_exits;
1337                 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1338                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1339                 break;
1340
1341         case EXCCODE_BP:
1342                 ++vcpu->stat.break_inst_exits;
1343                 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1344                 ret = kvm_mips_callbacks->handle_break(vcpu);
1345                 break;
1346
1347         case EXCCODE_TR:
1348                 ++vcpu->stat.trap_inst_exits;
1349                 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1350                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1351                 break;
1352
1353         case EXCCODE_MSAFPE:
1354                 ++vcpu->stat.msa_fpe_exits;
1355                 trace_kvm_exit(vcpu, MSA_FPE_EXITS);
1356                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1357                 break;
1358
1359         case EXCCODE_FPE:
1360                 ++vcpu->stat.fpe_exits;
1361                 trace_kvm_exit(vcpu, FPE_EXITS);
1362                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1363                 break;
1364
1365         case EXCCODE_MSADIS:
1366                 ++vcpu->stat.msa_disabled_exits;
1367                 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS);
1368                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1369                 break;
1370
1371         default:
1372                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#lx\n",
1373                         exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1374                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1375                 kvm_arch_vcpu_dump_regs(vcpu);
1376                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1377                 ret = RESUME_HOST;
1378                 break;
1379
1380         }
1381
1382 skip_emul:
1383         local_irq_disable();
1384
1385         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1386                 kvm_mips_deliver_interrupts(vcpu, cause);
1387
1388         if (!(ret & RESUME_HOST)) {
1389                 /* Only check for signals if not already exiting to userspace */
1390                 if (signal_pending(current)) {
1391                         run->exit_reason = KVM_EXIT_INTR;
1392                         ret = (-EINTR << 2) | RESUME_HOST;
1393                         ++vcpu->stat.signal_exits;
1394                         trace_kvm_exit(vcpu, SIGNAL_EXITS);
1395                 }
1396         }
1397
1398         if (ret == RESUME_GUEST) {
1399                 /*
1400                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1401                  * is live), restore FCR31 / MSACSR.
1402                  *
1403                  * This should be before returning to the guest exception
1404                  * vector, as it may well cause an [MSA] FP exception if there
1405                  * are pending exception bits unmasked. (see
1406                  * kvm_mips_csr_die_notifier() for how that is handled).
1407                  */
1408                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1409                     read_c0_status() & ST0_CU1)
1410                         __kvm_restore_fcsr(&vcpu->arch);
1411
1412                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1413                     read_c0_config5() & MIPS_CONF5_MSAEN)
1414                         __kvm_restore_msacsr(&vcpu->arch);
1415         }
1416
1417         /* Disable HTW before returning to guest or host */
1418         htw_stop();
1419
1420         return ret;
1421 }
1422
1423 /* Enable FPU for guest and restore context */
1424 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1425 {
1426         struct mips_coproc *cop0 = vcpu->arch.cop0;
1427         unsigned int sr, cfg5;
1428
1429         preempt_disable();
1430
1431         sr = kvm_read_c0_guest_status(cop0);
1432
1433         /*
1434          * If MSA state is already live, it is undefined how it interacts with
1435          * FR=0 FPU state, and we don't want to hit reserved instruction
1436          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1437          * play it safe and save it first.
1438          *
1439          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1440          * get called when guest CU1 is set, however we can't trust the guest
1441          * not to clobber the status register directly via the commpage.
1442          */
1443         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1444             vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1445                 kvm_lose_fpu(vcpu);
1446
1447         /*
1448          * Enable FPU for guest
1449          * We set FR and FRE according to guest context
1450          */
1451         change_c0_status(ST0_CU1 | ST0_FR, sr);
1452         if (cpu_has_fre) {
1453                 cfg5 = kvm_read_c0_guest_config5(cop0);
1454                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1455         }
1456         enable_fpu_hazard();
1457
1458         /* If guest FPU state not active, restore it now */
1459         if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
1460                 __kvm_restore_fpu(&vcpu->arch);
1461                 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1462         }
1463
1464         preempt_enable();
1465 }
1466
1467 #ifdef CONFIG_CPU_HAS_MSA
1468 /* Enable MSA for guest and restore context */
1469 void kvm_own_msa(struct kvm_vcpu *vcpu)
1470 {
1471         struct mips_coproc *cop0 = vcpu->arch.cop0;
1472         unsigned int sr, cfg5;
1473
1474         preempt_disable();
1475
1476         /*
1477          * Enable FPU if enabled in guest, since we're restoring FPU context
1478          * anyway. We set FR and FRE according to guest context.
1479          */
1480         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1481                 sr = kvm_read_c0_guest_status(cop0);
1482
1483                 /*
1484                  * If FR=0 FPU state is already live, it is undefined how it
1485                  * interacts with MSA state, so play it safe and save it first.
1486                  */
1487                 if (!(sr & ST0_FR) &&
1488                     (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU |
1489                                 KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU)
1490                         kvm_lose_fpu(vcpu);
1491
1492                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1493                 if (sr & ST0_CU1 && cpu_has_fre) {
1494                         cfg5 = kvm_read_c0_guest_config5(cop0);
1495                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1496                 }
1497         }
1498
1499         /* Enable MSA for guest */
1500         set_c0_config5(MIPS_CONF5_MSAEN);
1501         enable_fpu_hazard();
1502
1503         switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) {
1504         case KVM_MIPS_FPU_FPU:
1505                 /*
1506                  * Guest FPU state already loaded, only restore upper MSA state
1507                  */
1508                 __kvm_restore_msa_upper(&vcpu->arch);
1509                 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1510                 break;
1511         case 0:
1512                 /* Neither FPU or MSA already active, restore full MSA state */
1513                 __kvm_restore_msa(&vcpu->arch);
1514                 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1515                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1516                         vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1517                 break;
1518         default:
1519                 break;
1520         }
1521
1522         preempt_enable();
1523 }
1524 #endif
1525
1526 /* Drop FPU & MSA without saving it */
1527 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1528 {
1529         preempt_disable();
1530         if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1531                 disable_msa();
1532                 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA;
1533         }
1534         if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1535                 clear_c0_status(ST0_CU1 | ST0_FR);
1536                 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1537         }
1538         preempt_enable();
1539 }
1540
1541 /* Save and disable FPU & MSA */
1542 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1543 {
1544         /*
1545          * FPU & MSA get disabled in root context (hardware) when it is disabled
1546          * in guest context (software), but the register state in the hardware
1547          * may still be in use. This is why we explicitly re-enable the hardware
1548          * before saving.
1549          */
1550
1551         preempt_disable();
1552         if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1553                 set_c0_config5(MIPS_CONF5_MSAEN);
1554                 enable_fpu_hazard();
1555
1556                 __kvm_save_msa(&vcpu->arch);
1557
1558                 /* Disable MSA & FPU */
1559                 disable_msa();
1560                 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1561                         clear_c0_status(ST0_CU1 | ST0_FR);
1562                         disable_fpu_hazard();
1563                 }
1564                 vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA);
1565         } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1566                 set_c0_status(ST0_CU1);
1567                 enable_fpu_hazard();
1568
1569                 __kvm_save_fpu(&vcpu->arch);
1570                 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1571
1572                 /* Disable FPU */
1573                 clear_c0_status(ST0_CU1 | ST0_FR);
1574                 disable_fpu_hazard();
1575         }
1576         preempt_enable();
1577 }
1578
1579 /*
1580  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1581  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1582  * exception if cause bits are set in the value being written.
1583  */
1584 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1585                                    unsigned long cmd, void *ptr)
1586 {
1587         struct die_args *args = (struct die_args *)ptr;
1588         struct pt_regs *regs = args->regs;
1589         unsigned long pc;
1590
1591         /* Only interested in FPE and MSAFPE */
1592         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1593                 return NOTIFY_DONE;
1594
1595         /* Return immediately if guest context isn't active */
1596         if (!(current->flags & PF_VCPU))
1597                 return NOTIFY_DONE;
1598
1599         /* Should never get here from user mode */
1600         BUG_ON(user_mode(regs));
1601
1602         pc = instruction_pointer(regs);
1603         switch (cmd) {
1604         case DIE_FP:
1605                 /* match 2nd instruction in __kvm_restore_fcsr */
1606                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1607                         return NOTIFY_DONE;
1608                 break;
1609         case DIE_MSAFP:
1610                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1611                 if (!cpu_has_msa ||
1612                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1613                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1614                         return NOTIFY_DONE;
1615                 break;
1616         }
1617
1618         /* Move PC forward a little and continue executing */
1619         instruction_pointer(regs) += 4;
1620
1621         return NOTIFY_STOP;
1622 }
1623
1624 static struct notifier_block kvm_mips_csr_die_notifier = {
1625         .notifier_call = kvm_mips_csr_die_notify,
1626 };
1627
1628 static int __init kvm_mips_init(void)
1629 {
1630         int ret;
1631
1632         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1633
1634         if (ret)
1635                 return ret;
1636
1637         register_die_notifier(&kvm_mips_csr_die_notifier);
1638
1639         /*
1640          * On MIPS, kernel modules are executed from "mapped space", which
1641          * requires TLBs. The TLB handling code is statically linked with
1642          * the rest of the kernel (tlb.c) to avoid the possibility of
1643          * double faulting. The issue is that the TLB code references
1644          * routines that are part of the the KVM module, which are only
1645          * available once the module is loaded.
1646          */
1647         kvm_mips_gfn_to_pfn = gfn_to_pfn;
1648         kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
1649         kvm_mips_is_error_pfn = is_error_pfn;
1650
1651         return 0;
1652 }
1653
1654 static void __exit kvm_mips_exit(void)
1655 {
1656         kvm_exit();
1657
1658         kvm_mips_gfn_to_pfn = NULL;
1659         kvm_mips_release_pfn_clean = NULL;
1660         kvm_mips_is_error_pfn = NULL;
1661
1662         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1663 }
1664
1665 module_init(kvm_mips_init);
1666 module_exit(kvm_mips_exit);
1667
1668 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);