arch/mips/lantiq/xway/sysctrl.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org>
   7  */
   8
   9 #include <linux/ioport.h>
  10 #include <linux/export.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/of.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/of_address.h>
  15
  16 #include <lantiq_soc.h>
  17
  18 #include "../clk.h"
  19 #include "../prom.h"
  20
  21 /* clock control register */
  22 #define CGU_IFCCR       0x0018
  23 /* system clock register */
  24 #define CGU_SYS         0x0010
  25 /* pci control register */
  26 #define CGU_PCICR       0x0034
  27 /* ephy configuration register */
  28 #define CGU_EPHY        0x10
  29 /* power control register */
  30 #define PMU_PWDCR       0x1C
  31 /* power status register */
  32 #define PMU_PWDSR       0x20
  33 /* power control register */
  34 #define PMU_PWDCR1      0x24
  35 /* power status register */
  36 #define PMU_PWDSR1      0x28
  37 /* power control register */
  38 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
  39 /* power status register */
  40 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
  41
  42 /* clock gates that we can en/disable */
  43 #define PMU_USB0_P      BIT(0)
  44 #define PMU_PCI         BIT(4)
  45 #define PMU_DMA         BIT(5)
  46 #define PMU_USB0        BIT(6)
  47 #define PMU_ASC0        BIT(7)
  48 #define PMU_EPHY        BIT(7)  /* ase */
  49 #define PMU_SPI         BIT(8)
  50 #define PMU_DFE         BIT(9)
  51 #define PMU_EBU         BIT(10)
  52 #define PMU_STP         BIT(11)
  53 #define PMU_GPT         BIT(12)
  54 #define PMU_AHBS        BIT(13) /* vr9 */
  55 #define PMU_FPI         BIT(14)
  56 #define PMU_AHBM        BIT(15)
  57 #define PMU_ASC1        BIT(17)
  58 #define PMU_PPE_QSB     BIT(18)
  59 #define PMU_PPE_SLL01   BIT(19)
  60 #define PMU_PPE_TC      BIT(21)
  61 #define PMU_PPE_EMA     BIT(22)
  62 #define PMU_PPE_DPLUM   BIT(23)
  63 #define PMU_PPE_DPLUS   BIT(24)
  64 #define PMU_USB1_P      BIT(26)
  65 #define PMU_USB1        BIT(27)
  66 #define PMU_SWITCH      BIT(28)
  67 #define PMU_PPE_TOP     BIT(29)
  68 #define PMU_GPHY        BIT(30)
  69 #define PMU_PCIE_CLK    BIT(31)
  70
  71 #define PMU1_PCIE_PHY   BIT(0)
  72 #define PMU1_PCIE_CTL   BIT(1)
  73 #define PMU1_PCIE_PDI   BIT(4)
  74 #define PMU1_PCIE_MSI   BIT(5)
  75
  76 #define pmu_w32(x, y)   ltq_w32((x), pmu_membase + (y))
  77 #define pmu_r32(x)      ltq_r32(pmu_membase + (x))
  78
  79 static void __iomem *pmu_membase;
  80 void __iomem *ltq_cgu_membase;
  81 void __iomem *ltq_ebu_membase;
  82
  83 /* legacy function kept alive to ease clkdev transition */
  84 void ltq_pmu_enable(unsigned int module)
  85 {
  86         int err = 1000000;
  87
  88         pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
  89         do {} while (--err && (pmu_r32(PMU_PWDSR) & module));
  90
  91         if (!err)
  92                 panic("activating PMU module failed!");
  93 }
  94 EXPORT_SYMBOL(ltq_pmu_enable);
  95
  96 /* legacy function kept alive to ease clkdev transition */
  97 void ltq_pmu_disable(unsigned int module)
  98 {
  99         pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
 100 }
 101 EXPORT_SYMBOL(ltq_pmu_disable);
 102
 103 /* enable a hw clock */
 104 static int cgu_enable(struct clk *clk)
 105 {
 106         ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
 107         return 0;
 108 }
 109
 110 /* disable a hw clock */
 111 static void cgu_disable(struct clk *clk)
 112 {
 113         ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
 114 }
 115
 116 /* enable a clock gate */
 117 static int pmu_enable(struct clk *clk)
 118 {
 119         int retry = 1000000;
 120
 121         pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
 122                 PWDCR(clk->module));
 123         do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits));
 124
 125         if (!retry)
 126                 panic("activating PMU module failed!\n");
 127
 128         return 0;
 129 }
 130
 131 /* disable a clock gate */
 132 static void pmu_disable(struct clk *clk)
 133 {
 134         pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
 135                 PWDCR(clk->module));
 136 }
 137
 138 /* the pci enable helper */
 139 static int pci_enable(struct clk *clk)
 140 {
 141         unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
 142         /* set bus clock speed */
 143         if (of_machine_is_compatible("lantiq,ar9")) {
 144                 ifccr &= ~0x1f00000;
 145                 if (clk->rate == CLOCK_33M)
 146                         ifccr |= 0xe00000;
 147                 else
 148                         ifccr |= 0x700000; /* 62.5M */
 149         } else {
 150                 ifccr &= ~0xf00000;
 151                 if (clk->rate == CLOCK_33M)
 152                         ifccr |= 0x800000;
 153                 else
 154                         ifccr |= 0x400000; /* 62.5M */
 155         }
 156         ltq_cgu_w32(ifccr, CGU_IFCCR);
 157         pmu_enable(clk);
 158         return 0;
 159 }
 160
 161 /* enable the external clock as a source */
 162 static int pci_ext_enable(struct clk *clk)
 163 {
 164         ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
 165                 CGU_IFCCR);
 166         ltq_cgu_w32((1 << 30), CGU_PCICR);
 167         return 0;
 168 }
 169
 170 /* disable the external clock as a source */
 171 static void pci_ext_disable(struct clk *clk)
 172 {
 173         ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
 174                 CGU_IFCCR);
 175         ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
 176 }
 177
 178 /* enable a clockout source */
 179 static int clkout_enable(struct clk *clk)
 180 {
 181         int i;
 182
 183         /* get the correct rate */
 184         for (i = 0; i < 4; i++) {
 185                 if (clk->rates[i] == clk->rate) {
 186                         int shift = 14 - (2 * clk->module);
 187                         unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
 188
 189                         ifccr &= ~(3 << shift);
 190                         ifccr |= i << shift;
 191                         ltq_cgu_w32(ifccr, CGU_IFCCR);
 192                         return 0;
 193                 }
 194         }
 195         return -1;
 196 }
 197
 198 /* manage the clock gates via PMU */
 199 static void clkdev_add_pmu(const char *dev, const char *con,
 200                                         unsigned int module, unsigned int bits)
 201 {
 202         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 203
 204         clk->cl.dev_id = dev;
 205         clk->cl.con_id = con;
 206         clk->cl.clk = clk;
 207         clk->enable = pmu_enable;
 208         clk->disable = pmu_disable;
 209         clk->module = module;
 210         clk->bits = bits;
 211         clkdev_add(&clk->cl);
 212 }
 213
 214 /* manage the clock generator */
 215 static void clkdev_add_cgu(const char *dev, const char *con,
 216                                         unsigned int bits)
 217 {
 218         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 219
 220         clk->cl.dev_id = dev;
 221         clk->cl.con_id = con;
 222         clk->cl.clk = clk;
 223         clk->enable = cgu_enable;
 224         clk->disable = cgu_disable;
 225         clk->bits = bits;
 226         clkdev_add(&clk->cl);
 227 }
 228
 229 /* pci needs its own enable function as the setup is a bit more complex */
 230 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
 231
 232 static void clkdev_add_pci(void)
 233 {
 234         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 235         struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
 236
 237         /* main pci clock */
 238         clk->cl.dev_id = "17000000.pci";
 239         clk->cl.con_id = NULL;
 240         clk->cl.clk = clk;
 241         clk->rate = CLOCK_33M;
 242         clk->rates = valid_pci_rates;
 243         clk->enable = pci_enable;
 244         clk->disable = pmu_disable;
 245         clk->module = 0;
 246         clk->bits = PMU_PCI;
 247         clkdev_add(&clk->cl);
 248
 249         /* use internal/external bus clock */
 250         clk_ext->cl.dev_id = "17000000.pci";
 251         clk_ext->cl.con_id = "external";
 252         clk_ext->cl.clk = clk_ext;
 253         clk_ext->enable = pci_ext_enable;
 254         clk_ext->disable = pci_ext_disable;
 255         clkdev_add(&clk_ext->cl);
 256 }
 257
 258 /* xway socs can generate clocks on gpio pins */
 259 static unsigned long valid_clkout_rates[4][5] = {
 260         {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
 261         {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
 262         {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
 263         {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
 264 };
 265
 266 static void clkdev_add_clkout(void)
 267 {
 268         int i;
 269
 270         for (i = 0; i < 4; i++) {
 271                 struct clk *clk;
 272                 char *name;
 273
 274                 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
 275                 sprintf(name, "clkout%d", i);
 276
 277                 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 278                 clk->cl.dev_id = "1f103000.cgu";
 279                 clk->cl.con_id = name;
 280                 clk->cl.clk = clk;
 281                 clk->rate = 0;
 282                 clk->rates = valid_clkout_rates[i];
 283                 clk->enable = clkout_enable;
 284                 clk->module = i;
 285                 clkdev_add(&clk->cl);
 286         }
 287 }
 288
 289 /* bring up all register ranges that we need for basic system control */
 290 void __init ltq_soc_init(void)
 291 {
 292         struct resource res_pmu, res_cgu, res_ebu;
 293         struct device_node *np_pmu =
 294                         of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
 295         struct device_node *np_cgu =
 296                         of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
 297         struct device_node *np_ebu =
 298                         of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
 299
 300         /* check if all the core register ranges are available */
 301         if (!np_pmu || !np_cgu || !np_ebu)
 302                 panic("Failed to load core nodess from devicetree");
 303
 304         if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
 305                         of_address_to_resource(np_cgu, 0, &res_cgu) ||
 306                         of_address_to_resource(np_ebu, 0, &res_ebu))
 307                 panic("Failed to get core resources");
 308
 309         if ((request_mem_region(res_pmu.start, resource_size(&res_pmu),
 310                                 res_pmu.name) < 0) ||
 311                 (request_mem_region(res_cgu.start, resource_size(&res_cgu),
 312                                 res_cgu.name) < 0) ||
 313                 (request_mem_region(res_ebu.start, resource_size(&res_ebu),
 314                                 res_ebu.name) < 0))
 315                 pr_err("Failed to request core reources");
 316
 317         pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
 318         ltq_cgu_membase = ioremap_nocache(res_cgu.start,
 319                                                 resource_size(&res_cgu));
 320         ltq_ebu_membase = ioremap_nocache(res_ebu.start,
 321                                                 resource_size(&res_ebu));
 322         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
 323                 panic("Failed to remap core resources");
 324
 325         /* make sure to unprotect the memory region where flash is located */
 326         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 327
 328         /* add our generic xway clocks */
 329         clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI);
 330         clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0);
 331         clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT);
 332         clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP);
 333         clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA);
 334         clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI);
 335         clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU);
 336         clkdev_add_clkout();
 337
 338         /* add the soc dependent clocks */
 339         if (!of_machine_is_compatible("lantiq,vr9"))
 340                 clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
 341
 342         if (!of_machine_is_compatible("lantiq,ase")) {
 343                 clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
 344                 clkdev_add_pci();
 345         }
 346
 347         if (of_machine_is_compatible("lantiq,ase")) {
 348                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 349                         clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
 350                 else
 351                         clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 352                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
 353                 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
 354         } else if (of_machine_is_compatible("lantiq,vr9")) {
 355                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 356                                 ltq_vr9_fpi_hz());
 357                 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
 358                 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
 359                 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
 360                 clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);
 361                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);
 362                 clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
 363         } else if (of_machine_is_compatible("lantiq,ar9")) {
 364                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 365                                 ltq_ar9_fpi_hz());
 366                 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
 367         } else {
 368                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 369                                 ltq_danube_fpi_hz());
 370         }
 371 }