arch/mips/lantiq/xway/sysctrl.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org>
   7  */
   8
   9 #include <linux/ioport.h>
  10 #include <linux/export.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/of.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/of_address.h>
  15
  16 #include <lantiq_soc.h>
  17
  18 #include "../clk.h"
  19 #include "../prom.h"
  20
  21 /* clock control register */
  22 #define CGU_IFCCR       0x0018
  23 #define CGU_IFCCR_VR9   0x0024
  24 /* system clock register */
  25 #define CGU_SYS         0x0010
  26 /* pci control register */
  27 #define CGU_PCICR       0x0034
  28 #define CGU_PCICR_VR9   0x0038
  29 /* ephy configuration register */
  30 #define CGU_EPHY        0x10
  31 /* power control register */
  32 #define PMU_PWDCR       0x1C
  33 /* power status register */
  34 #define PMU_PWDSR       0x20
  35 /* power control register */
  36 #define PMU_PWDCR1      0x24
  37 /* power status register */
  38 #define PMU_PWDSR1      0x28
  39 /* power control register */
  40 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
  41 /* power status register */
  42 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
  43
  44 /* clock gates that we can en/disable */
  45 #define PMU_USB0_P      BIT(0)
  46 #define PMU_PCI         BIT(4)
  47 #define PMU_DMA         BIT(5)
  48 #define PMU_USB0        BIT(6)
  49 #define PMU_ASC0        BIT(7)
  50 #define PMU_EPHY        BIT(7)  /* ase */
  51 #define PMU_SPI         BIT(8)
  52 #define PMU_DFE         BIT(9)
  53 #define PMU_EBU         BIT(10)
  54 #define PMU_STP         BIT(11)
  55 #define PMU_GPT         BIT(12)
  56 #define PMU_AHBS        BIT(13) /* vr9 */
  57 #define PMU_FPI         BIT(14)
  58 #define PMU_AHBM        BIT(15)
  59 #define PMU_ASC1        BIT(17)
  60 #define PMU_PPE_QSB     BIT(18)
  61 #define PMU_PPE_SLL01   BIT(19)
  62 #define PMU_PPE_TC      BIT(21)
  63 #define PMU_PPE_EMA     BIT(22)
  64 #define PMU_PPE_DPLUM   BIT(23)
  65 #define PMU_PPE_DPLUS   BIT(24)
  66 #define PMU_USB1_P      BIT(26)
  67 #define PMU_USB1        BIT(27)
  68 #define PMU_SWITCH      BIT(28)
  69 #define PMU_PPE_TOP     BIT(29)
  70 #define PMU_GPHY        BIT(30)
  71 #define PMU_PCIE_CLK    BIT(31)
  72
  73 #define PMU1_PCIE_PHY   BIT(0)
  74 #define PMU1_PCIE_CTL   BIT(1)
  75 #define PMU1_PCIE_PDI   BIT(4)
  76 #define PMU1_PCIE_MSI   BIT(5)
  77
  78 #define pmu_w32(x, y)   ltq_w32((x), pmu_membase + (y))
  79 #define pmu_r32(x)      ltq_r32(pmu_membase + (x))
  80
  81 static void __iomem *pmu_membase;
  82 void __iomem *ltq_cgu_membase;
  83 void __iomem *ltq_ebu_membase;
  84
  85 static u32 ifccr = CGU_IFCCR;
  86 static u32 pcicr = CGU_PCICR;
  87
  88 /* legacy function kept alive to ease clkdev transition */
  89 void ltq_pmu_enable(unsigned int module)
  90 {
  91         int err = 1000000;
  92
  93         pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
  94         do {} while (--err && (pmu_r32(PMU_PWDSR) & module));
  95
  96         if (!err)
  97                 panic("activating PMU module failed!");
  98 }
  99 EXPORT_SYMBOL(ltq_pmu_enable);
 100
 101 /* legacy function kept alive to ease clkdev transition */
 102 void ltq_pmu_disable(unsigned int module)
 103 {
 104         pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
 105 }
 106 EXPORT_SYMBOL(ltq_pmu_disable);
 107
 108 /* enable a hw clock */
 109 static int cgu_enable(struct clk *clk)
 110 {
 111         ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
 112         return 0;
 113 }
 114
 115 /* disable a hw clock */
 116 static void cgu_disable(struct clk *clk)
 117 {
 118         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
 119 }
 120
 121 /* enable a clock gate */
 122 static int pmu_enable(struct clk *clk)
 123 {
 124         int retry = 1000000;
 125
 126         pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
 127                 PWDCR(clk->module));
 128         do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits));
 129
 130         if (!retry)
 131                 panic("activating PMU module failed!\n");
 132
 133         return 0;
 134 }
 135
 136 /* disable a clock gate */
 137 static void pmu_disable(struct clk *clk)
 138 {
 139         pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
 140                 PWDCR(clk->module));
 141 }
 142
 143 /* the pci enable helper */
 144 static int pci_enable(struct clk *clk)
 145 {
 146         unsigned int val = ltq_cgu_r32(ifccr);
 147         /* set bus clock speed */
 148         if (of_machine_is_compatible("lantiq,ar9")) {
 149                 val &= ~0x1f00000;
 150                 if (clk->rate == CLOCK_33M)
 151                         val |= 0xe00000;
 152                 else
 153                         val |= 0x700000; /* 62.5M */
 154         } else {
 155                 val &= ~0xf00000;
 156                 if (clk->rate == CLOCK_33M)
 157                         val |= 0x800000;
 158                 else
 159                         val |= 0x400000; /* 62.5M */
 160         }
 161         ltq_cgu_w32(val, ifccr);
 162         pmu_enable(clk);
 163         return 0;
 164 }
 165
 166 /* enable the external clock as a source */
 167 static int pci_ext_enable(struct clk *clk)
 168 {
 169         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
 170         ltq_cgu_w32((1 << 30), pcicr);
 171         return 0;
 172 }
 173
 174 /* disable the external clock as a source */
 175 static void pci_ext_disable(struct clk *clk)
 176 {
 177         ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
 178         ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 179 }
 180
 181 /* enable a clockout source */
 182 static int clkout_enable(struct clk *clk)
 183 {
 184         int i;
 185
 186         /* get the correct rate */
 187         for (i = 0; i < 4; i++) {
 188                 if (clk->rates[i] == clk->rate) {
 189                         int shift = 14 - (2 * clk->module);
 190                         unsigned int val = ltq_cgu_r32(ifccr);
 191
 192                         val &= ~(3 << shift);
 193                         val |= i << shift;
 194                         ltq_cgu_w32(val, ifccr);
 195                         return 0;
 196                 }
 197         }
 198         return -1;
 199 }
 200
 201 /* manage the clock gates via PMU */
 202 static void clkdev_add_pmu(const char *dev, const char *con,
 203                                         unsigned int module, unsigned int bits)
 204 {
 205         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 206
 207         clk->cl.dev_id = dev;
 208         clk->cl.con_id = con;
 209         clk->cl.clk = clk;
 210         clk->enable = pmu_enable;
 211         clk->disable = pmu_disable;
 212         clk->module = module;
 213         clk->bits = bits;
 214         clkdev_add(&clk->cl);
 215 }
 216
 217 /* manage the clock generator */
 218 static void clkdev_add_cgu(const char *dev, const char *con,
 219                                         unsigned int bits)
 220 {
 221         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 222
 223         clk->cl.dev_id = dev;
 224         clk->cl.con_id = con;
 225         clk->cl.clk = clk;
 226         clk->enable = cgu_enable;
 227         clk->disable = cgu_disable;
 228         clk->bits = bits;
 229         clkdev_add(&clk->cl);
 230 }
 231
 232 /* pci needs its own enable function as the setup is a bit more complex */
 233 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
 234
 235 static void clkdev_add_pci(void)
 236 {
 237         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 238         struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
 239
 240         /* main pci clock */
 241         clk->cl.dev_id = "17000000.pci";
 242         clk->cl.con_id = NULL;
 243         clk->cl.clk = clk;
 244         clk->rate = CLOCK_33M;
 245         clk->rates = valid_pci_rates;
 246         clk->enable = pci_enable;
 247         clk->disable = pmu_disable;
 248         clk->module = 0;
 249         clk->bits = PMU_PCI;
 250         clkdev_add(&clk->cl);
 251
 252         /* use internal/external bus clock */
 253         clk_ext->cl.dev_id = "17000000.pci";
 254         clk_ext->cl.con_id = "external";
 255         clk_ext->cl.clk = clk_ext;
 256         clk_ext->enable = pci_ext_enable;
 257         clk_ext->disable = pci_ext_disable;
 258         clkdev_add(&clk_ext->cl);
 259 }
 260
 261 /* xway socs can generate clocks on gpio pins */
 262 static unsigned long valid_clkout_rates[4][5] = {
 263         {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
 264         {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
 265         {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
 266         {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
 267 };
 268
 269 static void clkdev_add_clkout(void)
 270 {
 271         int i;
 272
 273         for (i = 0; i < 4; i++) {
 274                 struct clk *clk;
 275                 char *name;
 276
 277                 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
 278                 sprintf(name, "clkout%d", i);
 279
 280                 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 281                 clk->cl.dev_id = "1f103000.cgu";
 282                 clk->cl.con_id = name;
 283                 clk->cl.clk = clk;
 284                 clk->rate = 0;
 285                 clk->rates = valid_clkout_rates[i];
 286                 clk->enable = clkout_enable;
 287                 clk->module = i;
 288                 clkdev_add(&clk->cl);
 289         }
 290 }
 291
 292 /* bring up all register ranges that we need for basic system control */
 293 void __init ltq_soc_init(void)
 294 {
 295         struct resource res_pmu, res_cgu, res_ebu;
 296         struct device_node *np_pmu =
 297                         of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
 298         struct device_node *np_cgu =
 299                         of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
 300         struct device_node *np_ebu =
 301                         of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
 302
 303         /* check if all the core register ranges are available */
 304         if (!np_pmu || !np_cgu || !np_ebu)
 305                 panic("Failed to load core nodess from devicetree");
 306
 307         if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
 308                         of_address_to_resource(np_cgu, 0, &res_cgu) ||
 309                         of_address_to_resource(np_ebu, 0, &res_ebu))
 310                 panic("Failed to get core resources");
 311
 312         if ((request_mem_region(res_pmu.start, resource_size(&res_pmu),
 313                                 res_pmu.name) < 0) ||
 314                 (request_mem_region(res_cgu.start, resource_size(&res_cgu),
 315                                 res_cgu.name) < 0) ||
 316                 (request_mem_region(res_ebu.start, resource_size(&res_ebu),
 317                                 res_ebu.name) < 0))
 318                 pr_err("Failed to request core reources");
 319
 320         pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
 321         ltq_cgu_membase = ioremap_nocache(res_cgu.start,
 322                                                 resource_size(&res_cgu));
 323         ltq_ebu_membase = ioremap_nocache(res_ebu.start,
 324                                                 resource_size(&res_ebu));
 325         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
 326                 panic("Failed to remap core resources");
 327
 328         /* make sure to unprotect the memory region where flash is located */
 329         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 330
 331         /* add our generic xway clocks */
 332         clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI);
 333         clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0);
 334         clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT);
 335         clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP);
 336         clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA);
 337         clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI);
 338         clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU);
 339         clkdev_add_clkout();
 340
 341         /* add the soc dependent clocks */
 342         if (of_machine_is_compatible("lantiq,vr9")) {
 343                 ifccr = CGU_IFCCR_VR9;
 344                 pcicr = CGU_PCICR_VR9;
 345         } else {
 346                 clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
 347         }
 348
 349         if (!of_machine_is_compatible("lantiq,ase")) {
 350                 clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
 351                 clkdev_add_pci();
 352         }
 353
 354         if (of_machine_is_compatible("lantiq,ase")) {
 355                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 356                         clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
 357                 else
 358                         clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 359                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
 360                 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
 361         } else if (of_machine_is_compatible("lantiq,vr9")) {
 362                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 363                                 ltq_vr9_fpi_hz());
 364                 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
 365                 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
 366                 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
 367                 clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);
 368                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);
 369                 clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
 370         } else if (of_machine_is_compatible("lantiq,ar9")) {
 371                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 372                                 ltq_ar9_fpi_hz());
 373                 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
 374         } else {
 375                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 376                                 ltq_danube_fpi_hz());
 377         }
 378 }