MIPS: bugfix: missed cache flush of TLB refill handler
[cascardo/linux.git] / arch / mips / loongson / loongson-3 / Makefile
1 #
2 # Makefile for Loongson-3 family machines
3 #
4 obj-y                   += irq.o
5
6 obj-$(CONFIG_SMP)       += smp.o