2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
54 /* Function which emulates a floating point instruction. */
56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 static int fpux_emu(struct pt_regs *,
60 struct mips_fpu_struct *, mips_instruction, void *__user *);
62 /* Control registers */
64 #define FPCREG_RID 0 /* $0 = revision id */
65 #define FPCREG_CSR 31 /* $31 = csr */
67 /* Determine rounding mode from the RM bits of the FCSR */
68 #define modeindex(v) ((v) & FPU_CSR_RM)
70 /* convert condition code register number to csr bit */
71 static const unsigned int fpucondbit[8] = {
82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89 * This functions translates a 32-bit microMIPS instruction
90 * into a 32-bit MIPS32 instruction. Returns 0 on success
91 * and SIGILL otherwise.
93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
95 union mips_instruction insn = *insn_ptr;
96 union mips_instruction mips32_insn = insn;
99 switch (insn.mm_i_format.opcode) {
101 mips32_insn.mm_i_format.opcode = ldc1_op;
102 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
103 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 mips32_insn.mm_i_format.opcode = lwc1_op;
107 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
108 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 mips32_insn.mm_i_format.opcode = sdc1_op;
112 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
113 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 mips32_insn.mm_i_format.opcode = swc1_op;
117 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
118 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 /* NOTE: offset is << by 1 if in microMIPS mode. */
122 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
123 (insn.mm_i_format.rt == mm_bc1t_op)) {
124 mips32_insn.fb_format.opcode = cop1_op;
125 mips32_insn.fb_format.bc = bc_op;
126 mips32_insn.fb_format.flag =
127 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
132 switch (insn.mm_fp0_format.func) {
141 op = insn.mm_fp0_format.func;
142 if (op == mm_32f_01_op)
144 else if (op == mm_32f_11_op)
146 else if (op == mm_32f_02_op)
148 else if (op == mm_32f_12_op)
150 else if (op == mm_32f_41_op)
152 else if (op == mm_32f_51_op)
154 else if (op == mm_32f_42_op)
158 mips32_insn.fp6_format.opcode = cop1x_op;
159 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
160 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
161 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
162 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
163 mips32_insn.fp6_format.func = func;
166 func = -1; /* Invalid */
167 op = insn.mm_fp5_format.op & 0x7;
168 if (op == mm_ldxc1_op)
170 else if (op == mm_sdxc1_op)
172 else if (op == mm_lwxc1_op)
174 else if (op == mm_swxc1_op)
178 mips32_insn.r_format.opcode = cop1x_op;
179 mips32_insn.r_format.rs =
180 insn.mm_fp5_format.base;
181 mips32_insn.r_format.rt =
182 insn.mm_fp5_format.index;
183 mips32_insn.r_format.rd = 0;
184 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
185 mips32_insn.r_format.func = func;
190 op = -1; /* Invalid */
191 if (insn.mm_fp2_format.op == mm_fmovt_op)
193 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 mips32_insn.fp0_format.opcode = cop1_op;
197 mips32_insn.fp0_format.fmt =
198 sdps_format[insn.mm_fp2_format.fmt];
199 mips32_insn.fp0_format.ft =
200 (insn.mm_fp2_format.cc<<2) + op;
201 mips32_insn.fp0_format.fs =
202 insn.mm_fp2_format.fs;
203 mips32_insn.fp0_format.fd =
204 insn.mm_fp2_format.fd;
205 mips32_insn.fp0_format.func = fmovc_op;
210 func = -1; /* Invalid */
211 if (insn.mm_fp0_format.op == mm_fadd_op)
213 else if (insn.mm_fp0_format.op == mm_fsub_op)
215 else if (insn.mm_fp0_format.op == mm_fmul_op)
217 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 mips32_insn.fp0_format.opcode = cop1_op;
221 mips32_insn.fp0_format.fmt =
222 sdps_format[insn.mm_fp0_format.fmt];
223 mips32_insn.fp0_format.ft =
224 insn.mm_fp0_format.ft;
225 mips32_insn.fp0_format.fs =
226 insn.mm_fp0_format.fs;
227 mips32_insn.fp0_format.fd =
228 insn.mm_fp0_format.fd;
229 mips32_insn.fp0_format.func = func;
234 func = -1; /* Invalid */
235 if (insn.mm_fp0_format.op == mm_fmovn_op)
237 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 mips32_insn.fp0_format.opcode = cop1_op;
241 mips32_insn.fp0_format.fmt =
242 sdps_format[insn.mm_fp0_format.fmt];
243 mips32_insn.fp0_format.ft =
244 insn.mm_fp0_format.ft;
245 mips32_insn.fp0_format.fs =
246 insn.mm_fp0_format.fs;
247 mips32_insn.fp0_format.fd =
248 insn.mm_fp0_format.fd;
249 mips32_insn.fp0_format.func = func;
253 case mm_32f_73_op: /* POOL32FXF */
254 switch (insn.mm_fp1_format.op) {
259 if ((insn.mm_fp1_format.op & 0x7f) ==
264 mips32_insn.r_format.opcode = spec_op;
265 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
266 mips32_insn.r_format.rt =
267 (insn.mm_fp4_format.cc << 2) + op;
268 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
269 mips32_insn.r_format.re = 0;
270 mips32_insn.r_format.func = movc_op;
276 if ((insn.mm_fp1_format.op & 0x7f) ==
279 fmt = swl_format[insn.mm_fp3_format.fmt];
282 fmt = dwl_format[insn.mm_fp3_format.fmt];
284 mips32_insn.fp0_format.opcode = cop1_op;
285 mips32_insn.fp0_format.fmt = fmt;
286 mips32_insn.fp0_format.ft = 0;
287 mips32_insn.fp0_format.fs =
288 insn.mm_fp3_format.fs;
289 mips32_insn.fp0_format.fd =
290 insn.mm_fp3_format.rt;
291 mips32_insn.fp0_format.func = func;
299 if ((insn.mm_fp1_format.op & 0x7f) ==
302 else if ((insn.mm_fp1_format.op & 0x7f) ==
307 mips32_insn.fp0_format.opcode = cop1_op;
308 mips32_insn.fp0_format.fmt =
309 sdps_format[insn.mm_fp3_format.fmt];
310 mips32_insn.fp0_format.ft = 0;
311 mips32_insn.fp0_format.fs =
312 insn.mm_fp3_format.fs;
313 mips32_insn.fp0_format.fd =
314 insn.mm_fp3_format.rt;
315 mips32_insn.fp0_format.func = func;
327 if (insn.mm_fp1_format.op == mm_ffloorl_op)
329 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
331 else if (insn.mm_fp1_format.op == mm_fceill_op)
333 else if (insn.mm_fp1_format.op == mm_fceilw_op)
335 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
337 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
339 else if (insn.mm_fp1_format.op == mm_froundl_op)
341 else if (insn.mm_fp1_format.op == mm_froundw_op)
343 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sd_format[insn.mm_fp1_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp1_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp1_format.rt;
355 mips32_insn.fp0_format.func = func;
360 if (insn.mm_fp1_format.op == mm_frsqrt_op)
362 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
366 mips32_insn.fp0_format.opcode = cop1_op;
367 mips32_insn.fp0_format.fmt =
368 sdps_format[insn.mm_fp1_format.fmt];
369 mips32_insn.fp0_format.ft = 0;
370 mips32_insn.fp0_format.fs =
371 insn.mm_fp1_format.fs;
372 mips32_insn.fp0_format.fd =
373 insn.mm_fp1_format.rt;
374 mips32_insn.fp0_format.func = func;
382 if (insn.mm_fp1_format.op == mm_mfc1_op)
384 else if (insn.mm_fp1_format.op == mm_mtc1_op)
386 else if (insn.mm_fp1_format.op == mm_cfc1_op)
388 else if (insn.mm_fp1_format.op == mm_ctc1_op)
390 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
394 mips32_insn.fp1_format.opcode = cop1_op;
395 mips32_insn.fp1_format.op = op;
396 mips32_insn.fp1_format.rt =
397 insn.mm_fp1_format.rt;
398 mips32_insn.fp1_format.fs =
399 insn.mm_fp1_format.fs;
400 mips32_insn.fp1_format.fd = 0;
401 mips32_insn.fp1_format.func = 0;
407 case mm_32f_74_op: /* c.cond.fmt */
408 mips32_insn.fp0_format.opcode = cop1_op;
409 mips32_insn.fp0_format.fmt =
410 sdps_format[insn.mm_fp4_format.fmt];
411 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
412 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
413 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
414 mips32_insn.fp0_format.func =
415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
425 *insn_ptr = mips32_insn;
430 * Redundant with logic already in kernel/branch.c,
431 * embedded in compute_return_epc. At some point,
432 * a single subroutine should be used across both
435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
436 unsigned long *contpc)
438 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
440 unsigned int bit = 0;
442 switch (insn.i_format.opcode) {
444 switch (insn.r_format.func) {
446 regs->regs[insn.r_format.rd] =
447 regs->cp0_epc + dec_insn.pc_inc +
448 dec_insn.next_pc_inc;
451 *contpc = regs->regs[insn.r_format.rs];
456 switch (insn.i_format.rt) {
459 regs->regs[31] = regs->cp0_epc +
461 dec_insn.next_pc_inc;
465 if ((long)regs->regs[insn.i_format.rs] < 0)
466 *contpc = regs->cp0_epc +
468 (insn.i_format.simmediate << 2);
470 *contpc = regs->cp0_epc +
472 dec_insn.next_pc_inc;
476 regs->regs[31] = regs->cp0_epc +
478 dec_insn.next_pc_inc;
482 if ((long)regs->regs[insn.i_format.rs] >= 0)
483 *contpc = regs->cp0_epc +
485 (insn.i_format.simmediate << 2);
487 *contpc = regs->cp0_epc +
489 dec_insn.next_pc_inc;
496 regs->regs[31] = regs->cp0_epc +
498 dec_insn.next_pc_inc;
501 *contpc = regs->cp0_epc + dec_insn.pc_inc;
504 *contpc |= (insn.j_format.target << 2);
505 /* Set microMIPS mode bit: XOR for jalx. */
510 if (regs->regs[insn.i_format.rs] ==
511 regs->regs[insn.i_format.rt])
512 *contpc = regs->cp0_epc +
514 (insn.i_format.simmediate << 2);
516 *contpc = regs->cp0_epc +
518 dec_insn.next_pc_inc;
522 if (regs->regs[insn.i_format.rs] !=
523 regs->regs[insn.i_format.rt])
524 *contpc = regs->cp0_epc +
526 (insn.i_format.simmediate << 2);
528 *contpc = regs->cp0_epc +
530 dec_insn.next_pc_inc;
534 if ((long)regs->regs[insn.i_format.rs] <= 0)
535 *contpc = regs->cp0_epc +
537 (insn.i_format.simmediate << 2);
539 *contpc = regs->cp0_epc +
541 dec_insn.next_pc_inc;
545 if ((long)regs->regs[insn.i_format.rs] > 0)
546 *contpc = regs->cp0_epc +
548 (insn.i_format.simmediate << 2);
550 *contpc = regs->cp0_epc +
552 dec_insn.next_pc_inc;
554 #ifdef CONFIG_CPU_CAVIUM_OCTEON
555 case lwc2_op: /* This is bbit0 on Octeon */
556 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
557 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
559 *contpc = regs->cp0_epc + 8;
561 case ldc2_op: /* This is bbit032 on Octeon */
562 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
563 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
565 *contpc = regs->cp0_epc + 8;
567 case swc2_op: /* This is bbit1 on Octeon */
568 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
569 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
571 *contpc = regs->cp0_epc + 8;
573 case sdc2_op: /* This is bbit132 on Octeon */
574 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
575 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
577 *contpc = regs->cp0_epc + 8;
584 if (insn.i_format.rs == bc_op) {
587 fcr31 = read_32bit_cp1_register(CP1_STATUS);
589 fcr31 = current->thread.fpu.fcr31;
592 bit = (insn.i_format.rt >> 2);
595 switch (insn.i_format.rt & 3) {
598 if (~fcr31 & (1 << bit))
599 *contpc = regs->cp0_epc +
601 (insn.i_format.simmediate << 2);
603 *contpc = regs->cp0_epc +
605 dec_insn.next_pc_inc;
609 if (fcr31 & (1 << bit))
610 *contpc = regs->cp0_epc +
612 (insn.i_format.simmediate << 2);
614 *contpc = regs->cp0_epc +
616 dec_insn.next_pc_inc;
626 * In the Linux kernel, we support selection of FPR format on the
627 * basis of the Status.FR bit. If an FPU is not present, the FR bit
628 * is hardwired to zero, which would imply a 32-bit FPU even for
629 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
630 * FPU emu is slow and bulky and optimizing this function offers fairly
631 * sizeable benefits so we try to be clever and make this function return
632 * a constant whenever possible, that is on 64-bit kernels without O32
633 * compatibility enabled and on 32-bit without 64-bit FPU support.
635 static inline int cop1_64bit(struct pt_regs *xcp)
637 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
639 else if (config_enabled(CONFIG_32BIT) &&
640 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
643 return !test_thread_flag(TIF_32BIT_FPREGS);
646 #define SIFROMREG(si, x) \
648 if (cop1_64bit(xcp)) \
649 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
651 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
654 #define SITOREG(si, x) \
656 if (cop1_64bit(xcp)) { \
658 set_fpr32(&ctx->fpr[x], 0, si); \
659 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
660 set_fpr32(&ctx->fpr[x], i, 0); \
662 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
666 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
668 #define SITOHREG(si, x) \
671 set_fpr32(&ctx->fpr[x], 1, si); \
672 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
673 set_fpr32(&ctx->fpr[x], i, 0); \
676 #define DIFROMREG(di, x) \
677 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
679 #define DITOREG(di, x) \
682 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
683 set_fpr64(&ctx->fpr[fpr], 0, di); \
684 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
685 set_fpr64(&ctx->fpr[fpr], i, 0); \
688 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
689 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
690 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
691 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
694 * Emulate the single floating point instruction pointed at by EPC.
695 * Two instructions if the instruction is in a branch delay slot.
698 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
699 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
701 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
702 unsigned int cond, cbit;
713 * These are giving gcc a gentle hint about what to expect in
714 * dec_inst in order to do better optimization.
716 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
719 /* XXX NEC Vr54xx bug workaround */
720 if (delay_slot(xcp)) {
721 if (dec_insn.micro_mips_mode) {
722 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
723 clear_delay_slot(xcp);
725 if (!isBranchInstr(xcp, dec_insn, &contpc))
726 clear_delay_slot(xcp);
730 if (delay_slot(xcp)) {
732 * The instruction to be emulated is in a branch delay slot
733 * which means that we have to emulate the branch instruction
734 * BEFORE we do the cop1 instruction.
736 * This branch could be a COP1 branch, but in that case we
737 * would have had a trap for that instruction, and would not
738 * come through this route.
740 * Linux MIPS branch emulator operates on context, updating the
743 ir = dec_insn.next_insn; /* process delay slot instr */
744 pc_inc = dec_insn.next_pc_inc;
746 ir = dec_insn.insn; /* process current instr */
747 pc_inc = dec_insn.pc_inc;
751 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
752 * instructions, we want to convert microMIPS FPU instructions
753 * into MIPS32 instructions so that we could reuse all of the
754 * FPU emulation code.
756 * NOTE: We cannot do this for branch instructions since they
757 * are not a subset. Example: Cannot emulate a 16-bit
758 * aligned target address with a MIPS32 instruction.
760 if (dec_insn.micro_mips_mode) {
762 * If next instruction is a 16-bit instruction, then it
763 * it cannot be a FPU instruction. This could happen
764 * since we can be called for non-FPU instructions.
767 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
773 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
774 MIPS_FPU_EMU_INC_STATS(emulated);
775 switch (MIPSInst_OPCODE(ir)) {
777 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
779 MIPS_FPU_EMU_INC_STATS(loads);
781 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
782 MIPS_FPU_EMU_INC_STATS(errors);
786 if (__get_user(dval, dva)) {
787 MIPS_FPU_EMU_INC_STATS(errors);
791 DITOREG(dval, MIPSInst_RT(ir));
795 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
797 MIPS_FPU_EMU_INC_STATS(stores);
798 DIFROMREG(dval, MIPSInst_RT(ir));
799 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
800 MIPS_FPU_EMU_INC_STATS(errors);
804 if (__put_user(dval, dva)) {
805 MIPS_FPU_EMU_INC_STATS(errors);
812 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
814 MIPS_FPU_EMU_INC_STATS(loads);
815 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
816 MIPS_FPU_EMU_INC_STATS(errors);
820 if (__get_user(wval, wva)) {
821 MIPS_FPU_EMU_INC_STATS(errors);
825 SITOREG(wval, MIPSInst_RT(ir));
829 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
831 MIPS_FPU_EMU_INC_STATS(stores);
832 SIFROMREG(wval, MIPSInst_RT(ir));
833 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
834 MIPS_FPU_EMU_INC_STATS(errors);
838 if (__put_user(wval, wva)) {
839 MIPS_FPU_EMU_INC_STATS(errors);
846 switch (MIPSInst_RS(ir)) {
848 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
851 /* copregister fs -> gpr[rt] */
852 if (MIPSInst_RT(ir) != 0) {
853 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
859 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
862 /* copregister fs <- rt */
863 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
867 if (!cpu_has_mips_r2)
870 /* copregister rd -> gpr[rt] */
871 if (MIPSInst_RT(ir) != 0) {
872 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
878 if (!cpu_has_mips_r2)
881 /* copregister rd <- gpr[rt] */
882 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
886 /* copregister rd -> gpr[rt] */
887 if (MIPSInst_RT(ir) != 0) {
888 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
894 /* copregister rd <- rt */
895 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
899 /* cop control register rd -> gpr[rt] */
900 if (MIPSInst_RD(ir) == FPCREG_CSR) {
902 value = (value & ~FPU_CSR_RM) | modeindex(value);
903 pr_debug("%p gpr[%d]<-csr=%08x\n",
904 (void *) (xcp->cp0_epc),
905 MIPSInst_RT(ir), value);
907 else if (MIPSInst_RD(ir) == FPCREG_RID)
912 xcp->regs[MIPSInst_RT(ir)] = value;
916 /* copregister rd <- rt */
917 if (MIPSInst_RT(ir) == 0)
920 value = xcp->regs[MIPSInst_RT(ir)];
922 /* we only have one writable control reg
924 if (MIPSInst_RD(ir) == FPCREG_CSR) {
925 pr_debug("%p gpr[%d]->csr=%08x\n",
926 (void *) (xcp->cp0_epc),
927 MIPSInst_RT(ir), value);
930 * Don't write reserved bits,
931 * and convert to ieee library modes
933 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
936 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
945 if (cpu_has_mips_4_5_r)
946 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
949 cond = ctx->fcr31 & cbit;
952 switch (MIPSInst_RT(ir) & 3) {
963 /* thats an illegal instruction */
970 * Branch taken: emulate dslot instruction
972 xcp->cp0_epc += dec_insn.pc_inc;
974 contpc = MIPSInst_SIMM(ir);
975 ir = dec_insn.next_insn;
976 if (dec_insn.micro_mips_mode) {
977 contpc = (xcp->cp0_epc + (contpc << 1));
979 /* If 16-bit instruction, not FPU. */
980 if ((dec_insn.next_pc_inc == 2) ||
981 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
984 * Since this instruction will
985 * be put on the stack with
986 * 32-bit words, get around
987 * this problem by putting a
988 * NOP16 as the second one.
990 if (dec_insn.next_pc_inc == 2)
991 ir = (ir & (~0xffff)) | MM_NOP16;
994 * Single step the non-CP1
995 * instruction in the dslot.
997 return mips_dsemul(xcp, ir, contpc);
1000 contpc = (xcp->cp0_epc + (contpc << 2));
1002 switch (MIPSInst_OPCODE(ir)) {
1011 if (cpu_has_mips_2_3_4_5 ||
1022 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1023 /* its one of ours */
1029 if (!cpu_has_mips_4_5_r)
1032 if (MIPSInst_FUNC(ir) == movc_op)
1038 * Single step the non-cp1
1039 * instruction in the dslot
1041 return mips_dsemul(xcp, ir, contpc);
1042 } else if (likely) { /* branch not taken */
1044 * branch likely nullifies
1045 * dslot if not taken
1047 xcp->cp0_epc += dec_insn.pc_inc;
1048 contpc += dec_insn.pc_inc;
1050 * else continue & execute
1051 * dslot as normal insn
1057 if (!(MIPSInst_RS(ir) & 0x10))
1060 /* a real fpu computation instruction */
1061 if ((sig = fpu_emu(xcp, ctx, ir)))
1067 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1070 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1076 if (!cpu_has_mips_4_5_r)
1079 if (MIPSInst_FUNC(ir) != movc_op)
1081 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1082 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1083 xcp->regs[MIPSInst_RD(ir)] =
1084 xcp->regs[MIPSInst_RS(ir)];
1092 xcp->cp0_epc = contpc;
1093 clear_delay_slot(xcp);
1099 * Conversion table from MIPS compare ops 48-63
1100 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1102 static const unsigned char cmptab[8] = {
1103 0, /* cmp_0 (sig) cmp_sf */
1104 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1105 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1106 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1107 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1108 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1109 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1110 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1115 * Additional MIPS4 instructions
1118 #define DEF3OP(name, p, f1, f2, f3) \
1119 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1120 union ieee754##p s, union ieee754##p t) \
1122 struct _ieee754_csr ieee754_csr_save; \
1124 ieee754_csr_save = ieee754_csr; \
1126 ieee754_csr_save.cx |= ieee754_csr.cx; \
1127 ieee754_csr_save.sx |= ieee754_csr.sx; \
1129 ieee754_csr.cx |= ieee754_csr_save.cx; \
1130 ieee754_csr.sx |= ieee754_csr_save.sx; \
1134 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1136 return ieee754dp_div(ieee754dp_one(0), d);
1139 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1141 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1144 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1146 return ieee754sp_div(ieee754sp_one(0), s);
1149 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1151 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1154 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1155 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1156 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1157 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1158 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1159 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1160 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1161 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1163 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1164 mips_instruction ir, void *__user *fault_addr)
1166 unsigned rcsr = 0; /* resulting csr */
1168 MIPS_FPU_EMU_INC_STATS(cp1xops);
1170 switch (MIPSInst_FMA_FFMT(ir)) {
1171 case s_fmt:{ /* 0 */
1173 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1174 union ieee754sp fd, fr, fs, ft;
1178 switch (MIPSInst_FUNC(ir)) {
1180 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1181 xcp->regs[MIPSInst_FT(ir)]);
1183 MIPS_FPU_EMU_INC_STATS(loads);
1184 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1185 MIPS_FPU_EMU_INC_STATS(errors);
1189 if (__get_user(val, va)) {
1190 MIPS_FPU_EMU_INC_STATS(errors);
1194 SITOREG(val, MIPSInst_FD(ir));
1198 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1199 xcp->regs[MIPSInst_FT(ir)]);
1201 MIPS_FPU_EMU_INC_STATS(stores);
1203 SIFROMREG(val, MIPSInst_FS(ir));
1204 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1205 MIPS_FPU_EMU_INC_STATS(errors);
1209 if (put_user(val, va)) {
1210 MIPS_FPU_EMU_INC_STATS(errors);
1217 handler = fpemu_sp_madd;
1220 handler = fpemu_sp_msub;
1223 handler = fpemu_sp_nmadd;
1226 handler = fpemu_sp_nmsub;
1230 SPFROMREG(fr, MIPSInst_FR(ir));
1231 SPFROMREG(fs, MIPSInst_FS(ir));
1232 SPFROMREG(ft, MIPSInst_FT(ir));
1233 fd = (*handler) (fr, fs, ft);
1234 SPTOREG(fd, MIPSInst_FD(ir));
1237 if (ieee754_cxtest(IEEE754_INEXACT)) {
1238 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1239 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1241 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1242 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1243 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1245 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1246 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1247 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1249 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1250 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1251 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1254 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1255 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1256 /*printk ("SIGFPE: FPU csr = %08x\n",
1269 case d_fmt:{ /* 1 */
1270 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1271 union ieee754dp fd, fr, fs, ft;
1275 switch (MIPSInst_FUNC(ir)) {
1277 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1278 xcp->regs[MIPSInst_FT(ir)]);
1280 MIPS_FPU_EMU_INC_STATS(loads);
1281 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1282 MIPS_FPU_EMU_INC_STATS(errors);
1286 if (__get_user(val, va)) {
1287 MIPS_FPU_EMU_INC_STATS(errors);
1291 DITOREG(val, MIPSInst_FD(ir));
1295 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1296 xcp->regs[MIPSInst_FT(ir)]);
1298 MIPS_FPU_EMU_INC_STATS(stores);
1299 DIFROMREG(val, MIPSInst_FS(ir));
1300 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1301 MIPS_FPU_EMU_INC_STATS(errors);
1305 if (__put_user(val, va)) {
1306 MIPS_FPU_EMU_INC_STATS(errors);
1313 handler = fpemu_dp_madd;
1316 handler = fpemu_dp_msub;
1319 handler = fpemu_dp_nmadd;
1322 handler = fpemu_dp_nmsub;
1326 DPFROMREG(fr, MIPSInst_FR(ir));
1327 DPFROMREG(fs, MIPSInst_FS(ir));
1328 DPFROMREG(ft, MIPSInst_FT(ir));
1329 fd = (*handler) (fr, fs, ft);
1330 DPTOREG(fd, MIPSInst_FD(ir));
1340 if (MIPSInst_FUNC(ir) != pfetch_op)
1343 /* ignore prefx operation */
1356 * Emulate a single COP1 arithmetic instruction.
1358 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1359 mips_instruction ir)
1361 int rfmt; /* resulting format */
1362 unsigned rcsr = 0; /* resulting csr */
1371 } rv; /* resulting value */
1374 MIPS_FPU_EMU_INC_STATS(cp1ops);
1375 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1376 case s_fmt: { /* 0 */
1378 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1379 union ieee754sp(*u) (union ieee754sp);
1381 union ieee754sp fs, ft;
1383 switch (MIPSInst_FUNC(ir)) {
1386 handler.b = ieee754sp_add;
1389 handler.b = ieee754sp_sub;
1392 handler.b = ieee754sp_mul;
1395 handler.b = ieee754sp_div;
1400 if (!cpu_has_mips_4_5_r)
1403 handler.u = ieee754sp_sqrt;
1407 * Note that on some MIPS IV implementations such as the
1408 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1409 * achieve full IEEE-754 accuracy - however this emulator does.
1412 if (!cpu_has_mips_4_5_r2)
1415 handler.u = fpemu_sp_rsqrt;
1419 if (!cpu_has_mips_4_5_r2)
1422 handler.u = fpemu_sp_recip;
1426 if (!cpu_has_mips_4_5_r)
1429 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1430 if (((ctx->fcr31 & cond) != 0) !=
1431 ((MIPSInst_FT(ir) & 1) != 0))
1433 SPFROMREG(rv.s, MIPSInst_FS(ir));
1437 if (!cpu_has_mips_4_5_r)
1440 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1442 SPFROMREG(rv.s, MIPSInst_FS(ir));
1446 if (!cpu_has_mips_4_5_r)
1449 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1451 SPFROMREG(rv.s, MIPSInst_FS(ir));
1455 handler.u = ieee754sp_abs;
1459 handler.u = ieee754sp_neg;
1464 SPFROMREG(rv.s, MIPSInst_FS(ir));
1467 /* binary op on handler */
1469 SPFROMREG(fs, MIPSInst_FS(ir));
1470 SPFROMREG(ft, MIPSInst_FT(ir));
1472 rv.s = (*handler.b) (fs, ft);
1475 SPFROMREG(fs, MIPSInst_FS(ir));
1476 rv.s = (*handler.u) (fs);
1479 if (ieee754_cxtest(IEEE754_INEXACT)) {
1480 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1481 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1483 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1484 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1485 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1487 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1488 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1489 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1491 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1492 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1493 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1495 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1496 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1497 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1501 /* unary conv ops */
1503 return SIGILL; /* not defined */
1506 SPFROMREG(fs, MIPSInst_FS(ir));
1507 rv.d = ieee754dp_fsp(fs);
1512 SPFROMREG(fs, MIPSInst_FS(ir));
1513 rv.w = ieee754sp_tint(fs);
1521 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1524 oldrm = ieee754_csr.rm;
1525 SPFROMREG(fs, MIPSInst_FS(ir));
1526 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1527 rv.w = ieee754sp_tint(fs);
1528 ieee754_csr.rm = oldrm;
1533 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1536 SPFROMREG(fs, MIPSInst_FS(ir));
1537 rv.l = ieee754sp_tlong(fs);
1545 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1548 oldrm = ieee754_csr.rm;
1549 SPFROMREG(fs, MIPSInst_FS(ir));
1550 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1551 rv.l = ieee754sp_tlong(fs);
1552 ieee754_csr.rm = oldrm;
1557 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1558 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1559 union ieee754sp fs, ft;
1561 SPFROMREG(fs, MIPSInst_FS(ir));
1562 SPFROMREG(ft, MIPSInst_FT(ir));
1563 rv.w = ieee754sp_cmp(fs, ft,
1564 cmptab[cmpop & 0x7], cmpop & 0x8);
1566 if ((cmpop & 0x8) && ieee754_cxtest
1567 (IEEE754_INVALID_OPERATION))
1568 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1580 union ieee754dp fs, ft;
1582 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1583 union ieee754dp(*u) (union ieee754dp);
1586 switch (MIPSInst_FUNC(ir)) {
1589 handler.b = ieee754dp_add;
1592 handler.b = ieee754dp_sub;
1595 handler.b = ieee754dp_mul;
1598 handler.b = ieee754dp_div;
1603 if (!cpu_has_mips_2_3_4_5_r)
1606 handler.u = ieee754dp_sqrt;
1609 * Note that on some MIPS IV implementations such as the
1610 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1611 * achieve full IEEE-754 accuracy - however this emulator does.
1614 if (!cpu_has_mips_4_5_r2)
1617 handler.u = fpemu_dp_rsqrt;
1620 if (!cpu_has_mips_4_5_r2)
1623 handler.u = fpemu_dp_recip;
1626 if (!cpu_has_mips_4_5_r)
1629 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1630 if (((ctx->fcr31 & cond) != 0) !=
1631 ((MIPSInst_FT(ir) & 1) != 0))
1633 DPFROMREG(rv.d, MIPSInst_FS(ir));
1636 if (!cpu_has_mips_4_5_r)
1639 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1641 DPFROMREG(rv.d, MIPSInst_FS(ir));
1644 if (!cpu_has_mips_4_5_r)
1647 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1649 DPFROMREG(rv.d, MIPSInst_FS(ir));
1652 handler.u = ieee754dp_abs;
1656 handler.u = ieee754dp_neg;
1661 DPFROMREG(rv.d, MIPSInst_FS(ir));
1664 /* binary op on handler */
1666 DPFROMREG(fs, MIPSInst_FS(ir));
1667 DPFROMREG(ft, MIPSInst_FT(ir));
1669 rv.d = (*handler.b) (fs, ft);
1672 DPFROMREG(fs, MIPSInst_FS(ir));
1673 rv.d = (*handler.u) (fs);
1680 DPFROMREG(fs, MIPSInst_FS(ir));
1681 rv.s = ieee754sp_fdp(fs);
1686 return SIGILL; /* not defined */
1689 DPFROMREG(fs, MIPSInst_FS(ir));
1690 rv.w = ieee754dp_tint(fs); /* wrong */
1698 if (!cpu_has_mips_2_3_4_5_r)
1701 oldrm = ieee754_csr.rm;
1702 DPFROMREG(fs, MIPSInst_FS(ir));
1703 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1704 rv.w = ieee754dp_tint(fs);
1705 ieee754_csr.rm = oldrm;
1710 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1713 DPFROMREG(fs, MIPSInst_FS(ir));
1714 rv.l = ieee754dp_tlong(fs);
1722 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1725 oldrm = ieee754_csr.rm;
1726 DPFROMREG(fs, MIPSInst_FS(ir));
1727 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1728 rv.l = ieee754dp_tlong(fs);
1729 ieee754_csr.rm = oldrm;
1734 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1735 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1736 union ieee754dp fs, ft;
1738 DPFROMREG(fs, MIPSInst_FS(ir));
1739 DPFROMREG(ft, MIPSInst_FT(ir));
1740 rv.w = ieee754dp_cmp(fs, ft,
1741 cmptab[cmpop & 0x7], cmpop & 0x8);
1746 (IEEE754_INVALID_OPERATION))
1747 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1760 switch (MIPSInst_FUNC(ir)) {
1762 /* convert word to single precision real */
1763 SPFROMREG(fs, MIPSInst_FS(ir));
1764 rv.s = ieee754sp_fint(fs.bits);
1768 /* convert word to double precision real */
1769 SPFROMREG(fs, MIPSInst_FS(ir));
1770 rv.d = ieee754dp_fint(fs.bits);
1781 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1784 DIFROMREG(bits, MIPSInst_FS(ir));
1786 switch (MIPSInst_FUNC(ir)) {
1788 /* convert long to single precision real */
1789 rv.s = ieee754sp_flong(bits);
1793 /* convert long to double precision real */
1794 rv.d = ieee754dp_flong(bits);
1807 * Update the fpu CSR register for this operation.
1808 * If an exception is required, generate a tidy SIGFPE exception,
1809 * without updating the result register.
1810 * Note: cause exception bits do not accumulate, they are rewritten
1811 * for each op; only the flag/sticky bits accumulate.
1813 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1814 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1815 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1820 * Now we can safely write the result back to the register file.
1825 if (cpu_has_mips_4_5_r)
1826 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1828 cbit = FPU_CSR_COND;
1832 ctx->fcr31 &= ~cbit;
1836 DPTOREG(rv.d, MIPSInst_FD(ir));
1839 SPTOREG(rv.s, MIPSInst_FD(ir));
1842 SITOREG(rv.w, MIPSInst_FD(ir));
1845 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1848 DITOREG(rv.l, MIPSInst_FD(ir));
1857 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1858 int has_fpu, void *__user *fault_addr)
1860 unsigned long oldepc, prevepc;
1861 struct mm_decoded_insn dec_insn;
1866 oldepc = xcp->cp0_epc;
1868 prevepc = xcp->cp0_epc;
1870 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1872 * Get next 2 microMIPS instructions and convert them
1873 * into 32-bit instructions.
1875 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
1876 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
1877 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
1878 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
1879 MIPS_FPU_EMU_INC_STATS(errors);
1884 /* Get first instruction. */
1885 if (mm_insn_16bit(*instr_ptr)) {
1886 /* Duplicate the half-word. */
1887 dec_insn.insn = (*instr_ptr << 16) |
1889 /* 16-bit instruction. */
1890 dec_insn.pc_inc = 2;
1893 dec_insn.insn = (*instr_ptr << 16) |
1895 /* 32-bit instruction. */
1896 dec_insn.pc_inc = 4;
1899 /* Get second instruction. */
1900 if (mm_insn_16bit(*instr_ptr)) {
1901 /* Duplicate the half-word. */
1902 dec_insn.next_insn = (*instr_ptr << 16) |
1904 /* 16-bit instruction. */
1905 dec_insn.next_pc_inc = 2;
1907 dec_insn.next_insn = (*instr_ptr << 16) |
1909 /* 32-bit instruction. */
1910 dec_insn.next_pc_inc = 4;
1912 dec_insn.micro_mips_mode = 1;
1914 if ((get_user(dec_insn.insn,
1915 (mips_instruction __user *) xcp->cp0_epc)) ||
1916 (get_user(dec_insn.next_insn,
1917 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
1918 MIPS_FPU_EMU_INC_STATS(errors);
1921 dec_insn.pc_inc = 4;
1922 dec_insn.next_pc_inc = 4;
1923 dec_insn.micro_mips_mode = 0;
1926 if ((dec_insn.insn == 0) ||
1927 ((dec_insn.pc_inc == 2) &&
1928 ((dec_insn.insn & 0xffff) == MM_NOP16)))
1929 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1932 * The 'ieee754_csr' is an alias of
1933 * ctx->fcr31. No need to copy ctx->fcr31 to
1934 * ieee754_csr. But ieee754_csr.rm is ieee
1935 * library modes. (not mips rounding mode)
1937 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1946 } while (xcp->cp0_epc > prevepc);
1948 /* SIGILL indicates a non-fpu instruction */
1949 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1950 /* but if EPC has advanced, then ignore it */