arch/mips/mti-malta/malta-setup.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
   4  * Copyright (C) 2008 Dmitri Vorobiev
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  */
  19 #include <linux/cpu.h>
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/ioport.h>
  23 #include <linux/irq.h>
  24 #include <linux/pci.h>
  25 #include <linux/screen_info.h>
  26 #include <linux/time.h>
  27
  28 #include <asm/fw/fw.h>
  29 #include <asm/mips-cm.h>
  30 #include <asm/mips-boards/generic.h>
  31 #include <asm/mips-boards/malta.h>
  32 #include <asm/mips-boards/maltaint.h>
  33 #include <asm/dma.h>
  34 #include <asm/traps.h>
  35 #ifdef CONFIG_VT
  36 #include <linux/console.h>
  37 #endif
  38
  39 extern void malta_be_init(void);
  40 extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
  41
  42 static struct resource standard_io_resources[] = {
  43         {
  44                 .name = "dma1",
  45                 .start = 0x00,
  46                 .end = 0x1f,
  47                 .flags = IORESOURCE_BUSY
  48         },
  49         {
  50                 .name = "timer",
  51                 .start = 0x40,
  52                 .end = 0x5f,
  53                 .flags = IORESOURCE_BUSY
  54         },
  55         {
  56                 .name = "keyboard",
  57                 .start = 0x60,
  58                 .end = 0x6f,
  59                 .flags = IORESOURCE_BUSY
  60         },
  61         {
  62                 .name = "dma page reg",
  63                 .start = 0x80,
  64                 .end = 0x8f,
  65                 .flags = IORESOURCE_BUSY
  66         },
  67         {
  68                 .name = "dma2",
  69                 .start = 0xc0,
  70                 .end = 0xdf,
  71                 .flags = IORESOURCE_BUSY
  72         },
  73 };
  74
  75 const char *get_system_type(void)
  76 {
  77         return "MIPS Malta";
  78 }
  79
  80 #if defined(CONFIG_MIPS_MT_SMTC)
  81 const char display_string[] = "       SMTC LINUX ON MALTA       ";
  82 #else
  83 const char display_string[] = "        LINUX ON MALTA       ";
  84 #endif /* CONFIG_MIPS_MT_SMTC */
  85
  86 #ifdef CONFIG_BLK_DEV_FD
  87 static void __init fd_activate(void)
  88 {
  89         /*
  90          * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
  91          * Controller.
  92          * Done by YAMON 2.00 onwards
  93          */
  94         /* Entering config state. */
  95         SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
  96
  97         /* Activate floppy controller. */
  98         SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
  99         SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
 100         SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
 101         SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
 102
 103         /* Exit config state. */
 104         SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
 105 }
 106 #endif
 107
 108 static int __init plat_enable_iocoherency(void)
 109 {
 110         int supported = 0;
 111         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
 112                 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
 113                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
 114                         pr_info("Enabled Bonito CPU coherency\n");
 115                         supported = 1;
 116                 }
 117                 if (strstr(fw_getcmdline(), "iobcuncached")) {
 118                         BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
 119                         BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
 120                                 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 121                                   BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 122                         pr_info("Disabled Bonito IOBC coherency\n");
 123                 } else {
 124                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
 125                         BONITO_PCIMEMBASECFG |=
 126                                 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 127                                  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 128                         pr_info("Enabled Bonito IOBC coherency\n");
 129                 }
 130         } else if (mips_cm_numiocu() != 0) {
 131                 /* Nothing special needs to be done to enable coherency */
 132                 pr_info("CMP IOCU detected\n");
 133                 if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
 134                         pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
 135                         return 0;
 136                 }
 137                 supported = 1;
 138         }
 139         hw_coherentio = supported;
 140         return supported;
 141 }
 142
 143 static void __init plat_setup_iocoherency(void)
 144 {
 145 #ifdef CONFIG_DMA_NONCOHERENT
 146         /*
 147          * Kernel has been configured with software coherency
 148          * but we might choose to turn it off and use hardware
 149          * coherency instead.
 150          */
 151         if (plat_enable_iocoherency()) {
 152                 if (coherentio == 0)
 153                         pr_info("Hardware DMA cache coherency disabled\n");
 154                 else
 155                         pr_info("Hardware DMA cache coherency enabled\n");
 156         } else {
 157                 if (coherentio == 1)
 158                         pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
 159                 else
 160                         pr_info("Software DMA cache coherency enabled\n");
 161         }
 162 #else
 163         if (!plat_enable_iocoherency())
 164                 panic("Hardware DMA cache coherency not supported!");
 165 #endif
 166 }
 167
 168 static void __init pci_clock_check(void)
 169 {
 170         unsigned int __iomem *jmpr_p =
 171                 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
 172         int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
 173         static const int pciclocks[] __initconst = {
 174                 33, 20, 25, 30, 12, 16, 37, 10
 175         };
 176         int pciclock = pciclocks[jmpr];
 177         char *optptr, *argptr = fw_getcmdline();
 178
 179         /*
 180          * If user passed a pci_clock= option, don't tack on another one
 181          */
 182         optptr = strstr(argptr, "pci_clock=");
 183         if (optptr && (optptr == argptr || optptr[-1] == ' '))
 184                 return;
 185
 186         if (pciclock != 33) {
 187                 pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
 188                         pciclock);
 189                 argptr += strlen(argptr);
 190                 sprintf(argptr, " pci_clock=%d", pciclock);
 191                 if (pciclock < 20 || pciclock > 66)
 192                         pr_warn("WARNING: IDE timing calculations will be "
 193                                 "incorrect\n");
 194         }
 195 }
 196
 197 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
 198 static void __init screen_info_setup(void)
 199 {
 200         screen_info = (struct screen_info) {
 201                 .orig_x = 0,
 202                 .orig_y = 25,
 203                 .ext_mem_k = 0,
 204                 .orig_video_page = 0,
 205                 .orig_video_mode = 0,
 206                 .orig_video_cols = 80,
 207                 .unused2 = 0,
 208                 .orig_video_ega_bx = 0,
 209                 .unused3 = 0,
 210                 .orig_video_lines = 25,
 211                 .orig_video_isVGA = VIDEO_TYPE_VGAC,
 212                 .orig_video_points = 16
 213         };
 214 }
 215 #endif
 216
 217 static void __init bonito_quirks_setup(void)
 218 {
 219         char *argptr;
 220
 221         argptr = fw_getcmdline();
 222         if (strstr(argptr, "debug")) {
 223                 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
 224                 pr_info("Enabled Bonito debug mode\n");
 225         } else
 226                 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
 227
 228 #ifdef CONFIG_DMA_COHERENT
 229         if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
 230                 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
 231                 pr_info("Enabled Bonito CPU coherency\n");
 232
 233                 argptr = fw_getcmdline();
 234                 if (strstr(argptr, "iobcuncached")) {
 235                         BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
 236                         BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
 237                                 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 238                                         BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 239                         pr_info("Disabled Bonito IOBC coherency\n");
 240                 } else {
 241                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
 242                         BONITO_PCIMEMBASECFG |=
 243                                 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 244                                         BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 245                         pr_info("Enabled Bonito IOBC coherency\n");
 246                 }
 247         } else
 248                 panic("Hardware DMA cache coherency not supported");
 249 #endif
 250 }
 251
 252 void __init plat_mem_setup(void)
 253 {
 254         unsigned int i;
 255
 256         if (config_enabled(CONFIG_EVA))
 257                 /* EVA has already been configured in mach-malta/kernel-init.h */
 258                 pr_info("Enhanced Virtual Addressing (EVA) activated\n");
 259
 260         mips_pcibios_init();
 261
 262         /* Request I/O space for devices used on the Malta board. */
 263         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
 264                 request_resource(&ioport_resource, standard_io_resources+i);
 265
 266         /*
 267          * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
 268          */
 269         enable_dma(4);
 270
 271 #ifdef CONFIG_DMA_COHERENT
 272         if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
 273                 panic("Hardware DMA cache coherency not supported");
 274 #endif
 275
 276         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
 277                 bonito_quirks_setup();
 278
 279         plat_setup_iocoherency();
 280
 281         pci_clock_check();
 282
 283 #ifdef CONFIG_BLK_DEV_FD
 284         fd_activate();
 285 #endif
 286
 287 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
 288         screen_info_setup();
 289 #endif
 290
 291         board_be_init = malta_be_init;
 292         board_be_handler = malta_be_handler;
 293 }