2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/asm-offsets.h>
27 /* we have the following possibilities to act on an interruption:
28 * - handle in assembly and use shadowed registers only
29 * - save registers to kernel stack and handle in assembly or C */
33 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
34 #include <asm/assembly.h> /* for LDREG/STREG defines */
35 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
38 #include <asm/thread_info.h>
40 #include <linux/linkage.h>
48 .import pa_dbit_lock,data
50 /* space_to_prot macro creates a prot id from a space id */
52 #if (SPACEID_SHIFT) == 0
53 .macro space_to_prot spc prot
54 depd,z \spc,62,31,\prot
57 .macro space_to_prot spc prot
58 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
62 /* Switch to virtual mapping, trashing only %r1 */
65 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
69 or,= %r0,%r1,%r0 /* Only save sr7 in sr3 if sr7 != 0 */
72 load32 KERNEL_PSW, %r1
74 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
77 mtctl %r0, %cr17 /* Clear IIASQ tail */
78 mtctl %r0, %cr17 /* Clear IIASQ head */
81 mtctl %r1, %cr18 /* Set IIAOQ tail */
83 mtctl %r1, %cr18 /* Set IIAOQ head */
90 * The "get_stack" macros are responsible for determining the
94 * Already using a kernel stack, so call the
95 * get_stack_use_r30 macro to push a pt_regs structure
96 * on the stack, and store registers there.
98 * Need to set up a kernel stack, so call the
99 * get_stack_use_cr30 macro to set up a pointer
100 * to the pt_regs structure contained within the
101 * task pointer pointed to by cr30. Set the stack
102 * pointer to point to the end of the task structure.
104 * Note that we use shadowed registers for temps until
105 * we can save %r26 and %r29. %r26 is used to preserve
106 * %r8 (a shadowed register) which temporarily contained
107 * either the fault type ("code") or the eirr. We need
108 * to use a non-shadowed register to carry the value over
109 * the rfir in virt_map. We use %r26 since this value winds
110 * up being passed as the argument to either do_cpu_irq_mask
111 * or handle_interruption. %r29 is used to hold a pointer
112 * the register save area, and once again, it needs to
113 * be a non-shadowed register so that it survives the rfir.
115 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
118 .macro get_stack_use_cr30
120 /* we save the registers in the task struct */
124 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
126 ldo TASK_REGS(%r9),%r9
127 STREG %r30, PT_GR30(%r9)
128 STREG %r29,PT_GR29(%r9)
129 STREG %r26,PT_GR26(%r9)
132 ldo THREAD_SZ_ALGN(%r1), %r30
135 .macro get_stack_use_r30
137 /* we put a struct pt_regs on the stack and save the registers there */
140 STREG %r30,PT_GR30(%r9)
141 ldo PT_SZ_ALGN(%r30),%r30
142 STREG %r29,PT_GR29(%r9)
143 STREG %r26,PT_GR26(%r9)
148 LDREG PT_GR1(%r29), %r1
149 LDREG PT_GR30(%r29),%r30
150 LDREG PT_GR29(%r29),%r29
153 /* default interruption handler
154 * (calls traps.c:handle_interruption) */
161 /* Interrupt interruption handler
162 * (calls irq.c:do_cpu_irq_mask) */
169 .import os_hpmc, code
173 nop /* must be a NOP, will be patched later */
174 load32 PA(os_hpmc), %r3
177 .word 0 /* checksum (will be patched) */
178 .word PA(os_hpmc) /* address of handler */
179 .word 0 /* length of handler */
183 * Performance Note: Instructions will be moved up into
184 * this part of the code later on, once we are sure
185 * that the tlb miss handlers are close to final form.
188 /* Register definitions for tlb miss handler macros */
190 va = r8 /* virtual address for which the trap occurred */
191 spc = r24 /* space for which the trap occurred */
196 * itlb miss interruption handler (parisc 1.1 - 32 bit)
210 * itlb miss interruption handler (parisc 2.0)
227 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
230 .macro naitlb_11 code
241 * naitlb miss interruption handler (parisc 2.0)
244 .macro naitlb_20 code
259 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
273 * dtlb miss interruption handler (parisc 2.0)
290 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
292 .macro nadtlb_11 code
302 /* nadtlb miss interruption handler (parisc 2.0) */
304 .macro nadtlb_20 code
319 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
333 * dirty bit trap interruption handler (parisc 2.0)
349 /* In LP64, the space contains part of the upper 32 bits of the
350 * fault. We have to extract this and place it in the va,
351 * zeroing the corresponding bits in the space register */
352 .macro space_adjust spc,va,tmp
354 extrd,u \spc,63,SPACEID_SHIFT,\tmp
355 depd %r0,63,SPACEID_SHIFT,\spc
356 depd \tmp,31,SPACEID_SHIFT,\va
360 .import swapper_pg_dir,code
362 /* Get the pgd. For faults on space zero (kernel space), this
363 * is simply swapper_pg_dir. For user space faults, the
364 * pgd is stored in %cr25 */
365 .macro get_pgd spc,reg
366 ldil L%PA(swapper_pg_dir),\reg
367 ldo R%PA(swapper_pg_dir)(\reg),\reg
368 or,COND(=) %r0,\spc,%r0
373 space_check(spc,tmp,fault)
375 spc - The space we saw the fault with.
376 tmp - The place to store the current space.
377 fault - Function to call on failure.
379 Only allow faults on different spaces from the
380 currently active one if we're the kernel
383 .macro space_check spc,tmp,fault
385 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
386 * as kernel, so defeat the space
389 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
390 cmpb,COND(<>),n \tmp,\spc,\fault
393 /* Look up a PTE in a 2-Level scheme (faulting at each
394 * level if the entry isn't present
396 * NOTE: we use ldw even for LP64, since the short pointers
397 * can address up to 1TB
399 .macro L2_ptep pmd,pte,index,va,fault
401 extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
403 # if defined(CONFIG_64BIT)
404 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
406 # if PAGE_SIZE > 4096
407 extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
409 extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
413 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
415 ldw,s \index(\pmd),\pmd
416 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
417 dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
419 SHLREG %r9,PxD_VALUE_SHIFT,\pmd
420 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
421 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
422 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
423 LDREG %r0(\pmd),\pte /* pmd is now pte */
424 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
427 /* Look up PTE in a 3-Level scheme.
429 * Here we implement a Hybrid L2/L3 scheme: we allocate the
430 * first pmd adjacent to the pgd. This means that we can
431 * subtract a constant offset to get to it. The pmd and pgd
432 * sizes are arranged so that a single pmd covers 4GB (giving
433 * a full LP64 process access to 8TB) so our lookups are
434 * effectively L2 for the first 4GB of the kernel (i.e. for
435 * all ILP32 processes and all the kernel for machines with
436 * under 4GB of memory) */
437 .macro L3_ptep pgd,pte,index,va,fault
438 #if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
439 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
441 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
442 ldw,s \index(\pgd),\pgd
443 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
444 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
445 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
446 shld \pgd,PxD_VALUE_SHIFT,\index
447 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
449 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
450 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
452 L2_ptep \pgd,\pte,\index,\va,\fault
455 /* Acquire pa_dbit_lock lock. */
456 .macro dbit_lock spc,tmp,tmp1
458 cmpib,COND(=),n 0,\spc,2f
459 load32 PA(pa_dbit_lock),\tmp
460 1: LDCW 0(\tmp),\tmp1
461 cmpib,COND(=) 0,\tmp1,1b
467 /* Release pa_dbit_lock lock without reloading lock address. */
468 .macro dbit_unlock0 spc,tmp
470 or,COND(=) %r0,\spc,%r0
475 /* Release pa_dbit_lock lock. */
476 .macro dbit_unlock1 spc,tmp
478 load32 PA(pa_dbit_lock),\tmp
479 dbit_unlock0 \spc,\tmp
483 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
484 * don't needlessly dirty the cache line if it was already set */
485 .macro update_ptep spc,ptep,pte,tmp,tmp1
487 or,COND(=) %r0,\spc,%r0
490 ldi _PAGE_ACCESSED,\tmp1
492 and,COND(<>) \tmp1,\pte,%r0
496 /* Set the dirty bit (and accessed bit). No need to be
497 * clever, this is only used from the dirty fault */
498 .macro update_dirty spc,ptep,pte,tmp
500 or,COND(=) %r0,\spc,%r0
503 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
508 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
509 * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
510 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
512 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
513 .macro convert_for_tlb_insert20 pte
514 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
515 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
516 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
517 (63-58)+PAGE_ADD_SHIFT,\pte
520 /* Convert the pte and prot to tlb insertion values. How
521 * this happens is quite subtle, read below */
522 .macro make_insert_tlb spc,pte,prot
523 space_to_prot \spc \prot /* create prot id from space */
524 /* The following is the real subtlety. This is depositing
525 * T <-> _PAGE_REFTRAP
527 * B <-> _PAGE_DMB (memory break)
529 * Then incredible subtlety: The access rights are
530 * _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE
531 * See 3-14 of the parisc 2.0 manual
533 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
534 * trigger an access rights trap in user space if the user
535 * tries to read an unreadable page */
538 /* PAGE_USER indicates the page can be read with user privileges,
539 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
540 * contains _PAGE_READ) */
541 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
543 /* If we're a gateway page, drop PL2 back to zero for promotion
544 * to kernel privilege (so we can execute the page as kernel).
545 * Any privilege promotion page always denys read and write */
546 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
547 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
549 /* Enforce uncacheable pages.
550 * This should ONLY be use for MMIO on PA 2.0 machines.
551 * Memory/DMA is cache coherent on all PA2.0 machines we support
552 * (that means T-class is NOT supported) and the memory controllers
553 * on most of those machines only handles cache transactions.
555 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
558 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
559 convert_for_tlb_insert20 \pte
562 /* Identical macro to make_insert_tlb above, except it
563 * makes the tlb entry for the differently formatted pa11
564 * insertion instructions */
565 .macro make_insert_tlb_11 spc,pte,prot
566 zdep \spc,30,15,\prot
568 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
570 extru,= \pte,_PAGE_USER_BIT,1,%r0
571 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
572 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
573 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
575 /* Get rid of prot bits and convert to page addr for iitlba */
577 depi 0,31,ASM_PFN_PTE_SHIFT,\pte
578 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
581 /* This is for ILP32 PA2.0 only. The TLB insertion needs
582 * to extend into I/O space if the address is 0xfXXXXXXX
583 * so we extend the f's into the top word of the pte in
585 .macro f_extend pte,tmp
586 extrd,s \pte,42,4,\tmp
588 extrd,s \pte,63,25,\pte
591 /* The alias region is an 8MB aligned 16MB to do clear and
592 * copy user pages at addresses congruent with the user
595 * To use the alias page, you set %r26 up with the to TLB
596 * entry (identifying the physical page) and %r23 up with
597 * the from tlb entry (or nothing if only a to entry---for
598 * clear_user_page_asm) */
599 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault,patype
600 cmpib,COND(<>),n 0,\spc,\fault
601 ldil L%(TMPALIAS_MAP_START),\tmp
602 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
603 /* on LP64, ldi will sign extend into the upper 32 bits,
604 * which is behaviour we don't want */
609 cmpb,COND(<>),n \tmp,\tmp1,\fault
610 mfctl %cr19,\tmp /* iir */
611 /* get the opcode (first six bits) into \tmp */
612 extrw,u \tmp,5,6,\tmp
614 * Only setting the T bit prevents data cache movein
615 * Setting access rights to zero prevents instruction cache movein
617 * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
618 * to type field and _PAGE_READ goes to top bit of PL1
620 ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
622 * so if the opcode is one (i.e. this is a memory management
623 * instruction) nullify the next load so \prot is only T.
624 * Otherwise this is a normal data operation
626 cmpiclr,= 0x01,\tmp,%r0
627 ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
629 depd,z \prot,8,7,\prot
632 depw,z \prot,8,7,\prot
634 .error "undefined PA type to do_alias"
638 * OK, it is in the temp alias region, check whether "from" or "to".
639 * Check "subtle" note in pacache.S re: r23/r26.
642 extrd,u,*= \va,41,1,%r0
644 extrw,u,= \va,9,1,%r0
646 or,COND(tr) %r23,%r0,\pte
652 * Align fault_vector_20 on 4K boundary so that both
653 * fault_vector_11 and fault_vector_20 are on the
654 * same page. This is only necessary as long as we
655 * write protect the kernel text, which we may stop
656 * doing once we use large page translations to cover
657 * the static part of the kernel address space.
664 ENTRY(fault_vector_20)
665 /* First vector is invalid (0) */
666 .ascii "cows can fly"
707 ENTRY(fault_vector_11)
708 /* First vector is invalid (0) */
709 .ascii "cows can fly"
747 /* Fault vector is separately protected and *must* be on its own page */
749 ENTRY(end_fault_vector)
751 .import handle_interruption,code
752 .import do_cpu_irq_mask,code
757 * copy_thread moved args into task save area.
760 ENTRY(ret_from_kernel_thread)
762 /* Call schedule_tail first though */
763 BL schedule_tail, %r2
766 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
767 LDREG TASK_PT_GR25(%r1), %r26
769 LDREG TASK_PT_GR27(%r1), %r27
771 LDREG TASK_PT_GR26(%r1), %r1
774 b finish_child_return
776 ENDPROC(ret_from_kernel_thread)
780 * struct task_struct *_switch_to(struct task_struct *prev,
781 * struct task_struct *next)
783 * switch kernel stacks and return prev */
785 STREG %r2, -RP_OFFSET(%r30)
790 load32 _switch_to_ret, %r2
792 STREG %r2, TASK_PT_KPC(%r26)
793 LDREG TASK_PT_KPC(%r25), %r2
795 STREG %r30, TASK_PT_KSP(%r26)
796 LDREG TASK_PT_KSP(%r25), %r30
797 LDREG TASK_THREAD_INFO(%r25), %r25
802 mtctl %r0, %cr0 /* Needed for single stepping */
806 LDREG -RP_OFFSET(%r30), %r2
812 * Common rfi return path for interruptions, kernel execve, and
813 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
814 * return via this path if the signal was received when the process
815 * was running; if the process was blocked on a syscall then the
816 * normal syscall_exit path is used. All syscalls for traced
817 * proceses exit via intr_restore.
819 * XXX If any syscalls that change a processes space id ever exit
820 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
827 ENTRY(syscall_exit_rfi)
829 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
830 ldo TASK_REGS(%r16),%r16
831 /* Force iaoq to userspace, as the user has had access to our current
832 * context via sigcontext. Also Filter the PSW for the same reason.
834 LDREG PT_IAOQ0(%r16),%r19
836 STREG %r19,PT_IAOQ0(%r16)
837 LDREG PT_IAOQ1(%r16),%r19
839 STREG %r19,PT_IAOQ1(%r16)
840 LDREG PT_PSW(%r16),%r19
841 load32 USER_PSW_MASK,%r1
843 load32 USER_PSW_HI_MASK,%r20
846 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
848 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
849 STREG %r19,PT_PSW(%r16)
852 * If we aren't being traced, we never saved space registers
853 * (we don't store them in the sigcontext), so set them
854 * to "proper" values now (otherwise we'll wind up restoring
855 * whatever was last stored in the task structure, which might
856 * be inconsistent if an interrupt occurred while on the gateway
857 * page). Note that we may be "trashing" values the user put in
858 * them, but we don't support the user changing them.
861 STREG %r0,PT_SR2(%r16)
863 STREG %r19,PT_SR0(%r16)
864 STREG %r19,PT_SR1(%r16)
865 STREG %r19,PT_SR3(%r16)
866 STREG %r19,PT_SR4(%r16)
867 STREG %r19,PT_SR5(%r16)
868 STREG %r19,PT_SR6(%r16)
869 STREG %r19,PT_SR7(%r16)
872 /* check for reschedule */
874 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
875 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
877 .import do_notify_resume,code
881 LDREG TI_FLAGS(%r1),%r19
882 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r20
883 and,COND(<>) %r19, %r20, %r0
884 b,n intr_restore /* skip past if we've nothing to do */
886 /* This check is critical to having LWS
887 * working. The IASQ is zero on the gateway
888 * page and we cannot deliver any signals until
889 * we get off the gateway page.
891 * Only do signals if we are returning to user space
893 LDREG PT_IASQ0(%r16), %r20
894 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
895 LDREG PT_IASQ1(%r16), %r20
896 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
898 /* NOTE: We need to enable interrupts if we have to deliver
899 * signals. We used to do this earlier but it caused kernel
900 * stack overflows. */
903 copy %r0, %r25 /* long in_syscall = 0 */
905 ldo -16(%r30),%r29 /* Reference param save area */
908 BL do_notify_resume,%r2
909 copy %r16, %r26 /* struct pt_regs *regs */
915 ldo PT_FR31(%r29),%r1
919 /* inverse of virt_map */
921 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
924 /* Restore space id's and special cr's from PT_REGS
925 * structure pointed to by r29
929 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
930 * It also restores r1 and r30.
937 #ifndef CONFIG_PREEMPT
938 # define intr_do_preempt intr_restore
939 #endif /* !CONFIG_PREEMPT */
941 .import schedule,code
943 /* Only call schedule on return to userspace. If we're returning
944 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
945 * we jump back to intr_restore.
947 LDREG PT_IASQ0(%r16), %r20
948 cmpib,COND(=) 0, %r20, intr_do_preempt
950 LDREG PT_IASQ1(%r16), %r20
951 cmpib,COND(=) 0, %r20, intr_do_preempt
954 /* NOTE: We need to enable interrupts if we schedule. We used
955 * to do this earlier but it caused kernel stack overflows. */
959 ldo -16(%r30),%r29 /* Reference param save area */
962 ldil L%intr_check_sig, %r2
966 load32 schedule, %r20
969 ldo R%intr_check_sig(%r2), %r2
971 /* preempt the current task on returning to kernel
972 * mode from an interrupt, iff need_resched is set,
973 * and preempt_count is 0. otherwise, we continue on
974 * our merry way back to the current running task.
976 #ifdef CONFIG_PREEMPT
977 .import preempt_schedule_irq,code
979 rsm PSW_SM_I, %r0 /* disable interrupts */
981 /* current_thread_info()->preempt_count */
983 LDREG TI_PRE_COUNT(%r1), %r19
984 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
985 nop /* prev insn branched backwards */
987 /* check if we interrupted a critical path */
988 LDREG PT_PSW(%r16), %r20
989 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
992 BL preempt_schedule_irq, %r2
995 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
996 #endif /* CONFIG_PREEMPT */
999 * External interrupts.
1003 cmpib,COND(=),n 0,%r16,1f
1015 ldo PT_FR0(%r29), %r24
1020 copy %r29, %r26 /* arg0 is pt_regs */
1021 copy %r29, %r16 /* save pt_regs */
1023 ldil L%intr_return, %r2
1026 ldo -16(%r30),%r29 /* Reference param save area */
1030 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1031 ENDPROC(syscall_exit_rfi)
1034 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1036 ENTRY(intr_save) /* for os_hpmc */
1038 cmpib,COND(=),n 0,%r16,1f
1050 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1053 * FIXME: 1) Use a #define for the hardwired "6" below (and in
1055 * 2) Once we start executing code above 4 Gb, we need
1056 * to adjust iasq/iaoq here in the same way we
1057 * adjust isr/ior below.
1060 cmpib,COND(=),n 6,%r26,skip_save_ior
1063 mfctl %cr20, %r16 /* isr */
1064 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1065 mfctl %cr21, %r17 /* ior */
1070 * If the interrupted code was running with W bit off (32 bit),
1071 * clear the b bits (bits 0 & 1) in the ior.
1072 * save_specials left ipsw value in r8 for us to test.
1074 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1078 * FIXME: This code has hardwired assumptions about the split
1079 * between space bits and offset bits. This will change
1080 * when we allow alternate page sizes.
1083 /* adjust isr/ior. */
1084 extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
1085 depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
1086 depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
1088 STREG %r16, PT_ISR(%r29)
1089 STREG %r17, PT_IOR(%r29)
1096 ldo PT_FR0(%r29), %r25
1101 copy %r29, %r25 /* arg1 is pt_regs */
1103 ldo -16(%r30),%r29 /* Reference param save area */
1106 ldil L%intr_check_sig, %r2
1107 copy %r25, %r16 /* save pt_regs */
1109 b handle_interruption
1110 ldo R%intr_check_sig(%r2), %r2
1115 * Note for all tlb miss handlers:
1117 * cr24 contains a pointer to the kernel address space
1120 * cr25 contains a pointer to the current user address
1121 * space page directory.
1123 * sr3 will contain the space id of the user address space
1124 * of the current running thread while that thread is
1125 * running in the kernel.
1129 * register number allocations. Note that these are all
1130 * in the shadowed registers
1133 t0 = r1 /* temporary register 0 */
1134 va = r8 /* virtual address for which the trap occurred */
1135 t1 = r9 /* temporary register 1 */
1136 pte = r16 /* pte/phys page # */
1137 prot = r17 /* prot bits */
1138 spc = r24 /* space for which the trap occurred */
1139 ptp = r25 /* page directory/page table pointer */
1144 space_adjust spc,va,t0
1146 space_check spc,t0,dtlb_fault
1148 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1151 update_ptep spc,ptp,pte,t0,t1
1153 make_insert_tlb spc,pte,prot
1161 dtlb_check_alias_20w:
1162 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1170 space_adjust spc,va,t0
1172 space_check spc,t0,nadtlb_fault
1174 L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
1177 update_ptep spc,ptp,pte,t0,t1
1179 make_insert_tlb spc,pte,prot
1187 nadtlb_check_alias_20w:
1188 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1200 space_check spc,t0,dtlb_fault
1202 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1205 update_ptep spc,ptp,pte,t0,t1
1207 make_insert_tlb_11 spc,pte,prot
1209 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1212 idtlba pte,(%sr1,va)
1213 idtlbp prot,(%sr1,va)
1215 mtsp t0, %sr1 /* Restore sr1 */
1221 dtlb_check_alias_11:
1222 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,11
1233 space_check spc,t0,nadtlb_fault
1235 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
1238 update_ptep spc,ptp,pte,t0,t1
1240 make_insert_tlb_11 spc,pte,prot
1243 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1246 idtlba pte,(%sr1,va)
1247 idtlbp prot,(%sr1,va)
1249 mtsp t0, %sr1 /* Restore sr1 */
1255 nadtlb_check_alias_11:
1256 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,11
1265 space_adjust spc,va,t0
1267 space_check spc,t0,dtlb_fault
1269 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1272 update_ptep spc,ptp,pte,t0,t1
1274 make_insert_tlb spc,pte,prot
1284 dtlb_check_alias_20:
1285 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1295 space_check spc,t0,nadtlb_fault
1297 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
1300 update_ptep spc,ptp,pte,t0,t1
1302 make_insert_tlb spc,pte,prot
1312 nadtlb_check_alias_20:
1313 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1325 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1326 * probei instructions. We don't want to fault for these
1327 * instructions (not only does it not make sense, it can cause
1328 * deadlocks, since some flushes are done with the mmap
1329 * semaphore held). If the translation doesn't exist, we can't
1330 * insert a translation, so have to emulate the side effects
1331 * of the instruction. Since we don't insert a translation
1332 * we can get a lot of faults during a flush loop, so it makes
1333 * sense to try to do it here with minimum overhead. We only
1334 * emulate fdc,fic,pdc,probew,prober instructions whose base
1335 * and index registers are not shadowed. We defer everything
1336 * else to the "slow" path.
1339 mfctl %cr19,%r9 /* Get iir */
1341 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1342 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1344 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1347 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1348 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1349 BL get_register,%r25
1350 extrw,u %r9,15,5,%r8 /* Get index register # */
1351 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1353 BL get_register,%r25
1354 extrw,u %r9,10,5,%r8 /* Get base register # */
1355 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1356 BL set_register,%r25
1357 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1362 or %r8,%r9,%r8 /* Set PSW_N */
1369 When there is no translation for the probe address then we
1370 must nullify the insn and return zero in the target regsiter.
1371 This will indicate to the calling code that it does not have
1372 write/read privileges to this address.
1374 This should technically work for prober and probew in PA 1.1,
1375 and also probe,r and probe,w in PA 2.0
1377 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1378 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1384 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1385 BL get_register,%r25 /* Find the target register */
1386 extrw,u %r9,31,5,%r8 /* Get target register */
1387 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1388 BL set_register,%r25
1389 copy %r0,%r1 /* Write zero to target register */
1390 b nadtlb_nullify /* Nullify return insn */
1398 * I miss is a little different, since we allow users to fault
1399 * on the gateway page which is in the kernel address space.
1402 space_adjust spc,va,t0
1404 space_check spc,t0,itlb_fault
1406 L3_ptep ptp,pte,t0,va,itlb_fault
1409 update_ptep spc,ptp,pte,t0,t1
1411 make_insert_tlb spc,pte,prot
1422 * I miss is a little different, since we allow users to fault
1423 * on the gateway page which is in the kernel address space.
1426 space_adjust spc,va,t0
1428 space_check spc,t0,naitlb_fault
1430 L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
1433 update_ptep spc,ptp,pte,t0,t1
1435 make_insert_tlb spc,pte,prot
1443 naitlb_check_alias_20w:
1444 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1456 space_check spc,t0,itlb_fault
1458 L2_ptep ptp,pte,t0,va,itlb_fault
1461 update_ptep spc,ptp,pte,t0,t1
1463 make_insert_tlb_11 spc,pte,prot
1465 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1468 iitlba pte,(%sr1,va)
1469 iitlbp prot,(%sr1,va)
1471 mtsp t0, %sr1 /* Restore sr1 */
1480 space_check spc,t0,naitlb_fault
1482 L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
1485 update_ptep spc,ptp,pte,t0,t1
1487 make_insert_tlb_11 spc,pte,prot
1489 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1492 iitlba pte,(%sr1,va)
1493 iitlbp prot,(%sr1,va)
1495 mtsp t0, %sr1 /* Restore sr1 */
1501 naitlb_check_alias_11:
1502 do_alias spc,t0,t1,va,pte,prot,itlb_fault,11
1504 iitlba pte,(%sr0, va)
1505 iitlbp prot,(%sr0, va)
1514 space_check spc,t0,itlb_fault
1516 L2_ptep ptp,pte,t0,va,itlb_fault
1519 update_ptep spc,ptp,pte,t0,t1
1521 make_insert_tlb spc,pte,prot
1534 space_check spc,t0,naitlb_fault
1536 L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
1539 update_ptep spc,ptp,pte,t0,t1
1541 make_insert_tlb spc,pte,prot
1551 naitlb_check_alias_20:
1552 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1564 space_adjust spc,va,t0
1566 space_check spc,t0,dbit_fault
1568 L3_ptep ptp,pte,t0,va,dbit_fault
1571 update_dirty spc,ptp,pte,t1
1573 make_insert_tlb spc,pte,prot
1586 space_check spc,t0,dbit_fault
1588 L2_ptep ptp,pte,t0,va,dbit_fault
1591 update_dirty spc,ptp,pte,t1
1593 make_insert_tlb_11 spc,pte,prot
1595 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1598 idtlba pte,(%sr1,va)
1599 idtlbp prot,(%sr1,va)
1601 mtsp t1, %sr1 /* Restore sr1 */
1610 space_check spc,t0,dbit_fault
1612 L2_ptep ptp,pte,t0,va,dbit_fault
1615 update_dirty spc,ptp,pte,t1
1617 make_insert_tlb spc,pte,prot
1628 .import handle_interruption,code
1632 ldi 31,%r8 /* Use an unused code */
1654 /* Register saving semantics for system calls:
1656 %r1 clobbered by system call macro in userspace
1657 %r2 saved in PT_REGS by gateway page
1658 %r3 - %r18 preserved by C code (saved by signal code)
1659 %r19 - %r20 saved in PT_REGS by gateway page
1660 %r21 - %r22 non-standard syscall args
1661 stored in kernel stack by gateway page
1662 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1663 %r27 - %r30 saved in PT_REGS by gateway page
1664 %r31 syscall return pointer
1667 /* Floating point registers (FIXME: what do we do with these?)
1669 %fr0 - %fr3 status/exception, not preserved
1670 %fr4 - %fr7 arguments
1671 %fr8 - %fr11 not preserved by C code
1672 %fr12 - %fr21 preserved by C code
1673 %fr22 - %fr31 not preserved by C code
1676 .macro reg_save regs
1677 STREG %r3, PT_GR3(\regs)
1678 STREG %r4, PT_GR4(\regs)
1679 STREG %r5, PT_GR5(\regs)
1680 STREG %r6, PT_GR6(\regs)
1681 STREG %r7, PT_GR7(\regs)
1682 STREG %r8, PT_GR8(\regs)
1683 STREG %r9, PT_GR9(\regs)
1684 STREG %r10,PT_GR10(\regs)
1685 STREG %r11,PT_GR11(\regs)
1686 STREG %r12,PT_GR12(\regs)
1687 STREG %r13,PT_GR13(\regs)
1688 STREG %r14,PT_GR14(\regs)
1689 STREG %r15,PT_GR15(\regs)
1690 STREG %r16,PT_GR16(\regs)
1691 STREG %r17,PT_GR17(\regs)
1692 STREG %r18,PT_GR18(\regs)
1695 .macro reg_restore regs
1696 LDREG PT_GR3(\regs), %r3
1697 LDREG PT_GR4(\regs), %r4
1698 LDREG PT_GR5(\regs), %r5
1699 LDREG PT_GR6(\regs), %r6
1700 LDREG PT_GR7(\regs), %r7
1701 LDREG PT_GR8(\regs), %r8
1702 LDREG PT_GR9(\regs), %r9
1703 LDREG PT_GR10(\regs),%r10
1704 LDREG PT_GR11(\regs),%r11
1705 LDREG PT_GR12(\regs),%r12
1706 LDREG PT_GR13(\regs),%r13
1707 LDREG PT_GR14(\regs),%r14
1708 LDREG PT_GR15(\regs),%r15
1709 LDREG PT_GR16(\regs),%r16
1710 LDREG PT_GR17(\regs),%r17
1711 LDREG PT_GR18(\regs),%r18
1714 .macro fork_like name
1715 ENTRY(sys_\name\()_wrapper)
1716 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1717 ldo TASK_REGS(%r1),%r1
1720 ldil L%sys_\name, %r31
1721 be R%sys_\name(%sr4,%r31)
1722 STREG %r28, PT_CR27(%r1)
1723 ENDPROC(sys_\name\()_wrapper)
1730 /* Set the return value for the child */
1732 BL schedule_tail, %r2
1734 finish_child_return:
1735 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1736 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1738 LDREG PT_CR27(%r1), %r3
1743 ENDPROC(child_return)
1745 ENTRY(sys_rt_sigreturn_wrapper)
1746 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1747 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1748 /* Don't save regs, we are going to restore them from sigcontext. */
1749 STREG %r2, -RP_OFFSET(%r30)
1751 ldo FRAME_SIZE(%r30), %r30
1752 BL sys_rt_sigreturn,%r2
1753 ldo -16(%r30),%r29 /* Reference param save area */
1755 BL sys_rt_sigreturn,%r2
1756 ldo FRAME_SIZE(%r30), %r30
1759 ldo -FRAME_SIZE(%r30), %r30
1760 LDREG -RP_OFFSET(%r30), %r2
1762 /* FIXME: I think we need to restore a few more things here. */
1763 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1764 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1767 /* If the signal was received while the process was blocked on a
1768 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1769 * take us to syscall_exit_rfi and on to intr_return.
1772 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1773 ENDPROC(sys_rt_sigreturn_wrapper)
1776 /* NOTE: HP-UX syscalls also come through here
1777 * after hpux_syscall_exit fixes up return
1780 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
1781 * via syscall_exit_rfi if the signal was received while the process
1785 /* save return value now */
1788 LDREG TI_TASK(%r1),%r1
1789 STREG %r28,TASK_PT_GR28(%r1)
1792 /* <linux/personality.h> cannot be easily included */
1793 #define PER_HPUX 0x10
1794 ldw TASK_PERSONALITY(%r1),%r19
1796 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
1797 ldo -PER_HPUX(%r19), %r19
1798 cmpib,COND(<>),n 0,%r19,1f
1800 /* Save other hpux returns if personality is PER_HPUX */
1801 STREG %r22,TASK_PT_GR22(%r1)
1802 STREG %r29,TASK_PT_GR29(%r1)
1805 #endif /* CONFIG_HPUX */
1807 /* Seems to me that dp could be wrong here, if the syscall involved
1808 * calling a module, and nothing got round to restoring dp on return.
1812 syscall_check_resched:
1814 /* check for reschedule */
1816 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
1817 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
1819 .import do_signal,code
1821 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1822 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r26
1823 and,COND(<>) %r19, %r26, %r0
1824 b,n syscall_restore /* skip past if we've nothing to do */
1827 /* Save callee-save registers (for sigcontext).
1828 * FIXME: After this point the process structure should be
1829 * consistent with all the relevant state of the process
1830 * before the syscall. We need to verify this.
1832 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1833 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
1837 ldo -16(%r30),%r29 /* Reference param save area */
1840 BL do_notify_resume,%r2
1841 ldi 1, %r25 /* long in_syscall = 1 */
1843 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1844 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
1847 b,n syscall_check_sig
1850 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1852 /* Are we being ptraced? */
1853 ldw TASK_FLAGS(%r1),%r19
1854 ldi _TIF_SYSCALL_TRACE_MASK,%r2
1855 and,COND(=) %r19,%r2,%r0
1856 b,n syscall_restore_rfi
1858 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
1861 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
1864 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
1865 LDREG TASK_PT_GR19(%r1),%r19
1866 LDREG TASK_PT_GR20(%r1),%r20
1867 LDREG TASK_PT_GR21(%r1),%r21
1868 LDREG TASK_PT_GR22(%r1),%r22
1869 LDREG TASK_PT_GR23(%r1),%r23
1870 LDREG TASK_PT_GR24(%r1),%r24
1871 LDREG TASK_PT_GR25(%r1),%r25
1872 LDREG TASK_PT_GR26(%r1),%r26
1873 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
1874 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
1875 LDREG TASK_PT_GR29(%r1),%r29
1876 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
1878 /* NOTE: We use rsm/ssm pair to make this operation atomic */
1879 LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
1881 copy %r1,%r30 /* Restore user sp */
1882 mfsp %sr3,%r1 /* Get user space id */
1883 mtsp %r1,%sr7 /* Restore sr7 */
1886 /* Set sr2 to zero for userspace syscalls to work. */
1888 mtsp %r1,%sr4 /* Restore sr4 */
1889 mtsp %r1,%sr5 /* Restore sr5 */
1890 mtsp %r1,%sr6 /* Restore sr6 */
1892 depi 3,31,2,%r31 /* ensure return to user mode. */
1895 /* decide whether to reset the wide mode bit
1897 * For a syscall, the W bit is stored in the lowest bit
1898 * of sp. Extract it and reset W if it is zero */
1899 extrd,u,*<> %r30,63,1,%r1
1901 /* now reset the lowest bit of sp if it was set */
1904 be,n 0(%sr3,%r31) /* return to user space */
1906 /* We have to return via an RFI, so that PSW T and R bits can be set
1908 * This sets up pt_regs so we can return via intr_restore, which is not
1909 * the most efficient way of doing things, but it works.
1911 syscall_restore_rfi:
1912 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
1913 mtctl %r2,%cr0 /* for immediate trap */
1914 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
1915 ldi 0x0b,%r20 /* Create new PSW */
1916 depi -1,13,1,%r20 /* C, Q, D, and I bits */
1918 /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
1919 * set in thread_info.h and converted to PA bitmap
1920 * numbers in asm-offsets.c */
1922 /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
1923 extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
1924 depi -1,27,1,%r20 /* R bit */
1926 /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
1927 extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
1928 depi -1,7,1,%r20 /* T bit */
1930 STREG %r20,TASK_PT_PSW(%r1)
1932 /* Always store space registers, since sr3 can be changed (e.g. fork) */
1935 STREG %r25,TASK_PT_SR3(%r1)
1936 STREG %r25,TASK_PT_SR4(%r1)
1937 STREG %r25,TASK_PT_SR5(%r1)
1938 STREG %r25,TASK_PT_SR6(%r1)
1939 STREG %r25,TASK_PT_SR7(%r1)
1940 STREG %r25,TASK_PT_IASQ0(%r1)
1941 STREG %r25,TASK_PT_IASQ1(%r1)
1944 /* Now if old D bit is clear, it means we didn't save all registers
1945 * on syscall entry, so do that now. This only happens on TRACEME
1946 * calls, or if someone attached to us while we were on a syscall.
1947 * We could make this more efficient by not saving r3-r18, but
1948 * then we wouldn't be able to use the common intr_restore path.
1949 * It is only for traced processes anyway, so performance is not
1952 bb,< %r2,30,pt_regs_ok /* Branch if D set */
1953 ldo TASK_REGS(%r1),%r25
1954 reg_save %r25 /* Save r3 to r18 */
1956 /* Save the current sr */
1958 STREG %r2,TASK_PT_SR0(%r1)
1960 /* Save the scratch sr */
1962 STREG %r2,TASK_PT_SR1(%r1)
1964 /* sr2 should be set to zero for userspace syscalls */
1965 STREG %r0,TASK_PT_SR2(%r1)
1967 LDREG TASK_PT_GR31(%r1),%r2
1968 depi 3,31,2,%r2 /* ensure return to user mode. */
1969 STREG %r2,TASK_PT_IAOQ0(%r1)
1971 STREG %r2,TASK_PT_IAOQ1(%r1)
1976 LDREG TASK_PT_IAOQ0(%r1),%r2
1977 depi 3,31,2,%r2 /* ensure return to user mode. */
1978 STREG %r2,TASK_PT_IAOQ0(%r1)
1979 LDREG TASK_PT_IAOQ1(%r1),%r2
1981 STREG %r2,TASK_PT_IAOQ1(%r1)
1985 .import schedule,code
1989 ldo -16(%r30),%r29 /* Reference param save area */
1993 b syscall_check_resched /* if resched, we start over again */
1995 ENDPROC(syscall_exit)
1998 #ifdef CONFIG_FUNCTION_TRACER
1999 .import ftrace_function_trampoline,code
2002 b ftrace_function_trampoline
2006 ENTRY(return_to_handler)
2007 load32 return_trampoline, %rp
2010 b ftrace_return_to_handler
2021 ENDPROC(return_to_handler)
2022 #endif /* CONFIG_FUNCTION_TRACER */
2024 #ifdef CONFIG_IRQSTACKS
2025 /* void call_on_stack(unsigned long param1, void *func,
2026 unsigned long new_stack) */
2027 ENTRY(call_on_stack)
2030 /* Regarding the HPPA calling conventions for function pointers,
2031 we assume the PIC register is not changed across call. For
2032 CONFIG_64BIT, the argument pointer is left to point at the
2033 argument region allocated for the call to call_on_stack. */
2034 # ifdef CONFIG_64BIT
2035 /* Switch to new stack. We allocate two 128 byte frames. */
2037 /* Save previous stack pointer and return pointer in frame marker */
2038 STREG %rp, -144(%sp)
2039 /* Calls always use function descriptor */
2040 LDREG 16(%arg1), %arg1
2042 STREG %r1, -136(%sp)
2043 LDREG -144(%sp), %rp
2045 LDREG -136(%sp), %sp
2047 /* Switch to new stack. We allocate two 64 byte frames. */
2049 /* Save previous stack pointer and return pointer in frame marker */
2052 /* Calls use function descriptor if PLABEL bit is set */
2053 bb,>=,n %arg1, 30, 1f
2055 LDREG 0(%arg1), %arg1
2057 be,l 0(%sr4,%arg1), %sr0, %r31
2062 # endif /* CONFIG_64BIT */
2063 ENDPROC(call_on_stack)
2064 #endif /* CONFIG_IRQSTACKS */
2068 * get_register is used by the non access tlb miss handlers to
2069 * copy the value of the general register specified in r8 into
2070 * r1. This routine can't be used for shadowed registers, since
2071 * the rfir will restore the original value. So, for the shadowed
2072 * registers we put a -1 into r1 to indicate that the register
2073 * should not be used (the register being copied could also have
2074 * a -1 in it, but that is OK, it just means that we will have
2075 * to use the slow path instead).
2079 bv %r0(%r25) /* r0 */
2081 bv %r0(%r25) /* r1 - shadowed */
2083 bv %r0(%r25) /* r2 */
2085 bv %r0(%r25) /* r3 */
2087 bv %r0(%r25) /* r4 */
2089 bv %r0(%r25) /* r5 */
2091 bv %r0(%r25) /* r6 */
2093 bv %r0(%r25) /* r7 */
2095 bv %r0(%r25) /* r8 - shadowed */
2097 bv %r0(%r25) /* r9 - shadowed */
2099 bv %r0(%r25) /* r10 */
2101 bv %r0(%r25) /* r11 */
2103 bv %r0(%r25) /* r12 */
2105 bv %r0(%r25) /* r13 */
2107 bv %r0(%r25) /* r14 */
2109 bv %r0(%r25) /* r15 */
2111 bv %r0(%r25) /* r16 - shadowed */
2113 bv %r0(%r25) /* r17 - shadowed */
2115 bv %r0(%r25) /* r18 */
2117 bv %r0(%r25) /* r19 */
2119 bv %r0(%r25) /* r20 */
2121 bv %r0(%r25) /* r21 */
2123 bv %r0(%r25) /* r22 */
2125 bv %r0(%r25) /* r23 */
2127 bv %r0(%r25) /* r24 - shadowed */
2129 bv %r0(%r25) /* r25 - shadowed */
2131 bv %r0(%r25) /* r26 */
2133 bv %r0(%r25) /* r27 */
2135 bv %r0(%r25) /* r28 */
2137 bv %r0(%r25) /* r29 */
2139 bv %r0(%r25) /* r30 */
2141 bv %r0(%r25) /* r31 */
2147 * set_register is used by the non access tlb miss handlers to
2148 * copy the value of r1 into the general register specified in
2153 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2155 bv %r0(%r25) /* r1 */
2157 bv %r0(%r25) /* r2 */
2159 bv %r0(%r25) /* r3 */
2161 bv %r0(%r25) /* r4 */
2163 bv %r0(%r25) /* r5 */
2165 bv %r0(%r25) /* r6 */
2167 bv %r0(%r25) /* r7 */
2169 bv %r0(%r25) /* r8 */
2171 bv %r0(%r25) /* r9 */
2173 bv %r0(%r25) /* r10 */
2175 bv %r0(%r25) /* r11 */
2177 bv %r0(%r25) /* r12 */
2179 bv %r0(%r25) /* r13 */
2181 bv %r0(%r25) /* r14 */
2183 bv %r0(%r25) /* r15 */
2185 bv %r0(%r25) /* r16 */
2187 bv %r0(%r25) /* r17 */
2189 bv %r0(%r25) /* r18 */
2191 bv %r0(%r25) /* r19 */
2193 bv %r0(%r25) /* r20 */
2195 bv %r0(%r25) /* r21 */
2197 bv %r0(%r25) /* r22 */
2199 bv %r0(%r25) /* r23 */
2201 bv %r0(%r25) /* r24 */
2203 bv %r0(%r25) /* r25 */
2205 bv %r0(%r25) /* r26 */
2207 bv %r0(%r25) /* r27 */
2209 bv %r0(%r25) /* r28 */
2211 bv %r0(%r25) /* r29 */
2213 bv %r0(%r25) /* r30 */
2215 bv %r0(%r25) /* r31 */