1 #ifndef _ASM_POWERPC_BOOK3S_32_PGTABLE_H
2 #define _ASM_POWERPC_BOOK3S_32_PGTABLE_H
4 #include <asm-generic/pgtable-nopmd.h>
6 #include <asm/book3s/32/hash.h>
8 /* And here we include common definitions */
9 #include <asm/pte-common.h>
12 * The normal case is that PTEs are 32-bits and we have a 1-page
13 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
15 * For any >32-bit physical address platform, we can use the following
16 * two level page table layout where the pgdir is 8KB and the MS 13 bits
17 * are an index to the second level table. The combined pgdir/pmd first
18 * level has 2048 entries and the second level has 512 64-bit PTE entries.
21 /* PGDIR_SHIFT determines what a top-level page table entry can map */
22 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
23 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
24 #define PGDIR_MASK (~(PGDIR_SIZE-1))
26 #define PTRS_PER_PTE (1 << PTE_SHIFT)
27 #define PTRS_PER_PMD 1
28 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
30 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
32 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
33 * value (for now) on others, from where we can start layout kernel
34 * virtual space that goes below PKMAP and FIXMAP
37 #define KVIRT_TOP PKMAP_BASE
39 #define KVIRT_TOP (0xfe000000UL) /* for now, could be FIXMAP_BASE ? */
43 * ioremap_bot starts at that address. Early ioremaps move down from there,
44 * until mem_init() at which point this becomes the top of the vmalloc
47 #ifdef CONFIG_NOT_COHERENT_CACHE
48 #define IOREMAP_TOP ((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
50 #define IOREMAP_TOP KVIRT_TOP
54 * Just any arbitrary offset to the start of the vmalloc VM area: the
55 * current 16MB value just means that there will be a 64MB "hole" after the
56 * physical memory until the kernel virtual memory starts. That means that
57 * any out-of-bounds memory accesses will hopefully be caught.
58 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
59 * area for the same reason. ;)
61 * We no longer map larger than phys RAM with the BATs so we don't have
62 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
63 * about clashes between our early calls to ioremap() that start growing down
64 * from ioremap_base being run into the VM area allocations (growing upwards
65 * from VMALLOC_START). For this reason we have ioremap_bot to check when
66 * we actually run into our mappings setup in the early boot with the VM
67 * system. This really does become a problem for machines with good amounts
70 #define VMALLOC_OFFSET (0x1000000) /* 16M */
72 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
74 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
76 #define VMALLOC_END ioremap_bot
79 #include <linux/sched.h>
80 #include <linux/threads.h>
81 #include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
83 extern unsigned long ioremap_bot;
86 * entries per page directory level: our page-table tree is two-level, so
87 * we don't really have any PMD directory.
89 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
90 #define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
92 #define pte_ERROR(e) \
93 pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
94 (unsigned long long)pte_val(e))
95 #define pgd_ERROR(e) \
96 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
98 * Bits in a linux-style PTE. These match the bits in the
99 * (hardware-defined) PowerPC PTE as closely as possible.
102 #define pte_clear(mm, addr, ptep) \
103 do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
105 #define pmd_none(pmd) (!pmd_val(pmd))
106 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
107 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
108 static inline void pmd_clear(pmd_t *pmdp)
115 * When flushing the tlb entry for a page, we also need to flush the hash
116 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
118 extern int flush_hash_pages(unsigned context, unsigned long va,
119 unsigned long pmdval, int count);
121 /* Add an HPTE to the hash table */
122 extern void add_hash_page(unsigned context, unsigned long va,
123 unsigned long pmdval);
125 /* Flush an entry from the TLB/hash table */
126 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
127 unsigned long address);
130 * PTE updates. This function is called whenever an existing
131 * valid PTE is updated. This does -not- include set_pte_at()
132 * which nowadays only sets a new PTE.
134 * Depending on the type of MMU, we may need to use atomic updates
135 * and the PTE may be either 32 or 64 bit wide. In the later case,
136 * when using atomic updates, only the low part of the PTE is
137 * accessed atomically.
139 * In addition, on 44x, we also maintain a global flag indicating
140 * that an executable user mapping was modified, which is needed
141 * to properly flush the virtually tagged instruction cache of
142 * those implementations.
144 #ifndef CONFIG_PTE_64BIT
145 static inline unsigned long pte_update(pte_t *p,
149 unsigned long old, tmp;
151 __asm__ __volatile__("\
158 : "=&r" (old), "=&r" (tmp), "=m" (*p)
159 : "r" (p), "r" (clr), "r" (set), "m" (*p)
164 #else /* CONFIG_PTE_64BIT */
165 static inline unsigned long long pte_update(pte_t *p,
169 unsigned long long old;
172 __asm__ __volatile__("\
180 : "=&r" (old), "=&r" (tmp), "=m" (*p)
181 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
186 #endif /* CONFIG_PTE_64BIT */
189 * 2.6 calls this without flushing the TLB entry; this is wrong
190 * for our hash-based implementation, we fix that up here.
192 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
193 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
196 old = pte_update(ptep, _PAGE_ACCESSED, 0);
197 if (old & _PAGE_HASHPTE) {
198 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
199 flush_hash_pages(context, addr, ptephys, 1);
201 return (old & _PAGE_ACCESSED) != 0;
203 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
204 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
206 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
207 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
210 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
213 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
214 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
217 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), _PAGE_RO);
219 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
220 unsigned long addr, pte_t *ptep)
222 ptep_set_wrprotect(mm, addr, ptep);
226 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
228 unsigned long set = pte_val(entry) &
229 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
230 unsigned long clr = ~pte_val(entry) & _PAGE_RO;
232 pte_update(ptep, clr, set);
235 #define __HAVE_ARCH_PTE_SAME
236 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
239 * Note that on Book E processors, the pmd contains the kernel virtual
240 * (lowmem) address of the pte page. The physical address is less useful
241 * because everything runs with translation enabled (even the TLB miss
242 * handler). On everything else the pmd contains the physical address
243 * of the pte page. -- paulus
246 #define pmd_page_vaddr(pmd) \
247 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
248 #define pmd_page(pmd) \
249 pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
251 #define pmd_page_vaddr(pmd) \
252 ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
253 #define pmd_page(pmd) \
254 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
257 /* to find an entry in a kernel page-table-directory */
258 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
260 /* to find an entry in a page-table-directory */
261 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
262 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
264 /* Find an entry in the third-level page table.. */
265 #define pte_index(address) \
266 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
267 #define pte_offset_kernel(dir, addr) \
268 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
269 #define pte_offset_map(dir, addr) \
270 ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
271 #define pte_unmap(pte) kunmap_atomic(pte)
274 * Encode and decode a swap entry.
275 * Note that the bits we use in a PTE for representing a swap entry
276 * must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used).
279 #define __swp_type(entry) ((entry).val & 0x1f)
280 #define __swp_offset(entry) ((entry).val >> 5)
281 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
282 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
283 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
285 #ifndef CONFIG_PPC_4K_PAGES
286 void pgtable_cache_init(void);
289 * No page table caches to initialise
291 #define pgtable_cache_init() do { } while (0)
294 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
297 /* Generic accessors to PTE bits */
298 static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);}
299 static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
300 static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
301 static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
302 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
303 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
305 static inline int pte_present(pte_t pte)
307 return pte_val(pte) & _PAGE_PRESENT;
310 /* Conversion functions: convert a page and protection to a page entry,
311 * and a page entry and page directory to the page they refer to.
313 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
316 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
318 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
322 static inline unsigned long pte_pfn(pte_t pte)
324 return pte_val(pte) >> PTE_RPN_SHIFT;
327 /* Generic modifiers for PTE bits */
328 static inline pte_t pte_wrprotect(pte_t pte)
330 return __pte(pte_val(pte) & ~_PAGE_RW);
333 static inline pte_t pte_mkclean(pte_t pte)
335 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
338 static inline pte_t pte_mkold(pte_t pte)
340 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
343 static inline pte_t pte_mkwrite(pte_t pte)
345 return __pte(pte_val(pte) | _PAGE_RW);
348 static inline pte_t pte_mkdirty(pte_t pte)
350 return __pte(pte_val(pte) | _PAGE_DIRTY);
353 static inline pte_t pte_mkyoung(pte_t pte)
355 return __pte(pte_val(pte) | _PAGE_ACCESSED);
358 static inline pte_t pte_mkspecial(pte_t pte)
360 return __pte(pte_val(pte) | _PAGE_SPECIAL);
363 static inline pte_t pte_mkhuge(pte_t pte)
368 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
370 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
375 /* This low level function performs the actual PTE insertion
376 * Setting the PTE depends on the MMU type and other factors. It's
377 * an horrible mess that I'm not going to try to clean up now but
378 * I'm keeping it in one place rather than spread around
380 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
381 pte_t *ptep, pte_t pte, int percpu)
383 #if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
384 /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
385 * helper pte_update() which does an atomic update. We need to do that
386 * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
387 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving
388 * the hash bits instead (ie, same as the non-SMP case)
391 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
392 | (pte_val(pte) & ~_PAGE_HASHPTE));
394 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
396 #elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
397 /* Second case is 32-bit with 64-bit PTE. In this case, we
398 * can just store as long as we do the two halves in the right order
399 * with a barrier in between. This is possible because we take care,
400 * in the hash code, to pre-invalidate if the PTE was already hashed,
401 * which synchronizes us with any concurrent invalidation.
402 * In the percpu case, we also fallback to the simple update preserving
406 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
407 | (pte_val(pte) & ~_PAGE_HASHPTE));
410 if (pte_val(*ptep) & _PAGE_HASHPTE)
411 flush_hash_entry(mm, ptep, addr);
412 __asm__ __volatile__("\
416 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
417 : "r" (pte) : "memory");
419 #elif defined(CONFIG_PPC_STD_MMU_32)
420 /* Third case is 32-bit hash table in UP mode, we need to preserve
421 * the _PAGE_HASHPTE bit since we may not have invalidated the previous
422 * translation in the hash yet (done in a subsequent flush_tlb_xxx())
423 * and see we need to keep track that this PTE needs invalidating
425 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
426 | (pte_val(pte) & ~_PAGE_HASHPTE));
429 #error "Not supported "
434 * Macro to mark a page protection value as "uncacheable".
437 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
440 #define pgprot_noncached pgprot_noncached
441 static inline pgprot_t pgprot_noncached(pgprot_t prot)
443 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
444 _PAGE_NO_CACHE | _PAGE_GUARDED);
447 #define pgprot_noncached_wc pgprot_noncached_wc
448 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
450 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
454 #define pgprot_cached pgprot_cached
455 static inline pgprot_t pgprot_cached(pgprot_t prot)
457 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
461 #define pgprot_cached_wthru pgprot_cached_wthru
462 static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)
464 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
465 _PAGE_COHERENT | _PAGE_WRITETHRU);
468 #define pgprot_cached_noncoherent pgprot_cached_noncoherent
469 static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)
471 return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);
474 #define pgprot_writecombine pgprot_writecombine
475 static inline pgprot_t pgprot_writecombine(pgprot_t prot)
477 return pgprot_noncached_wc(prot);
480 #endif /* !__ASSEMBLY__ */
482 #endif /* _ASM_POWERPC_BOOK3S_32_PGTABLE_H */