1 #ifndef _ASM_POWERPC_MMU_H_
2 #define _ASM_POWERPC_MMU_H_
5 #include <linux/types.h>
7 #include <asm/asm-compat.h>
8 #include <asm/feature-fixups.h>
11 * MMU features bit definitions
17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
19 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
20 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
21 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
22 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
24 /* Radix page table supported and enabled */
25 #define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
28 * Individual features below.
32 * We need to clear top 16bits of va (from the remaining 64 bits )in
35 #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
37 /* Enable use of high BAT registers */
38 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
40 /* Enable >32-bit physical addresses on 32-bit processor, only used
41 * by CONFIG_6xx currently as BookE supports that from day 1
43 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
45 /* Enable use of broadcast TLB invalidations. We don't always set it
46 * on processors that support it due to other constraints with the
47 * use of such invalidations
49 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
51 /* Enable use of tlbilx invalidate instructions.
53 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
55 /* This indicates that the processor cannot handle multiple outstanding
56 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
57 * around such invalidate forms.
59 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
61 /* This indicates that the processor doesn't handle way selection
62 * properly and needs SW to track and update the LRU state. This
63 * is specific to an errata on e300c2/c3/c4 class parts
65 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
67 /* Enable use of TLB reservation. Processor should support tlbsrx.
68 * instruction and MAS0[WQ].
70 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
72 /* Use paired MAS registers (MAS7||MAS3, etc.)
74 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
76 /* Doesn't support the B bit (1T segment) in SLBIE
78 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
80 /* Support 16M large pages
82 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
84 /* Supports TLBIEL variant
86 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
88 /* Supports tlbies w/o locking
90 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
92 /* Large pages can be marked CI
94 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
96 /* 1T segments available
98 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
100 /* MMU feature bit sets for various CPUs */
101 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
102 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
103 #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
104 #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA
105 #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
106 #define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
107 #define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
108 #define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
109 #define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
110 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
111 MMU_FTR_CI_LARGE_PAGE
112 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
113 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
115 #include <asm/cputable.h>
117 #ifdef CONFIG_PPC_FSL_BOOK3E
118 #include <asm/percpu.h>
119 DECLARE_PER_CPU(int, next_tlbcam_idx);
123 MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx |
124 MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E |
125 MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS |
126 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX |
127 MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU |
128 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
129 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
130 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
131 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
132 #ifdef CONFIG_PPC_RADIX_MMU
138 static inline bool mmu_has_feature(unsigned long feature)
140 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
143 static inline void mmu_clear_feature(unsigned long feature)
145 cur_cpu_spec->mmu_features &= ~feature;
148 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
151 /* This is our real memory area size on ppc64 server, on embedded, we
152 * make it match the size our of bolted TLB area
154 extern u64 ppc64_rma_size;
155 #endif /* CONFIG_PPC64 */
158 #ifdef CONFIG_DEBUG_VM
159 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
160 #else /* CONFIG_DEBUG_VM */
161 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
164 #endif /* !CONFIG_DEBUG_VM */
166 #endif /* !__ASSEMBLY__ */
168 /* The kernel use the constants below to index in the page sizes array.
169 * The use of fixed constants for this purpose is better for performances
170 * of the low level hash refill handlers.
172 * A non supported page size has a "shift" field set to 0
174 * Any new page size being implemented can get a new entry in here. Whether
175 * the kernel will use it or not is a different matter though. The actual page
176 * size used by hugetlbfs is not defined here and may be made variable
178 * Note: This array ended up being a false good idea as it's growing to the
179 * point where I wonder if we should replace it with something different,
180 * to think about, feedback welcome. --BenH.
183 /* These are #defines as they have to be used in assembly */
184 #define MMU_PAGE_4K 0
185 #define MMU_PAGE_16K 1
186 #define MMU_PAGE_64K 2
187 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
188 #define MMU_PAGE_256K 4
189 #define MMU_PAGE_1M 5
190 #define MMU_PAGE_2M 6
191 #define MMU_PAGE_4M 7
192 #define MMU_PAGE_8M 8
193 #define MMU_PAGE_16M 9
194 #define MMU_PAGE_64M 10
195 #define MMU_PAGE_256M 11
196 #define MMU_PAGE_1G 12
197 #define MMU_PAGE_16G 13
198 #define MMU_PAGE_64G 14
200 #define MMU_PAGE_COUNT 15
202 #ifdef CONFIG_PPC_BOOK3S_64
203 #include <asm/book3s/64/mmu.h>
204 #else /* CONFIG_PPC_BOOK3S_64 */
207 /* MMU initialization */
208 extern void early_init_mmu(void);
209 extern void early_init_mmu_secondary(void);
210 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
211 phys_addr_t first_memblock_size);
212 static inline void mmu_early_init_devtree(void) { }
213 #endif /* __ASSEMBLY__ */
216 #if defined(CONFIG_PPC_STD_MMU_32)
217 /* 32-bit classic hash table MMU */
218 #include <asm/book3s/32/mmu-hash.h>
219 #elif defined(CONFIG_40x)
220 /* 40x-style software loaded TLB */
221 # include <asm/mmu-40x.h>
222 #elif defined(CONFIG_44x)
223 /* 44x-style software loaded TLB */
224 # include <asm/mmu-44x.h>
225 #elif defined(CONFIG_PPC_BOOK3E_MMU)
226 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
227 # include <asm/mmu-book3e.h>
228 #elif defined (CONFIG_PPC_8xx)
229 /* Motorola/Freescale 8xx software loaded TLB */
230 # include <asm/mmu-8xx.h>
233 #ifndef radix_enabled
234 #define radix_enabled() (0)
237 #endif /* __KERNEL__ */
238 #endif /* _ASM_POWERPC_MMU_H_ */