arch/powerpc/include/asm/opal.h

   1 /*
   2  * PowerNV OPAL definitions.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_H
  13 #define __OPAL_H
  14
  15 #ifndef __ASSEMBLY__
  16 /*
  17  * SG entry
  18  *
  19  * WARNING: The current implementation requires each entry
  20  * to represent a block that is 4k aligned *and* each block
  21  * size except the last one in the list to be as well.
  22  */
  23 struct opal_sg_entry {
  24         __be64 data;
  25         __be64 length;
  26 };
  27
  28 /* SG list */
  29 struct opal_sg_list {
  30         __be64 length;
  31         __be64 next;
  32         struct opal_sg_entry entry[];
  33 };
  34
  35 /* We calculate number of sg entries based on PAGE_SIZE */
  36 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
  37
  38 #endif /* __ASSEMBLY__ */
  39
  40 /****** OPAL APIs ******/
  41
  42 /* Return codes */
  43 #define OPAL_SUCCESS            0
  44 #define OPAL_PARAMETER          -1
  45 #define OPAL_BUSY               -2
  46 #define OPAL_PARTIAL            -3
  47 #define OPAL_CONSTRAINED        -4
  48 #define OPAL_CLOSED             -5
  49 #define OPAL_HARDWARE           -6
  50 #define OPAL_UNSUPPORTED        -7
  51 #define OPAL_PERMISSION         -8
  52 #define OPAL_NO_MEM             -9
  53 #define OPAL_RESOURCE           -10
  54 #define OPAL_INTERNAL_ERROR     -11
  55 #define OPAL_BUSY_EVENT         -12
  56 #define OPAL_HARDWARE_FROZEN    -13
  57 #define OPAL_WRONG_STATE        -14
  58 #define OPAL_ASYNC_COMPLETION   -15
  59
  60 /* API Tokens (in r0) */
  61 #define OPAL_INVALID_CALL                       -1
  62 #define OPAL_CONSOLE_WRITE                      1
  63 #define OPAL_CONSOLE_READ                       2
  64 #define OPAL_RTC_READ                           3
  65 #define OPAL_RTC_WRITE                          4
  66 #define OPAL_CEC_POWER_DOWN                     5
  67 #define OPAL_CEC_REBOOT                         6
  68 #define OPAL_READ_NVRAM                         7
  69 #define OPAL_WRITE_NVRAM                        8
  70 #define OPAL_HANDLE_INTERRUPT                   9
  71 #define OPAL_POLL_EVENTS                        10
  72 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  73 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  74 #define OPAL_PCI_CONFIG_READ_BYTE               13
  75 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  76 #define OPAL_PCI_CONFIG_READ_WORD               15
  77 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  78 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  79 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  80 #define OPAL_SET_XIVE                           19
  81 #define OPAL_GET_XIVE                           20
  82 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  83 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  84 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  85 #define OPAL_PCI_SHPC                           24
  86 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  87 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  88 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  89 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  90 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  91 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  92 #define OPAL_PCI_SET_PE                         31
  93 #define OPAL_PCI_SET_PELTV                      32
  94 #define OPAL_PCI_SET_MVE                        33
  95 #define OPAL_PCI_SET_MVE_ENABLE                 34
  96 #define OPAL_PCI_GET_XIVE_REISSUE               35
  97 #define OPAL_PCI_SET_XIVE_REISSUE               36
  98 #define OPAL_PCI_SET_XIVE_PE                    37
  99 #define OPAL_GET_XIVE_SOURCE                    38
 100 #define OPAL_GET_MSI_32                         39
 101 #define OPAL_GET_MSI_64                         40
 102 #define OPAL_START_CPU                          41
 103 #define OPAL_QUERY_CPU_STATUS                   42
 104 #define OPAL_WRITE_OPPANEL                      43
 105 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 106 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 107 #define OPAL_PCI_RESET                          49
 108 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
 109 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
 110 #define OPAL_PCI_FENCE_PHB                      52
 111 #define OPAL_PCI_REINIT                         53
 112 #define OPAL_PCI_MASK_PE_ERROR                  54
 113 #define OPAL_SET_SLOT_LED_STATUS                55
 114 #define OPAL_GET_EPOW_STATUS                    56
 115 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 116 #define OPAL_RESERVED1                          58
 117 #define OPAL_RESERVED2                          59
 118 #define OPAL_PCI_NEXT_ERROR                     60
 119 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 120 #define OPAL_PCI_POLL                           62
 121 #define OPAL_PCI_MSI_EOI                        63
 122 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 123 #define OPAL_XSCOM_READ                         65
 124 #define OPAL_XSCOM_WRITE                        66
 125 #define OPAL_LPC_READ                           67
 126 #define OPAL_LPC_WRITE                          68
 127 #define OPAL_RETURN_CPU                         69
 128 #define OPAL_REINIT_CPUS                        70
 129 #define OPAL_ELOG_READ                          71
 130 #define OPAL_ELOG_WRITE                         72
 131 #define OPAL_ELOG_ACK                           73
 132 #define OPAL_ELOG_RESEND                        74
 133 #define OPAL_ELOG_SIZE                          75
 134 #define OPAL_FLASH_VALIDATE                     76
 135 #define OPAL_FLASH_MANAGE                       77
 136 #define OPAL_FLASH_UPDATE                       78
 137 #define OPAL_RESYNC_TIMEBASE                    79
 138 #define OPAL_DUMP_INIT                          81
 139 #define OPAL_DUMP_INFO                          82
 140 #define OPAL_DUMP_READ                          83
 141 #define OPAL_DUMP_ACK                           84
 142 #define OPAL_GET_MSG                            85
 143 #define OPAL_CHECK_ASYNC_COMPLETION             86
 144 #define OPAL_SYNC_HOST_REBOOT                   87
 145 #define OPAL_SENSOR_READ                        88
 146 #define OPAL_GET_PARAM                          89
 147 #define OPAL_SET_PARAM                          90
 148 #define OPAL_DUMP_RESEND                        91
 149 #define OPAL_DUMP_INFO2                         94
 150
 151 #ifndef __ASSEMBLY__
 152
 153 #include <linux/notifier.h>
 154
 155 /* Other enums */
 156 enum OpalVendorApiTokens {
 157         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 158 };
 159
 160 enum OpalFreezeState {
 161         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 162         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 163         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 164         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 165         OPAL_EEH_STOPPED_RESET = 4,
 166         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 167         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 168 };
 169
 170 enum OpalEehFreezeActionToken {
 171         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 172         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 173         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
 174 };
 175
 176 enum OpalPciStatusToken {
 177         OPAL_EEH_NO_ERROR       = 0,
 178         OPAL_EEH_IOC_ERROR      = 1,
 179         OPAL_EEH_PHB_ERROR      = 2,
 180         OPAL_EEH_PE_ERROR       = 3,
 181         OPAL_EEH_PE_MMIO_ERROR  = 4,
 182         OPAL_EEH_PE_DMA_ERROR   = 5
 183 };
 184
 185 enum OpalPciErrorSeverity {
 186         OPAL_EEH_SEV_NO_ERROR   = 0,
 187         OPAL_EEH_SEV_IOC_DEAD   = 1,
 188         OPAL_EEH_SEV_PHB_DEAD   = 2,
 189         OPAL_EEH_SEV_PHB_FENCED = 3,
 190         OPAL_EEH_SEV_PE_ER      = 4,
 191         OPAL_EEH_SEV_INF        = 5
 192 };
 193
 194 enum OpalShpcAction {
 195         OPAL_SHPC_GET_LINK_STATE = 0,
 196         OPAL_SHPC_GET_SLOT_STATE = 1
 197 };
 198
 199 enum OpalShpcLinkState {
 200         OPAL_SHPC_LINK_DOWN = 0,
 201         OPAL_SHPC_LINK_UP = 1
 202 };
 203
 204 enum OpalMmioWindowType {
 205         OPAL_M32_WINDOW_TYPE = 1,
 206         OPAL_M64_WINDOW_TYPE = 2,
 207         OPAL_IO_WINDOW_TYPE = 3
 208 };
 209
 210 enum OpalShpcSlotState {
 211         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 212         OPAL_SHPC_DEV_PRESENT = 1
 213 };
 214
 215 enum OpalExceptionHandler {
 216         OPAL_MACHINE_CHECK_HANDLER = 1,
 217         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 218         OPAL_SOFTPATCH_HANDLER = 3
 219 };
 220
 221 enum OpalPendingState {
 222         OPAL_EVENT_OPAL_INTERNAL        = 0x1,
 223         OPAL_EVENT_NVRAM                = 0x2,
 224         OPAL_EVENT_RTC                  = 0x4,
 225         OPAL_EVENT_CONSOLE_OUTPUT       = 0x8,
 226         OPAL_EVENT_CONSOLE_INPUT        = 0x10,
 227         OPAL_EVENT_ERROR_LOG_AVAIL      = 0x20,
 228         OPAL_EVENT_ERROR_LOG            = 0x40,
 229         OPAL_EVENT_EPOW                 = 0x80,
 230         OPAL_EVENT_LED_STATUS           = 0x100,
 231         OPAL_EVENT_PCI_ERROR            = 0x200,
 232         OPAL_EVENT_DUMP_AVAIL           = 0x400,
 233         OPAL_EVENT_MSG_PENDING          = 0x800,
 234 };
 235
 236 enum OpalMessageType {
 237         OPAL_MSG_ASYNC_COMP = 0,        /* params[0] = token, params[1] = rc,
 238                                          * additional params function-specific
 239                                          */
 240         OPAL_MSG_MEM_ERR,
 241         OPAL_MSG_EPOW,
 242         OPAL_MSG_SHUTDOWN,
 243         OPAL_MSG_TYPE_MAX,
 244 };
 245
 246 /* Machine check related definitions */
 247 enum OpalMCE_Version {
 248         OpalMCE_V1 = 1,
 249 };
 250
 251 enum OpalMCE_Severity {
 252         OpalMCE_SEV_NO_ERROR = 0,
 253         OpalMCE_SEV_WARNING = 1,
 254         OpalMCE_SEV_ERROR_SYNC = 2,
 255         OpalMCE_SEV_FATAL = 3,
 256 };
 257
 258 enum OpalMCE_Disposition {
 259         OpalMCE_DISPOSITION_RECOVERED = 0,
 260         OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
 261 };
 262
 263 enum OpalMCE_Initiator {
 264         OpalMCE_INITIATOR_UNKNOWN = 0,
 265         OpalMCE_INITIATOR_CPU = 1,
 266 };
 267
 268 enum OpalMCE_ErrorType {
 269         OpalMCE_ERROR_TYPE_UNKNOWN = 0,
 270         OpalMCE_ERROR_TYPE_UE = 1,
 271         OpalMCE_ERROR_TYPE_SLB = 2,
 272         OpalMCE_ERROR_TYPE_ERAT = 3,
 273         OpalMCE_ERROR_TYPE_TLB = 4,
 274 };
 275
 276 enum OpalMCE_UeErrorType {
 277         OpalMCE_UE_ERROR_INDETERMINATE = 0,
 278         OpalMCE_UE_ERROR_IFETCH = 1,
 279         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
 280         OpalMCE_UE_ERROR_LOAD_STORE = 3,
 281         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
 282 };
 283
 284 enum OpalMCE_SlbErrorType {
 285         OpalMCE_SLB_ERROR_INDETERMINATE = 0,
 286         OpalMCE_SLB_ERROR_PARITY = 1,
 287         OpalMCE_SLB_ERROR_MULTIHIT = 2,
 288 };
 289
 290 enum OpalMCE_EratErrorType {
 291         OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
 292         OpalMCE_ERAT_ERROR_PARITY = 1,
 293         OpalMCE_ERAT_ERROR_MULTIHIT = 2,
 294 };
 295
 296 enum OpalMCE_TlbErrorType {
 297         OpalMCE_TLB_ERROR_INDETERMINATE = 0,
 298         OpalMCE_TLB_ERROR_PARITY = 1,
 299         OpalMCE_TLB_ERROR_MULTIHIT = 2,
 300 };
 301
 302 enum OpalThreadStatus {
 303         OPAL_THREAD_INACTIVE = 0x0,
 304         OPAL_THREAD_STARTED = 0x1,
 305         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 306 };
 307
 308 enum OpalPciBusCompare {
 309         OpalPciBusAny   = 0,    /* Any bus number match */
 310         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 311         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 312         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 313         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 314         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 315         OpalPciBusAll   = 7,    /* Match bus number exactly */
 316 };
 317
 318 enum OpalDeviceCompare {
 319         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 320         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 321 };
 322
 323 enum OpalFuncCompare {
 324         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 325         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 326 };
 327
 328 enum OpalPeAction {
 329         OPAL_UNMAP_PE = 0,
 330         OPAL_MAP_PE = 1
 331 };
 332
 333 enum OpalPeltvAction {
 334         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 335         OPAL_ADD_PE_TO_DOMAIN = 1
 336 };
 337
 338 enum OpalMveEnableAction {
 339         OPAL_DISABLE_MVE = 0,
 340         OPAL_ENABLE_MVE = 1
 341 };
 342
 343 enum OpalPciResetScope {
 344         OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
 345         OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
 346         OPAL_PCI_IODA_TABLE_RESET = 6,
 347 };
 348
 349 enum OpalPciReinitScope {
 350         OPAL_REINIT_PCI_DEV = 1000
 351 };
 352
 353 enum OpalPciResetState {
 354         OPAL_DEASSERT_RESET = 0,
 355         OPAL_ASSERT_RESET = 1
 356 };
 357
 358 enum OpalPciMaskAction {
 359         OPAL_UNMASK_ERROR_TYPE = 0,
 360         OPAL_MASK_ERROR_TYPE = 1
 361 };
 362
 363 enum OpalSlotLedType {
 364         OPAL_SLOT_LED_ID_TYPE = 0,
 365         OPAL_SLOT_LED_FAULT_TYPE = 1
 366 };
 367
 368 enum OpalLedAction {
 369         OPAL_TURN_OFF_LED = 0,
 370         OPAL_TURN_ON_LED = 1,
 371         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 372 };
 373
 374 enum OpalEpowStatus {
 375         OPAL_EPOW_NONE = 0,
 376         OPAL_EPOW_UPS = 1,
 377         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 378         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 379 };
 380
 381 /*
 382  * Address cycle types for LPC accesses. These also correspond
 383  * to the content of the first cell of the "reg" property for
 384  * device nodes on the LPC bus
 385  */
 386 enum OpalLPCAddressType {
 387         OPAL_LPC_MEM    = 0,
 388         OPAL_LPC_IO     = 1,
 389         OPAL_LPC_FW     = 2,
 390 };
 391
 392 /* System parameter permission */
 393 enum OpalSysparamPerm {
 394         OPAL_SYSPARAM_READ      = 0x1,
 395         OPAL_SYSPARAM_WRITE     = 0x2,
 396         OPAL_SYSPARAM_RW        = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 397 };
 398
 399 struct opal_msg {
 400         __be32 msg_type;
 401         __be32 reserved;
 402         __be64 params[8];
 403 };
 404
 405 struct opal_machine_check_event {
 406         enum OpalMCE_Version    version:8;      /* 0x00 */
 407         uint8_t                 in_use;         /* 0x01 */
 408         enum OpalMCE_Severity   severity:8;     /* 0x02 */
 409         enum OpalMCE_Initiator  initiator:8;    /* 0x03 */
 410         enum OpalMCE_ErrorType  error_type:8;   /* 0x04 */
 411         enum OpalMCE_Disposition disposition:8; /* 0x05 */
 412         uint8_t                 reserved_1[2];  /* 0x06 */
 413         uint64_t                gpr3;           /* 0x08 */
 414         uint64_t                srr0;           /* 0x10 */
 415         uint64_t                srr1;           /* 0x18 */
 416         union {                                 /* 0x20 */
 417                 struct {
 418                         enum OpalMCE_UeErrorType ue_error_type:8;
 419                         uint8_t         effective_address_provided;
 420                         uint8_t         physical_address_provided;
 421                         uint8_t         reserved_1[5];
 422                         uint64_t        effective_address;
 423                         uint64_t        physical_address;
 424                         uint8_t         reserved_2[8];
 425                 } ue_error;
 426
 427                 struct {
 428                         enum OpalMCE_SlbErrorType slb_error_type:8;
 429                         uint8_t         effective_address_provided;
 430                         uint8_t         reserved_1[6];
 431                         uint64_t        effective_address;
 432                         uint8_t         reserved_2[16];
 433                 } slb_error;
 434
 435                 struct {
 436                         enum OpalMCE_EratErrorType erat_error_type:8;
 437                         uint8_t         effective_address_provided;
 438                         uint8_t         reserved_1[6];
 439                         uint64_t        effective_address;
 440                         uint8_t         reserved_2[16];
 441                 } erat_error;
 442
 443                 struct {
 444                         enum OpalMCE_TlbErrorType tlb_error_type:8;
 445                         uint8_t         effective_address_provided;
 446                         uint8_t         reserved_1[6];
 447                         uint64_t        effective_address;
 448                         uint8_t         reserved_2[16];
 449                 } tlb_error;
 450         } u;
 451 };
 452
 453 /* FSP memory errors handling */
 454 enum OpalMemErr_Version {
 455         OpalMemErr_V1 = 1,
 456 };
 457
 458 enum OpalMemErrType {
 459         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 460         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 461         OPAL_MEM_ERR_TYPE_SCRUB,
 462 };
 463
 464 /* Memory Reilience error type */
 465 enum OpalMemErr_ResilErrType {
 466         OPAL_MEM_RESILIENCE_CE          = 0,
 467         OPAL_MEM_RESILIENCE_UE,
 468         OPAL_MEM_RESILIENCE_UE_SCRUB,
 469 };
 470
 471 /* Dynamic Memory Deallocation type */
 472 enum OpalMemErr_DynErrType {
 473         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 474 };
 475
 476 /* OpalMemoryErrorData->flags */
 477 #define OPAL_MEM_CORRECTED_ERROR        0x0001
 478 #define OPAL_MEM_THRESHOLD_EXCEEDED     0x0002
 479 #define OPAL_MEM_ACK_REQUIRED           0x8000
 480
 481 struct OpalMemoryErrorData {
 482         enum OpalMemErr_Version version:8;      /* 0x00 */
 483         enum OpalMemErrType     type:8;         /* 0x01 */
 484         __be16                  flags;          /* 0x02 */
 485         uint8_t                 reserved_1[4];  /* 0x04 */
 486
 487         union {
 488                 /* Memory Resilience corrected/uncorrected error info */
 489                 struct {
 490                         enum OpalMemErr_ResilErrType resil_err_type:8;
 491                         uint8_t         reserved_1[7];
 492                         __be64          physical_address_start;
 493                         __be64          physical_address_end;
 494                 } resilience;
 495                 /* Dynamic memory deallocation error info */
 496                 struct {
 497                         enum OpalMemErr_DynErrType dyn_err_type:8;
 498                         uint8_t         reserved_1[7];
 499                         __be64          physical_address_start;
 500                         __be64          physical_address_end;
 501                 } dyn_dealloc;
 502         } u;
 503 };
 504
 505 enum {
 506         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 507         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 508         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 509         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 510         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 511         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 512         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 513 };
 514
 515 struct OpalIoP7IOCErrorData {
 516         uint16_t type;
 517
 518         /* GEM */
 519         uint64_t gemXfir;
 520         uint64_t gemRfir;
 521         uint64_t gemRirqfir;
 522         uint64_t gemMask;
 523         uint64_t gemRwof;
 524
 525         /* LEM */
 526         uint64_t lemFir;
 527         uint64_t lemErrMask;
 528         uint64_t lemAction0;
 529         uint64_t lemAction1;
 530         uint64_t lemWof;
 531
 532         union {
 533                 struct OpalIoP7IOCRgcErrorData {
 534                         uint64_t rgcStatus;             /* 3E1C10 */
 535                         uint64_t rgcLdcp;               /* 3E1C18 */
 536                 }rgc;
 537                 struct OpalIoP7IOCBiErrorData {
 538                         uint64_t biLdcp0;               /* 3C0100, 3C0118 */
 539                         uint64_t biLdcp1;               /* 3C0108, 3C0120 */
 540                         uint64_t biLdcp2;               /* 3C0110, 3C0128 */
 541                         uint64_t biFenceStatus;         /* 3C0130, 3C0130 */
 542
 543                         uint8_t  biDownbound;           /* BI Downbound or Upbound */
 544                 }bi;
 545                 struct OpalIoP7IOCCiErrorData {
 546                         uint64_t ciPortStatus;          /* 3Dn008 */
 547                         uint64_t ciPortLdcp;            /* 3Dn010 */
 548
 549                         uint8_t  ciPort;                /* Index of CI port: 0/1 */
 550                 }ci;
 551         };
 552 };
 553
 554 /**
 555  * This structure defines the overlay which will be used to store PHB error
 556  * data upon request.
 557  */
 558 enum {
 559         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 560 };
 561
 562 enum {
 563         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 564         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 565 };
 566
 567 enum {
 568         OPAL_P7IOC_NUM_PEST_REGS = 128,
 569         OPAL_PHB3_NUM_PEST_REGS = 256
 570 };
 571
 572 struct OpalIoPhbErrorCommon {
 573         __be32 version;
 574         __be32 ioType;
 575         __be32 len;
 576 };
 577
 578 struct OpalIoP7IOCPhbErrorData {
 579         struct OpalIoPhbErrorCommon common;
 580
 581         uint32_t brdgCtl;
 582
 583         // P7IOC utl regs
 584         uint32_t portStatusReg;
 585         uint32_t rootCmplxStatus;
 586         uint32_t busAgentStatus;
 587
 588         // P7IOC cfg regs
 589         uint32_t deviceStatus;
 590         uint32_t slotStatus;
 591         uint32_t linkStatus;
 592         uint32_t devCmdStatus;
 593         uint32_t devSecStatus;
 594
 595         // cfg AER regs
 596         uint32_t rootErrorStatus;
 597         uint32_t uncorrErrorStatus;
 598         uint32_t corrErrorStatus;
 599         uint32_t tlpHdr1;
 600         uint32_t tlpHdr2;
 601         uint32_t tlpHdr3;
 602         uint32_t tlpHdr4;
 603         uint32_t sourceId;
 604
 605         uint32_t rsv3;
 606
 607         // Record data about the call to allocate a buffer.
 608         uint64_t errorClass;
 609         uint64_t correlator;
 610
 611         //P7IOC MMIO Error Regs
 612         uint64_t p7iocPlssr;                // n120
 613         uint64_t p7iocCsr;                  // n110
 614         uint64_t lemFir;                    // nC00
 615         uint64_t lemErrorMask;              // nC18
 616         uint64_t lemWOF;                    // nC40
 617         uint64_t phbErrorStatus;            // nC80
 618         uint64_t phbFirstErrorStatus;       // nC88
 619         uint64_t phbErrorLog0;              // nCC0
 620         uint64_t phbErrorLog1;              // nCC8
 621         uint64_t mmioErrorStatus;           // nD00
 622         uint64_t mmioFirstErrorStatus;      // nD08
 623         uint64_t mmioErrorLog0;             // nD40
 624         uint64_t mmioErrorLog1;             // nD48
 625         uint64_t dma0ErrorStatus;           // nD80
 626         uint64_t dma0FirstErrorStatus;      // nD88
 627         uint64_t dma0ErrorLog0;             // nDC0
 628         uint64_t dma0ErrorLog1;             // nDC8
 629         uint64_t dma1ErrorStatus;           // nE00
 630         uint64_t dma1FirstErrorStatus;      // nE08
 631         uint64_t dma1ErrorLog0;             // nE40
 632         uint64_t dma1ErrorLog1;             // nE48
 633         uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
 634         uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
 635 };
 636
 637 struct OpalIoPhb3ErrorData {
 638         struct OpalIoPhbErrorCommon common;
 639
 640         __be32 brdgCtl;
 641
 642         /* PHB3 UTL regs */
 643         __be32 portStatusReg;
 644         __be32 rootCmplxStatus;
 645         __be32 busAgentStatus;
 646
 647         /* PHB3 cfg regs */
 648         __be32 deviceStatus;
 649         __be32 slotStatus;
 650         __be32 linkStatus;
 651         __be32 devCmdStatus;
 652         __be32 devSecStatus;
 653
 654         /* cfg AER regs */
 655         __be32 rootErrorStatus;
 656         __be32 uncorrErrorStatus;
 657         __be32 corrErrorStatus;
 658         __be32 tlpHdr1;
 659         __be32 tlpHdr2;
 660         __be32 tlpHdr3;
 661         __be32 tlpHdr4;
 662         __be32 sourceId;
 663
 664         __be32 rsv3;
 665
 666         /* Record data about the call to allocate a buffer */
 667         __be64 errorClass;
 668         __be64 correlator;
 669
 670         __be64 nFir;                    /* 000 */
 671         __be64 nFirMask;                /* 003 */
 672         __be64 nFirWOF;         /* 008 */
 673
 674         /* PHB3 MMIO Error Regs */
 675         __be64 phbPlssr;                /* 120 */
 676         __be64 phbCsr;          /* 110 */
 677         __be64 lemFir;          /* C00 */
 678         __be64 lemErrorMask;            /* C18 */
 679         __be64 lemWOF;          /* C40 */
 680         __be64 phbErrorStatus;  /* C80 */
 681         __be64 phbFirstErrorStatus;     /* C88 */
 682         __be64 phbErrorLog0;            /* CC0 */
 683         __be64 phbErrorLog1;            /* CC8 */
 684         __be64 mmioErrorStatus; /* D00 */
 685         __be64 mmioFirstErrorStatus;    /* D08 */
 686         __be64 mmioErrorLog0;           /* D40 */
 687         __be64 mmioErrorLog1;           /* D48 */
 688         __be64 dma0ErrorStatus; /* D80 */
 689         __be64 dma0FirstErrorStatus;    /* D88 */
 690         __be64 dma0ErrorLog0;           /* DC0 */
 691         __be64 dma0ErrorLog1;           /* DC8 */
 692         __be64 dma1ErrorStatus; /* E00 */
 693         __be64 dma1FirstErrorStatus;    /* E08 */
 694         __be64 dma1ErrorLog0;           /* E40 */
 695         __be64 dma1ErrorLog1;           /* E48 */
 696         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 697         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 698 };
 699
 700 enum {
 701         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 702         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 703 };
 704
 705 typedef struct oppanel_line {
 706         const char *    line;
 707         uint64_t        line_len;
 708 } oppanel_line_t;
 709
 710 /* /sys/firmware/opal */
 711 extern struct kobject *opal_kobj;
 712
 713 /* /ibm,opal */
 714 extern struct device_node *opal_node;
 715
 716 /* API functions */
 717 int64_t opal_invalid_call(void);
 718 int64_t opal_console_write(int64_t term_number, __be64 *length,
 719                            const uint8_t *buffer);
 720 int64_t opal_console_read(int64_t term_number, __be64 *length,
 721                           uint8_t *buffer);
 722 int64_t opal_console_write_buffer_space(int64_t term_number,
 723                                         __be64 *length);
 724 int64_t opal_rtc_read(__be32 *year_month_day,
 725                       __be64 *hour_minute_second_millisecond);
 726 int64_t opal_rtc_write(uint32_t year_month_day,
 727                        uint64_t hour_minute_second_millisecond);
 728 int64_t opal_cec_power_down(uint64_t request);
 729 int64_t opal_cec_reboot(void);
 730 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 731 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 732 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
 733 int64_t opal_poll_events(__be64 *outstanding_event_mask);
 734 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
 735                                     uint64_t tce_mem_size);
 736 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
 737                                     uint64_t tce_mem_size);
 738 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
 739                                   uint64_t offset, uint8_t *data);
 740 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 741                                        uint64_t offset, __be16 *data);
 742 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
 743                                   uint64_t offset, __be32 *data);
 744 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
 745                                    uint64_t offset, uint8_t data);
 746 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 747                                         uint64_t offset, uint16_t data);
 748 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
 749                                    uint64_t offset, uint32_t data);
 750 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
 751 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
 752 int64_t opal_register_exception_handler(uint64_t opal_exception,
 753                                         uint64_t handler_address,
 754                                         uint64_t glue_cache_line);
 755 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 756                                    uint8_t *freeze_state,
 757                                    __be16 *pci_error_type,
 758                                    __be64 *phb_status);
 759 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 760                                   uint64_t eeh_action_token);
 761 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 762
 763
 764
 765 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
 766                                  uint16_t window_num, uint16_t enable);
 767 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
 768                                     uint16_t window_num,
 769                                     uint64_t starting_real_address,
 770                                     uint64_t starting_pci_address,
 771                                     uint16_t segment_size);
 772 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 773                                     uint16_t window_type, uint16_t window_num,
 774                                     uint16_t segment_num);
 775 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
 776                                       uint64_t ivt_addr, uint64_t ivt_len,
 777                                       uint64_t reject_array_addr,
 778                                       uint64_t peltv_addr);
 779 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
 780                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
 781                         uint8_t pe_action);
 782 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
 783                            uint8_t state);
 784 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
 785 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 786                                 uint32_t state);
 787 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 788                                   uint8_t *p_bit, uint8_t *q_bit);
 789 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 790                                   uint8_t p_bit, uint8_t q_bit);
 791 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 792 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 793                              uint32_t xive_num);
 794 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 795                              __be32 *interrupt_source_number);
 796 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
 797                         uint8_t msi_range, __be32 *msi_address,
 798                         __be32 *message_data);
 799 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 800                         uint32_t xive_num, uint8_t msi_range,
 801                         __be64 *msi_address, __be32 *message_data);
 802 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
 803 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
 804 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
 805 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
 806                                    uint16_t tce_levels, uint64_t tce_table_addr,
 807                                    uint64_t tce_table_size, uint64_t tce_page_size);
 808 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
 809                                         uint16_t dma_window_number, uint64_t pci_start_addr,
 810                                         uint64_t pci_mem_size);
 811 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 812
 813 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
 814                                    uint64_t diag_buffer_len);
 815 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
 816                                    uint64_t diag_buffer_len);
 817 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
 818                                     uint64_t diag_buffer_len);
 819 int64_t opal_pci_fence_phb(uint64_t phb_id);
 820 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
 821 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 822 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 823 int64_t opal_get_epow_status(__be64 *status);
 824 int64_t opal_set_system_attention_led(uint8_t led_action);
 825 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
 826                             __be16 *pci_error_type, __be16 *severity);
 827 int64_t opal_pci_poll(uint64_t phb_id);
 828 int64_t opal_return_cpu(void);
 829 int64_t opal_reinit_cpus(uint64_t flags);
 830
 831 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
 832 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
 833
 834 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 835                        uint32_t addr, uint32_t data, uint32_t sz);
 836 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 837                       uint32_t addr, __be32 *data, uint32_t sz);
 838
 839 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
 840 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
 841 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
 842 int64_t opal_send_ack_elog(uint64_t log_id);
 843 void opal_resend_pending_logs(void);
 844
 845 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
 846 int64_t opal_manage_flash(uint8_t op);
 847 int64_t opal_update_flash(uint64_t blk_list);
 848 int64_t opal_dump_init(uint8_t dump_type);
 849 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
 850 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
 851 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
 852 int64_t opal_dump_ack(uint32_t dump_id);
 853 int64_t opal_dump_resend_notification(void);
 854
 855 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
 856 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
 857 int64_t opal_sync_host_reboot(void);
 858 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 859                 uint64_t length);
 860 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 861                 uint64_t length);
 862 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
 863
 864 /* Internal functions */
 865 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
 866                                    int depth, void *data);
 867 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
 868                                  const char *uname, int depth, void *data);
 869
 870 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 871 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 872
 873 extern void hvc_opal_init_early(void);
 874
 875 extern int opal_notifier_register(struct notifier_block *nb);
 876 extern int opal_notifier_unregister(struct notifier_block *nb);
 877
 878 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
 879                                                 struct notifier_block *nb);
 880 extern void opal_notifier_enable(void);
 881 extern void opal_notifier_disable(void);
 882 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
 883
 884 extern int __opal_async_get_token(void);
 885 extern int opal_async_get_token_interruptible(void);
 886 extern int __opal_async_release_token(int token);
 887 extern int opal_async_release_token(int token);
 888 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
 889 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
 890
 891 struct rtc_time;
 892 extern int opal_set_rtc_time(struct rtc_time *tm);
 893 extern void opal_get_rtc_time(struct rtc_time *tm);
 894 extern unsigned long opal_get_boot_time(void);
 895 extern void opal_nvram_init(void);
 896 extern void opal_flash_init(void);
 897 extern void opal_flash_term_callback(void);
 898 extern int opal_elog_init(void);
 899 extern void opal_platform_dump_init(void);
 900 extern void opal_sys_param_init(void);
 901 extern void opal_msglog_init(void);
 902
 903 extern int opal_machine_check(struct pt_regs *regs);
 904 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
 905
 906 extern void opal_shutdown(void);
 907 extern int opal_resync_timebase(void);
 908
 909 extern void opal_lpc_init(void);
 910
 911 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
 912                                              unsigned long vmalloc_size);
 913 void opal_free_sg_list(struct opal_sg_list *sg);
 914
 915 #endif /* __ASSEMBLY__ */
 916
 917 #endif /* __OPAL_H */