2 * This control block defines the PACA which defines the processor
3 * specific data for each logical processor on the system.
4 * There are some pointers defined that are utilized by PLIC.
6 * C 2001 PPC 64 Team, IBM Corp
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
13 #ifndef _ASM_POWERPC_PACA_H
14 #define _ASM_POWERPC_PACA_H
19 #include <linux/string.h>
20 #include <asm/types.h>
21 #include <asm/lppaca.h>
24 #include <asm/exception-64e.h>
25 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
26 #include <asm/kvm_book3s_asm.h>
29 register struct paca_struct *local_paca asm("r13");
31 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
32 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
34 * Add standard checks that preemption cannot occur when using get_paca():
35 * otherwise the paca_struct it points to may be the wrong one just after.
37 #define get_paca() ((void) debug_smp_processor_id(), local_paca)
39 #define get_paca() local_paca
42 #define get_lppaca() (get_paca()->lppaca_ptr)
43 #define get_slb_shadow() (get_paca()->slb_shadow_ptr)
48 * Defines the layout of the paca.
50 * This structure is not directly accessed by firmware or the service
54 #ifdef CONFIG_PPC_BOOK3S
56 * Because hw_cpu_id, unlike other paca fields, is accessed
57 * routinely from other CPUs (from the IRQ code), we stick to
58 * read-only (after boot) fields in the first cacheline to
59 * avoid cacheline bouncing.
62 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
63 #endif /* CONFIG_PPC_BOOK3S */
65 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
66 * load lock_token and paca_index with a single lwz
67 * instruction. They must travel together and be properly
71 u16 lock_token; /* Constant 0x8000, used in locks */
72 u16 paca_index; /* Logical processor number */
74 u16 paca_index; /* Logical processor number */
75 u16 lock_token; /* Constant 0x8000, used in locks */
78 u64 kernel_toc; /* Kernel TOC address */
79 u64 kernelbase; /* Base address of kernel */
80 u64 kernel_msr; /* MSR while running in kernel */
81 void *emergency_sp; /* pointer to emergency stack */
82 u64 data_offset; /* per cpu data offset */
83 s16 hw_cpu_id; /* Physical processor number */
84 u8 cpu_start; /* At startup, processor spins until */
85 /* this becomes non-zero. */
86 u8 kexec_state; /* set when kexec down has irqs off */
87 #ifdef CONFIG_PPC_STD_MMU_64
88 struct slb_shadow *slb_shadow_ptr;
89 struct dtl_entry *dispatch_log;
90 struct dtl_entry *dispatch_log_end;
91 #endif /* CONFIG_PPC_STD_MMU_64 */
92 u64 dscr_default; /* per-CPU default DSCR */
94 #ifdef CONFIG_PPC_STD_MMU_64
96 * Now, starting in cacheline 2, the exception save areas
98 /* used for most interrupts/exceptions */
99 u64 exgen[13] __attribute__((aligned(0x80)));
100 u64 exmc[13]; /* used for machine checks */
101 u64 exslb[13]; /* used for SLB/segment table misses
102 * on the linear mapping */
103 /* SLB related definitions */
106 u32 slb_cache[SLB_CACHE_ENTRIES];
107 #endif /* CONFIG_PPC_STD_MMU_64 */
109 #ifdef CONFIG_PPC_BOOK3E
110 u64 exgen[8] __aligned(0x40);
111 /* Keep pgd in the same cacheline as the start of extlb */
112 pgd_t *pgd __aligned(0x40); /* Current PGD */
113 pgd_t *kernel_pgd; /* Kernel PGD */
115 /* Shared by all threads of a core -- points to tcd of first thread */
116 struct tlb_core_data *tcd_ptr;
119 * We can have up to 3 levels of reentrancy in the TLB miss handler,
120 * in each of four exception levels (normal, crit, mcheck, debug).
122 u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
123 u64 exmc[8]; /* used for machine checks */
124 u64 excrit[8]; /* used for crit interrupts */
125 u64 exdbg[8]; /* used for debug interrupts */
127 /* Kernel stack pointers for use by special exceptions */
132 struct tlb_core_data tcd;
133 #endif /* CONFIG_PPC_BOOK3E */
135 #ifdef CONFIG_PPC_BOOK3S
136 mm_context_id_t mm_ctx_id;
137 #ifdef CONFIG_PPC_MM_SLICES
138 u64 mm_ctx_low_slices_psize;
139 unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
141 u16 mm_ctx_user_psize;
147 * then miscellaneous read-write fields
149 struct task_struct *__current; /* Pointer to current */
150 u64 kstack; /* Saved Kernel stack addr */
151 u64 stab_rr; /* stab/slb round-robin counter */
152 u64 saved_r1; /* r1 save for RTAS calls or PM */
153 u64 saved_msr; /* MSR saved here by enter_rtas */
154 u16 trap_save; /* Used when bad stack is encountered */
155 u8 soft_enabled; /* irq soft-enable flag */
156 u8 irq_happened; /* irq happened while soft-disabled */
157 u8 io_sync; /* writel() needs spin_unlock sync */
158 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
159 u8 nap_state_lost; /* NV GPR values lost in power7_idle */
160 u64 sprg_vdso; /* Saved user-visible sprg */
161 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
162 u64 tm_scratch; /* TM scratch area for reclaim */
165 #ifdef CONFIG_PPC_POWERNV
166 /* Per-core mask tracking idle threads and a lock bit-[L][TTTTTTTT] */
167 u32 *core_idle_state_ptr;
168 u8 thread_idle_state; /* PNV_THREAD_RUNNING/NAP/SLEEP */
169 /* Mask to indicate thread id in core */
171 /* Mask to denote subcore sibling threads */
172 u8 subcore_sibling_mask;
175 #ifdef CONFIG_PPC_BOOK3S_64
176 /* Exclusive emergency stack pointer for machine check exception. */
177 void *mc_emergency_sp;
179 * Flag to check whether we are in machine check early handler
180 * and already using emergency stack.
183 u8 hmi_event_available; /* HMI event is available */
186 /* Stuff for accurate time accounting */
187 u64 user_time; /* accumulated usermode TB ticks */
188 u64 system_time; /* accumulated system TB ticks */
189 u64 user_time_scaled; /* accumulated usermode SPURR ticks */
190 u64 starttime; /* TB value snapshot */
191 u64 starttime_user; /* TB value on exit to usermode */
192 u64 startspurr; /* SPURR value snapshot */
193 u64 utime_sspurr; /* ->user_time when ->startspurr set */
194 u64 stolen_time; /* TB ticks taken by hypervisor */
195 u64 dtl_ridx; /* read index in dispatch log */
196 struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */
198 #ifdef CONFIG_KVM_BOOK3S_HANDLER
199 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
200 /* We use this to store guest state in */
201 struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
203 struct kvmppc_host_state kvm_hstate;
207 #ifdef CONFIG_PPC_BOOK3S
208 static inline void copy_mm_to_paca(mm_context_t *context)
210 get_paca()->mm_ctx_id = context->id;
211 #ifdef CONFIG_PPC_MM_SLICES
212 get_paca()->mm_ctx_low_slices_psize = context->low_slices_psize;
213 memcpy(&get_paca()->mm_ctx_high_slices_psize,
214 &context->high_slices_psize, SLICE_ARRAY_SIZE);
216 get_paca()->mm_ctx_user_psize = context->user_psize;
217 get_paca()->mm_ctx_sllp = context->sllp;
221 static inline void copy_mm_to_paca(mm_context_t *context){}
224 extern struct paca_struct *paca;
225 extern void initialise_paca(struct paca_struct *new_paca, int cpu);
226 extern void setup_paca(struct paca_struct *new_paca);
227 extern void allocate_pacas(void);
228 extern void free_unused_pacas(void);
230 #else /* CONFIG_PPC64 */
232 static inline void allocate_pacas(void) { };
233 static inline void free_unused_pacas(void) { };
235 #endif /* CONFIG_PPC64 */
237 #endif /* __KERNEL__ */
238 #endif /* _ASM_POWERPC_PACA_H */