2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
7 #include <linux/stringify.h>
8 #include <asm/asm-compat.h>
9 #include <asm/processor.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/firmware.h>
14 #error __FILE__ should only be used in assembler files
17 #define SZL (BITS_PER_LONG/8)
20 * Stuff for accurate CPU time accounting.
21 * These macros handle transitions between user and system state
22 * in exception entry and exit and accumulate time to the
23 * user_time and system_time fields in the paca.
26 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
27 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)
28 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)
29 #define ACCOUNT_STOLEN_TIME
31 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) \
32 MFTB(ra); /* get timebase */ \
33 PPC_LL rb, ACCOUNT_STARTTIME_USER(ptr); \
34 PPC_STL ra, ACCOUNT_STARTTIME(ptr); \
35 subf rb,rb,ra; /* subtract start value */ \
36 PPC_LL ra, ACCOUNT_USER_TIME(ptr); \
37 add ra,ra,rb; /* add on to user time */ \
38 PPC_STL ra, ACCOUNT_USER_TIME(ptr); \
40 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) \
41 MFTB(ra); /* get timebase */ \
42 PPC_LL rb, ACCOUNT_STARTTIME(ptr); \
43 PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr); \
44 subf rb,rb,ra; /* subtract start value */ \
45 PPC_LL ra, ACCOUNT_SYSTEM_TIME(ptr); \
46 add ra,ra,rb; /* add on to system time */ \
47 PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr)
49 #ifdef CONFIG_PPC_SPLPAR
50 #define ACCOUNT_STOLEN_TIME \
51 BEGIN_FW_FTR_SECTION; \
53 /* from user - see if there are any DTL entries to process */ \
54 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
55 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
56 addi r10,r10,LPPACA_DTLIDX; \
57 LDX_BE r10,0,r10; /* get log write index */ \
60 bl accumulate_stolen_time; \
62 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \
64 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
66 #else /* CONFIG_PPC_SPLPAR */
67 #define ACCOUNT_STOLEN_TIME
69 #endif /* CONFIG_PPC_SPLPAR */
71 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
74 * Macros for storing registers into and loading registers from
78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
93 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
94 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
95 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
96 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
97 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
98 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
100 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
101 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
102 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
103 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
104 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
105 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
106 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
107 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
108 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
109 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
110 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
111 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
113 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
119 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
123 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
124 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
126 #ifdef __BIG_ENDIAN__
127 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
128 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
130 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
134 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
137 /* Save the lower 32 VSRs in the thread VSR region */
138 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
139 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
140 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
141 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
142 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
143 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
144 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
145 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
146 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
147 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
148 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
149 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
152 * b = base register for addressing, o = base offset from register of 1st EVR
153 * n = first EVR, s = scratch
155 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
156 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
157 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
158 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
159 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
160 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
161 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
162 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
163 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
164 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
165 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
166 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
168 /* Macros to adjust thread priority for hardware multithreading */
169 #define HMT_VERY_LOW or 31,31,31 # very low priority
170 #define HMT_LOW or 1,1,1
171 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
172 #define HMT_MEDIUM or 2,2,2
173 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
174 #define HMT_HIGH or 3,3,3
175 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only
182 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
183 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
188 #define STACKFRAMESIZE 256
189 #define __STK_REG(i) (112 + ((i)-14)*8)
190 #define STK_REG(i) __STK_REG(__REG_##i)
192 #ifdef PPC64_ELF_ABI_v2
194 #define __STK_PARAM(i) (32 + ((i)-3)*8)
197 #define __STK_PARAM(i) (48 + ((i)-3)*8)
199 #define STK_PARAM(i) __STK_PARAM(__REG_##i)
201 #ifdef PPC64_ELF_ABI_v2
203 #define _GLOBAL(name) \
206 .type name,@function; \
210 #define _GLOBAL_TOC(name) \
213 .type name,@function; \
216 0: addis r2,r12,(.TOC.-0b)@ha; \
217 addi r2,r2,(.TOC.-0b)@l; \
218 .localentry name,.-name
220 #define _KPROBE(name) \
221 .section ".kprobes.text","a"; \
223 .type name,@function; \
231 #define XGLUE(a,b) a##b
232 #define GLUE(a,b) XGLUE(a,b)
234 #define _GLOBAL(name) \
238 .globl GLUE(.,name); \
239 .section ".opd","aw"; \
241 .quad GLUE(.,name); \
242 .quad .TOC.@tocbase; \
245 .type GLUE(.,name),@function; \
248 #define _GLOBAL_TOC(name) _GLOBAL(name)
250 #define _KPROBE(name) \
251 .section ".kprobes.text","a"; \
254 .globl GLUE(.,name); \
255 .section ".opd","aw"; \
257 .quad GLUE(.,name); \
258 .quad .TOC.@tocbase; \
261 .type GLUE(.,name),@function; \
264 #define DOTSYM(a) GLUE(.,a)
276 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
280 #define _GLOBAL_TOC(name) _GLOBAL(name)
283 .section ".kprobes.text","a"; \
289 #define FUNC_START(name) _GLOBAL(name)
290 #define FUNC_END(name)
293 * LOAD_REG_IMMEDIATE(rn, expr)
294 * Loads the value of the constant expression 'expr' into register 'rn'
295 * using immediate instructions only. Use this when it's important not
296 * to reference other data (i.e. on ppc64 when the TOC pointer is not
297 * valid) and when 'expr' is a constant or absolute address.
299 * LOAD_REG_ADDR(rn, name)
300 * Loads the address of label 'name' into register 'rn'. Use this when
301 * you don't particularly need immediate instructions only, but you need
302 * the whole address in one register (e.g. it's a structure address and
303 * you want to access various offsets within it). On ppc32 this is
304 * identical to LOAD_REG_IMMEDIATE.
306 * LOAD_REG_ADDR_PIC(rn, name)
307 * Loads the address of label 'name' into register 'run'. Use this when
308 * the kernel doesn't run at the linked or relocated address. Please
309 * note that this macro will clobber the lr register.
311 * LOAD_REG_ADDRBASE(rn, name)
313 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
314 * register 'rn'. ADDROFF(name) returns the remainder of the address as
315 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
316 * in size, so is suitable for use directly as an offset in load and store
317 * instructions. Use this when loading/storing a single word or less as:
318 * LOAD_REG_ADDRBASE(rX, name)
319 * ld rY,ADDROFF(name)(rX)
322 /* Be careful, this will clobber the lr register. */
323 #define LOAD_REG_ADDR_PIC(reg, name) \
326 addis reg,reg,(name - 0b)@ha; \
327 addi reg,reg,(name - 0b)@l;
330 #ifdef HAVE_AS_ATHIGH
331 #define __AS_ATHIGH high
333 #define __AS_ATHIGH h
335 #define LOAD_REG_IMMEDIATE(reg,expr) \
336 lis reg,(expr)@highest; \
337 ori reg,reg,(expr)@higher; \
338 rldicr reg,reg,32,31; \
339 oris reg,reg,(expr)@__AS_ATHIGH; \
340 ori reg,reg,(expr)@l;
342 #define LOAD_REG_ADDR(reg,name) \
345 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
346 #define ADDROFF(name) 0
348 /* offsets for stack frame layout */
353 #define LOAD_REG_IMMEDIATE(reg,expr) \
355 addi reg,reg,(expr)@l;
357 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
359 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
360 #define ADDROFF(name) name@l
362 /* offsets for stack frame layout */
367 /* various errata or part fixups */
368 #ifdef CONFIG_PPC601_SYNC_FIX
373 END_FTR_SECTION_IFSET(CPU_FTR_601)
377 END_FTR_SECTION_IFSET(CPU_FTR_601)
381 END_FTR_SECTION_IFSET(CPU_FTR_601)
388 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
390 90: mfspr dest, SPRN_TBRL; \
391 BEGIN_FTR_SECTION_NESTED(96); \
394 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
395 #elif defined(CONFIG_8xx)
396 #define MFTB(dest) mftb dest
398 #define MFTB(dest) mfspr dest, SPRN_TBRL
403 #else /* CONFIG_SMP */
404 /* tlbsync is not implemented on 601 */
409 END_FTR_SECTION_IFCLR(CPU_FTR_601)
413 #define MTOCRF(FXM, RS) \
414 BEGIN_FTR_SECTION_NESTED(848); \
416 FTR_SECTION_ELSE_NESTED(848); \
418 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
422 * This instruction is not implemented on the PPC 603 or 601; however, on
423 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
424 * All of these instructions exist in the 8xx, they have magical powers,
425 * and they must be used.
428 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
432 lis r4,KERNELBASE@h; \
442 #ifdef CONFIG_IBM440EP_ERR42
443 #define PPC440EP_ERR42 isync
445 #define PPC440EP_ERR42
448 /* The following stops all load and store data streams associated with stream
449 * ID (ie. streams created explicitly). The embedded and server mnemonics for
450 * dcbt are different so we use machine "power4" here explicitly.
452 #define DCBT_STOP_ALL_STREAM_IDS(scratch) \
454 .machine "power4" ; \
455 lis scratch,0x60000000@h; \
456 dcbt r0,scratch,0b01010; \
460 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
461 * keep the address intact to be compatible with code shared with
464 * On the other hand, I find it useful to have them behave as expected
465 * by their name (ie always do the addition) on 64-bit BookE
467 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
472 * We use addis to ensure compatibility with the "classic" ppc versions of
473 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
474 * converting the address in r0, and so this version has to do that too
475 * (i.e. set register rd to 0 when rs == 0).
477 #define tophys(rd,rs) \
480 #define tovirt(rd,rs) \
483 #elif defined(CONFIG_PPC64)
484 #define toreal(rd) /* we can access c000... in real mode */
487 #define tophys(rd,rs) \
490 #define tovirt(rd,rs) \
492 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
496 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
497 * physical base address of RAM at compile time.
499 #define toreal(rd) tophys(rd,rd)
500 #define fromreal(rd) tovirt(rd,rd)
502 #define tophys(rd,rs) \
503 0: addis rd,rs,-PAGE_OFFSET@h; \
504 .section ".vtop_fixup","aw"; \
509 #define tovirt(rd,rs) \
510 0: addis rd,rs,PAGE_OFFSET@h; \
511 .section ".ptov_fixup","aw"; \
517 #ifdef CONFIG_PPC_BOOK3S_64
519 #define MTMSRD(r) mtmsrd r
520 #define MTMSR_EERI(reg) mtmsrd reg,1
522 #define FIX_SRR1(ra, rb)
526 #define RFI rfi; b . /* Prevent prefetch past rfi */
528 #define MTMSRD(r) mtmsr r
529 #define MTMSR_EERI(reg) mtmsr reg
533 #endif /* __KERNEL__ */
535 /* The boring bits... */
537 /* Condition Register Bit Fields */
550 * General Purpose Registers (GPRs)
552 * The lower case r0-r31 should be used in preference to the upper
553 * case R0-R31 as they provide more error checking in the assembler.
554 * Use R0-31 only when really nessesary.
591 /* Floating Point Registers (FPRs) */
626 /* AltiVec Registers (VPRs) */
661 /* VSX Registers (VSRs) */
728 /* SPE Registers (EVPRs) */
763 /* some stab codes */
770 * Create an endian fixup trampoline
772 * This starts with a "tdi 0,0,0x48" instruction which is
773 * essentially a "trap never", and thus akin to a nop.
775 * The opcode for this instruction read with the wrong endian
776 * however results in a b . + 8
778 * So essentially we use that trick to execute the following
779 * trampoline in "reverse endian" if we are running with the
780 * MSR_LE bit set the "wrong" way for whatever endianness the
781 * kernel is built for.
784 #ifdef CONFIG_PPC_BOOK3E
787 #define FIXUP_ENDIAN \
788 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
789 b $+36; /* Skip trampoline if endian is good */ \
790 .long 0x05009f42; /* bcl 20,31,$+4 */ \
791 .long 0xa602487d; /* mflr r10 */ \
792 .long 0x1c004a39; /* addi r10,r10,28 */ \
793 .long 0xa600607d; /* mfmsr r11 */ \
794 .long 0x01006b69; /* xori r11,r11,1 */ \
795 .long 0xa6035a7d; /* mtsrr0 r10 */ \
796 .long 0xa6037b7d; /* mtsrr1 r11 */ \
797 .long 0x2400004c /* rfid */
798 #endif /* !CONFIG_PPC_BOOK3E */
799 #endif /* __ASSEMBLY__ */
800 #endif /* _ASM_POWERPC_PPC_ASM_H */