3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
35 #include <asm/hw_irq.h>
36 #include <asm/context_tracking.h>
43 .tc sys_call_table[TC],sys_call_table
45 /* This value is used to mark exception frames on the stack. */
47 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
54 .globl system_call_common
58 addi r1,r1,-INT_FRAME_SIZE
66 beq 2f /* if from kernel mode */
67 ACCOUNT_CPU_USER_ENTRY(r10, r11)
86 * This clears CR0.SO (bit 28), which is the error indication on
87 * return from this system call.
89 rldimi r2,r11,28,(63-28)
96 addi r9,r1,STACK_FRAME_OVERHEAD
97 ld r11,exception_marker@toc(r2)
98 std r11,-16(r9) /* "regshere" marker */
99 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
102 /* if from user, see if there are any DTL entries to process */
103 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
104 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
105 addi r10,r10,LPPACA_DTLIDX
106 LDX_BE r10,0,r10 /* get log write index */
109 bl accumulate_stolen_time
113 addi r9,r1,STACK_FRAME_OVERHEAD
115 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
116 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
119 * A syscall should always be called with interrupts enabled
120 * so we just unconditionally hard-enable here. When some kind
121 * of irq tracing is used, we additionally check that condition
124 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
125 lbz r10,PACASOFTIRQEN(r13)
128 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
131 #ifdef CONFIG_PPC_BOOK3E
137 #endif /* CONFIG_PPC_BOOK3E */
139 /* We do need to set SOFTE in the stack frame or the return
140 * from interrupt will be painful
150 addi r9,r1,STACK_FRAME_OVERHEAD
152 CURRENT_THREAD_INFO(r11, r1)
154 andi. r11,r10,_TIF_SYSCALL_T_OR_A
156 .Lsyscall_dotrace_cont:
157 cmpldi 0,r0,NR_syscalls
160 system_call: /* label this so stack traces look sane */
162 * Need to vector to 32 Bit or default sys_call_table here,
163 * based on caller's run-mode / personality.
165 ld r11,SYS_CALL_TABLE@toc(2)
166 andi. r10,r10,_TIF_32BIT
168 addi r11,r11,8 /* use 32-bit syscall entries */
177 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
179 bctrl /* Call handler */
184 bl do_show_syscall_exit
187 CURRENT_THREAD_INFO(r12, r1)
190 #ifdef CONFIG_PPC_BOOK3S
191 /* No MSR:RI on BookE */
196 * Disable interrupts so current_thread_info()->flags can't change,
197 * and so that we don't get interrupted after loading SRR0/1.
199 #ifdef CONFIG_PPC_BOOK3E
204 * For performance reasons we clear RI the same time that we
205 * clear EE. We only need to clear RI just before we restore r13
206 * below, but batching it with EE saves us one expensive mtmsrd call.
207 * We have to be careful to restore RI if we branch anywhere from
208 * here (eg syscall_exit_work).
213 #endif /* CONFIG_PPC_BOOK3E */
217 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
218 bne- syscall_exit_work
222 .Lsyscall_error_cont:
225 stdcx. r0,0,r1 /* to clear the reservation */
226 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
231 ACCOUNT_CPU_USER_EXIT(r11, r12)
232 HMT_MEDIUM_LOW_HAS_PPR
233 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
241 b . /* prevent speculative execution */
244 oris r5,r5,0x1000 /* Set SO bit in CR */
247 b .Lsyscall_error_cont
249 /* Traced system call support */
252 addi r3,r1,STACK_FRAME_OVERHEAD
253 bl do_syscall_trace_enter
255 * Restore argument registers possibly just changed.
256 * We use the return value of do_syscall_trace_enter
257 * for the call number to look up in the table (r0).
266 addi r9,r1,STACK_FRAME_OVERHEAD
267 CURRENT_THREAD_INFO(r10, r1)
269 b .Lsyscall_dotrace_cont
276 #ifdef CONFIG_PPC_BOOK3S
277 mtmsrd r10,1 /* Restore RI */
279 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
280 If TIF_NOERROR is set, just save r3 as it is. */
282 andi. r0,r9,_TIF_RESTOREALL
286 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
288 andi. r0,r9,_TIF_NOERROR
292 oris r5,r5,0x1000 /* Set SO bit in CR */
295 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
298 /* Clear per-syscall TIF flags if any are set. */
300 li r11,_TIF_PERSYSCALL_MASK
301 addi r12,r12,TI_FLAGS
306 subi r12,r12,TI_FLAGS
308 4: /* Anything else left to do? */
309 SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
310 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
311 beq ret_from_except_lite
313 /* Re-enable interrupts */
314 #ifdef CONFIG_PPC_BOOK3E
320 #endif /* CONFIG_PPC_BOOK3E */
323 addi r3,r1,STACK_FRAME_OVERHEAD
324 bl do_syscall_trace_leave
327 /* Save non-volatile GPRs, if not already saved. */
339 * The sigsuspend and rt_sigsuspend system calls can call do_signal
340 * and thus put the process into the stopped state where we might
341 * want to examine its user state with ptrace. Therefore we need
342 * to save all the nonvolatile registers (r14 - r31) before calling
343 * the C code. Similarly, fork, vfork and clone need the full
344 * register state on the stack so that it can be copied to the child.
362 _GLOBAL(ppc32_swapcontext)
364 bl compat_sys_swapcontext
367 _GLOBAL(ppc64_swapcontext)
372 _GLOBAL(ret_from_fork)
378 _GLOBAL(ret_from_kernel_thread)
383 #if defined(_CALL_ELF) && _CALL_ELF == 2
391 * This routine switches between two different tasks. The process
392 * state of one is saved on its kernel stack. Then the state
393 * of the other is restored from its kernel stack. The memory
394 * management hardware is updated to the second process's state.
395 * Finally, we can return to the second process, via ret_from_except.
396 * On entry, r3 points to the THREAD for the current task, r4
397 * points to the THREAD for the new task.
399 * Note: there are two ways to get to the "going out" portion
400 * of this code; either by coming in via the entry (_switch)
401 * or via "fork" which must set up an environment equivalent
402 * to the "_switch" path. If you change this you'll have to change
403 * the fork code also.
405 * The code which creates the new task context is in 'copy_thread'
406 * in arch/powerpc/kernel/process.c
412 stdu r1,-SWITCH_FRAME_SIZE(r1)
413 /* r3-r13 are caller saved -- Cort */
416 mflr r20 /* Return to switch caller */
421 oris r0,r0,MSR_VSX@h /* Disable VSX */
422 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
423 #endif /* CONFIG_VSX */
424 #ifdef CONFIG_ALTIVEC
426 oris r0,r0,MSR_VEC@h /* Disable altivec */
427 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
428 std r24,THREAD_VRSAVE(r3)
429 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
430 #endif /* CONFIG_ALTIVEC */
434 std r25,THREAD_DSCR(r3)
435 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
445 std r1,KSP(r3) /* Set old stack pointer */
447 #ifdef CONFIG_PPC_BOOK3S_64
449 /* Event based branch registers */
451 std r0, THREAD_BESCR(r3)
453 std r0, THREAD_EBBHR(r3)
455 std r0, THREAD_EBBRR(r3)
456 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
460 /* We need a sync somewhere here to make sure that if the
461 * previous task gets rescheduled on another CPU, it sees all
462 * stores it has performed on this one.
465 #endif /* CONFIG_SMP */
468 * If we optimise away the clear of the reservation in system
469 * calls because we know the CPU tracks the address of the
470 * reservation, then we need to clear it here to cover the
471 * case that the kernel context switch path has no larx
476 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
478 #ifdef CONFIG_PPC_BOOK3S
479 /* Cancel all explict user streams as they will have no use after context
480 * switch and will stop the HW from creating streams itself
482 DCBT_STOP_ALL_STREAM_IDS(r6)
485 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
486 std r6,PACACURRENT(r13) /* Set new 'current' */
488 ld r8,KSP(r4) /* new stack pointer */
489 #ifdef CONFIG_PPC_BOOK3S
491 BEGIN_FTR_SECTION_NESTED(95)
492 clrrdi r6,r8,28 /* get its ESID */
493 clrrdi r9,r1,28 /* get current sp ESID */
494 FTR_SECTION_ELSE_NESTED(95)
495 clrrdi r6,r8,40 /* get its 1T ESID */
496 clrrdi r9,r1,40 /* get current sp 1T ESID */
497 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
500 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
501 clrldi. r0,r6,2 /* is new ESID c00000000? */
502 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
504 beq 2f /* if yes, don't slbie it */
506 /* Bolt in the new stack SLB entry */
507 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
508 oris r0,r6,(SLB_ESID_V)@h
509 ori r0,r0,(SLB_NUM_BOLTED-1)@l
511 li r9,MMU_SEGSIZE_1T /* insert B field */
512 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
513 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
514 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
516 /* Update the last bolted SLB. No write barriers are needed
517 * here, provided we only update the current CPU's SLB shadow
520 ld r9,PACA_SLBSHADOWPTR(r13)
522 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
523 li r12,SLBSHADOW_STACKVSID
524 STDX_BE r7,r12,r9 /* Save VSID */
525 li r12,SLBSHADOW_STACKESID
526 STDX_BE r0,r12,r9 /* Save ESID */
528 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
529 * we have 1TB segments, the only CPUs known to have the errata
530 * only support less than 1TB of system memory and we'll never
531 * actually hit this code path.
535 slbie r6 /* Workaround POWER5 < DD2.1 issue */
539 #endif /* !CONFIG_PPC_BOOK3S */
541 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
542 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
543 because we don't need to leave the 288-byte ABI gap at the
544 top of the kernel stack. */
545 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
547 mr r1,r8 /* start using new stack pointer */
548 std r7,PACAKSAVE(r13)
550 #ifdef CONFIG_PPC_BOOK3S_64
552 /* Event based branch registers */
553 ld r0, THREAD_BESCR(r4)
555 ld r0, THREAD_EBBHR(r4)
557 ld r0, THREAD_EBBRR(r4)
562 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
565 #ifdef CONFIG_ALTIVEC
567 ld r0,THREAD_VRSAVE(r4)
568 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
569 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
570 #endif /* CONFIG_ALTIVEC */
573 lwz r6,THREAD_DSCR_INHERIT(r4)
574 ld r0,THREAD_DSCR(r4)
579 BEGIN_FTR_SECTION_NESTED(70)
581 rldimi r8, r6, FSCR_DSCR_LG, (63 - FSCR_DSCR_LG)
583 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
588 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
594 /* r3-r13 are destroyed -- Cort */
598 /* convert old thread to its task_struct for return value */
600 ld r7,_NIP(r1) /* Return to _switch caller in new task */
602 addi r1,r1,SWITCH_FRAME_SIZE
606 _GLOBAL(ret_from_except)
609 bne ret_from_except_lite
612 _GLOBAL(ret_from_except_lite)
614 * Disable interrupts so that current_thread_info()->flags
615 * can't change between when we test it and when we return
616 * from the interrupt.
618 #ifdef CONFIG_PPC_BOOK3E
621 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
622 mtmsrd r10,1 /* Update machine state */
623 #endif /* CONFIG_PPC_BOOK3E */
625 CURRENT_THREAD_INFO(r9, r1)
627 #ifdef CONFIG_PPC_BOOK3E
628 ld r10,PACACURRENT(r13)
629 #endif /* CONFIG_PPC_BOOK3E */
633 #ifdef CONFIG_PPC_BOOK3E
634 lwz r3,(THREAD+THREAD_DBCR0)(r10)
635 #endif /* CONFIG_PPC_BOOK3E */
637 /* Check current_thread_info()->flags */
638 andi. r0,r4,_TIF_USER_WORK_MASK
639 #ifdef CONFIG_PPC_BOOK3E
642 * Check to see if the dbcr0 register is set up to debug.
643 * Use the internal debug mode bit to do this.
645 andis. r0,r3,DBCR0_IDM@h
648 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
657 1: andi. r0,r4,_TIF_NEED_RESCHED
659 bl restore_interrupts
661 b ret_from_except_lite
663 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
664 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
665 bne 3f /* only restore TM if nothing else to do */
666 addi r3,r1,STACK_FRAME_OVERHEAD
672 bl restore_interrupts
673 addi r3,r1,STACK_FRAME_OVERHEAD
678 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
679 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
682 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
685 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
686 mr r4,r1 /* src: current exception frame */
687 mr r1,r3 /* Reroute the trampoline frame to r1 */
689 /* Copy from the original to the trampoline. */
690 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
691 li r6,0 /* start offset: 0 */
698 /* Do real store operation to complete stwu */
702 /* Clear _TIF_EMULATE_STACK_STORE flag */
703 lis r11,_TIF_EMULATE_STACK_STORE@h
711 #ifdef CONFIG_PREEMPT
712 /* Check if we need to preempt */
713 andi. r0,r4,_TIF_NEED_RESCHED
715 /* Check that preempt_count() == 0 and interrupts are enabled */
716 lwz r8,TI_PREEMPT(r9)
720 crandc eq,cr1*4+eq,eq
724 * Here we are preempting the current task. We want to make
725 * sure we are soft-disabled first and reconcile irq state.
727 RECONCILE_IRQ_STATE(r3,r4)
728 1: bl preempt_schedule_irq
730 /* Re-test flags and eventually loop */
731 CURRENT_THREAD_INFO(r9, r1)
733 andi. r0,r4,_TIF_NEED_RESCHED
737 * arch_local_irq_restore() from preempt_schedule_irq above may
738 * enable hard interrupt but we really should disable interrupts
739 * when we return from the interrupt, and so that we don't get
740 * interrupted after loading SRR0/1.
742 #ifdef CONFIG_PPC_BOOK3E
745 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
746 mtmsrd r10,1 /* Update machine state */
747 #endif /* CONFIG_PPC_BOOK3E */
748 #endif /* CONFIG_PREEMPT */
750 .globl fast_exc_return_irq
754 * This is the main kernel exit path. First we check if we
755 * are about to re-enable interrupts
758 lbz r6,PACASOFTIRQEN(r13)
762 /* We are enabling, were we already enabled ? Yes, just return */
767 * We are about to soft-enable interrupts (we are hard disabled
768 * at this point). We check if there's anything that needs to
771 lbz r0,PACAIRQHAPPENED(r13)
773 bne- restore_check_irq_replay
776 * Get here when nothing happened while soft-disabled, just
777 * soft-enable and move-on. We will hard-enable as a side
783 stb r0,PACASOFTIRQEN(r13);
786 * Final return path. BookE is handled in a different file
789 #ifdef CONFIG_PPC_BOOK3E
790 b exception_return_book3e
793 * Clear the reservation. If we know the CPU tracks the address of
794 * the reservation then we can potentially save some cycles and use
795 * a larx. On POWER6 and POWER7 this is significantly faster.
798 stdcx. r0,0,r1 /* to clear the reservation */
801 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
804 * Some code path such as load_up_fpu or altivec return directly
805 * here. They run entirely hard disabled and do not alter the
806 * interrupt state. They also don't use lwarx/stwcx. and thus
807 * are known not to leave dangling reservations.
809 .globl fast_exception_return
810 fast_exception_return:
824 /* Load PPR from thread struct before we clear MSR:RI */
826 ld r2,PACACURRENT(r13)
827 ld r2,TASKTHREADPPR(r2)
828 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
831 * Clear RI before restoring r13. If we are returning to
832 * userspace and we take an exception after restoring r13,
833 * we end up corrupting the userspace r13 value.
835 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
836 andc r4,r4,r0 /* r0 contains MSR_RI here */
839 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
841 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
844 * r13 is our per cpu area, only restore it if we are returning to
845 * userspace the value stored in the stack frame may belong to
851 mtspr SPRN_PPR,r2 /* Restore PPR */
852 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
853 ACCOUNT_CPU_USER_EXIT(r2, r4)
870 b . /* prevent speculative execution */
872 #endif /* CONFIG_PPC_BOOK3E */
875 * We are returning to a context with interrupts soft disabled.
877 * However, we may also about to hard enable, so we need to
878 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
879 * or that bit can get out of sync and bad things will happen
883 lbz r7,PACAIRQHAPPENED(r13)
886 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
887 stb r7,PACAIRQHAPPENED(r13)
889 stb r0,PACASOFTIRQEN(r13);
894 * Something did happen, check if a re-emit is needed
895 * (this also clears paca->irq_happened)
897 restore_check_irq_replay:
898 /* XXX: We could implement a fast path here where we check
899 * for irq_happened being just 0x01, in which case we can
900 * clear it and return. That means that we would potentially
901 * miss a decrementer having wrapped all the way around.
903 * Still, this might be useful for things like hash_page
905 bl __check_irq_replay
907 beq restore_no_replay
910 * We need to re-emit an interrupt. We do so by re-using our
911 * existing exception frame. We first change the trap value,
912 * but we need to ensure we preserve the low nibble of it
920 * Then find the right handler and call it. Interrupts are
921 * still soft-disabled and we keep them that way.
925 addi r3,r1,STACK_FRAME_OVERHEAD;
928 1: cmpwi cr0,r3,0x900
930 addi r3,r1,STACK_FRAME_OVERHEAD;
933 #ifdef CONFIG_PPC_DOORBELL
935 #ifdef CONFIG_PPC_BOOK3E
942 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
943 #endif /* CONFIG_PPC_BOOK3E */
945 addi r3,r1,STACK_FRAME_OVERHEAD;
946 bl doorbell_exception
948 #endif /* CONFIG_PPC_DOORBELL */
949 1: b ret_from_except /* What else to do here ? */
952 addi r3,r1,STACK_FRAME_OVERHEAD
953 bl unrecoverable_exception
956 #ifdef CONFIG_PPC_RTAS
958 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
959 * called with the MMU off.
961 * In addition, we need to be in 32b mode, at least for now.
963 * Note: r3 is an input parameter to rtas, so don't trash it...
968 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
970 /* Because RTAS is running in 32b mode, it clobbers the high order half
971 * of all registers that it saves. We therefore save those registers
972 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
974 SAVE_GPR(2, r1) /* Save the TOC */
975 SAVE_GPR(13, r1) /* Save paca */
976 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
977 SAVE_10GPRS(22, r1) /* ditto */
990 /* Temporary workaround to clear CR until RTAS can be modified to
997 /* There is no way it is acceptable to get here with interrupts enabled,
998 * check it with the asm equivalent of WARN_ON
1000 lbz r0,PACASOFTIRQEN(r13)
1002 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1005 /* Hard-disable interrupts */
1011 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1012 * so they are saved in the PACA which allows us to restore
1013 * our original state after RTAS returns.
1016 std r6,PACASAVEDMSR(r13)
1018 /* Setup our real return addr */
1019 LOAD_REG_ADDR(r4,rtas_return_loc)
1020 clrldi r4,r4,2 /* convert to realmode address */
1024 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1028 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1029 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1031 sync /* disable interrupts so SRR0/1 */
1032 mtmsrd r0 /* don't get trashed */
1034 LOAD_REG_ADDR(r4, rtas)
1035 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1036 ld r4,RTASBASE(r4) /* get the rtas->base value */
1041 b . /* prevent speculative execution */
1046 /* relocation is off at this point */
1048 clrldi r4,r4,2 /* convert to realmode address */
1052 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1060 ld r1,PACAR1(r4) /* Restore our SP */
1061 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1066 b . /* prevent speculative execution */
1069 1: .llong rtas_restore_regs
1072 /* relocation is on at this point */
1073 REST_GPR(2, r1) /* Restore the TOC */
1074 REST_GPR(13, r1) /* Restore paca */
1075 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1076 REST_10GPRS(22, r1) /* ditto */
1091 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1092 ld r0,16(r1) /* get return address */
1095 blr /* return to caller */
1097 #endif /* CONFIG_PPC_RTAS */
1102 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1104 /* Because PROM is running in 32b mode, it clobbers the high order half
1105 * of all registers that it saves. We therefore save those registers
1106 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1117 /* Put PROM address in SRR0 */
1120 /* Setup our trampoline return addr in LR */
1123 addi r4,r4,(1f - 0b)
1126 /* Prepare a 32-bit mode big endian MSR
1128 #ifdef CONFIG_PPC_BOOK3E
1129 rlwinm r11,r11,0,1,31
1132 #else /* CONFIG_PPC_BOOK3E */
1133 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1137 #endif /* CONFIG_PPC_BOOK3E */
1139 1: /* Return from OF */
1142 /* Just make sure that r1 top 32 bits didn't get
1147 /* Restore the MSR (back to 64 bits) */
1152 /* Restore other registers */
1160 addi r1,r1,PROM_FRAME_SIZE
1165 #ifdef CONFIG_FUNCTION_TRACER
1166 #ifdef CONFIG_DYNAMIC_FTRACE
1171 _GLOBAL_TOC(ftrace_caller)
1172 /* Taken from output of objdump from lib64/glibc */
1178 subi r3, r3, MCOUNT_INSN_SIZE
1183 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1184 .globl ftrace_graph_call
1187 _GLOBAL(ftrace_graph_stub)
1192 _GLOBAL(ftrace_stub)
1195 _GLOBAL_TOC(_mcount)
1196 /* Taken from output of objdump from lib64/glibc */
1203 subi r3, r3, MCOUNT_INSN_SIZE
1204 LOAD_REG_ADDR(r5,ftrace_trace_function)
1212 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1213 b ftrace_graph_caller
1218 _GLOBAL(ftrace_stub)
1221 #endif /* CONFIG_DYNAMIC_FTRACE */
1223 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1224 _GLOBAL(ftrace_graph_caller)
1225 /* load r4 with local address */
1227 subi r4, r4, MCOUNT_INSN_SIZE
1229 /* get the parent address */
1233 bl prepare_ftrace_return
1241 _GLOBAL(return_to_handler)
1242 /* need to save return values */
1249 bl ftrace_return_to_handler
1252 /* return value has real return address */
1260 /* Jump back to real return address */
1263 _GLOBAL(mod_return_to_handler)
1264 /* need to save return values */
1274 * We are in a module using the module's TOC.
1275 * Switch to our TOC to run inside the core kernel.
1279 bl ftrace_return_to_handler
1282 /* return value has real return address */
1291 /* Jump back to real return address */
1293 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1294 #endif /* CONFIG_FUNCTION_TRACER */