2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
10 * Most of this originates from head_64.S and thus has the same
15 #include <asm/hw_irq.h>
16 #include <asm/exception-64s.h>
17 #include <asm/ptrace.h>
18 #include <asm/cpuidle.h>
19 #include <asm/head-64.h>
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
30 * - Conditional branch targets must be within +/-32K of caller.
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
45 * It's impossible to receive interrupts below 0x300 via AIL.
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
61 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
62 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
63 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
64 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
65 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
67 * Data area reserved for FWNMI option.
68 * This address (0x7000) is fixed by the RPA.
69 * pseries and powernv need to keep the whole page from
70 * 0x7000 to 0x8000 free for use by the firmware
72 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
73 OPEN_TEXT_SECTION(0x8000)
75 OPEN_TEXT_SECTION(0x7000)
78 USE_FIXED_SECTION(real_vectors)
80 #define LOAD_SYSCALL_HANDLER(reg) \
81 ld reg,PACAKBASE(r13); \
82 ori reg,reg,(ABS_ADDR(system_call_common))@l;
84 /* Syscall routine is used twice, in reloc-off and reloc-on paths */
85 #define SYSCALL_PSERIES_1 \
89 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
92 mfspr r11,SPRN_SRR0 ; \
95 #define SYSCALL_PSERIES_2_RFID \
96 mfspr r12,SPRN_SRR1 ; \
97 LOAD_SYSCALL_HANDLER(r10) ; \
98 mtspr SPRN_SRR0,r10 ; \
99 ld r10,PACAKMSR(r13) ; \
100 mtspr SPRN_SRR1,r10 ; \
102 b . ; /* prevent speculative execution */
104 #define SYSCALL_PSERIES_3 \
105 /* Fast LE/BE switch system call */ \
106 1: mfspr r12,SPRN_SRR1 ; \
107 xori r12,r12,MSR_LE ; \
108 mtspr SPRN_SRR1,r12 ; \
109 rfid ; /* return to userspace */ \
110 b . ; /* prevent speculative execution */
112 #if defined(CONFIG_RELOCATABLE)
114 * We can't branch directly so we do it via the CTR which
115 * is volatile across system calls.
117 #define SYSCALL_PSERIES_2_DIRECT \
118 LOAD_SYSCALL_HANDLER(r12) ; \
120 mfspr r12,SPRN_SRR1 ; \
125 /* We can branch directly */
126 #define SYSCALL_PSERIES_2_DIRECT \
127 mfspr r12,SPRN_SRR1 ; \
129 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
130 b system_call_common ;
134 * This is the start of the interrupt handlers for pSeries
135 * This code runs with relocation off.
136 * Code from here to __end_interrupts gets copied down to real
137 * address 0x100 when we are running a relocatable kernel.
138 * Therefore any relative branches in this section must only
139 * branch to labels in this section.
141 .globl __start_interrupts
144 EXC_REAL_BEGIN(system_reset, 0x100, 0x200)
146 #ifdef CONFIG_PPC_P7_NAP
148 /* Running native on arch 2.06 or later, check if we are
149 * waking up from nap/sleep/winkle.
152 rlwinm. r13,r13,47-31,30,31
157 bl pnv_restore_hyp_resource
159 li r0,PNV_THREAD_RUNNING
160 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
162 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
163 li r0,KVM_HWTHREAD_IN_KERNEL
164 stb r0,HSTATE_HWTHREAD_STATE(r13)
165 /* Order setting hwthread_state vs. testing hwthread_req */
167 lbz r0,HSTATE_HWTHREAD_REQ(r13)
174 /* Return SRR1 from power7_nap() */
178 2: b pnv_wakeup_noloss
181 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
182 #endif /* CONFIG_PPC_P7_NAP */
183 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
185 EXC_REAL_END(system_reset, 0x100, 0x200)
186 EXC_VIRT_NONE(0x4100, 0x4200)
187 EXC_COMMON(system_reset_common, 0x100, system_reset_exception)
189 #ifdef CONFIG_PPC_PSERIES
191 * Vectors for the FWNMI option. Share common code.
193 TRAMP_REAL_BEGIN(system_reset_fwnmi)
194 SET_SCRATCH0(r13) /* save r13 */
195 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
197 #endif /* CONFIG_PPC_PSERIES */
200 EXC_REAL_BEGIN(machine_check, 0x200, 0x300)
201 /* This is moved out of line as it can be patched by FW, but
202 * some code path might still want to branch into the original
205 SET_SCRATCH0(r13) /* save r13 */
207 * Running native on arch 2.06 or later, we may wakeup from winkle
208 * inside machine check. If yes, then last bit of HSPGR0 would be set
209 * to 1. Hence clear it unconditionally.
214 EXCEPTION_PROLOG_0(PACA_EXMC)
216 b machine_check_powernv_early
218 b machine_check_pSeries_0
219 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
220 EXC_REAL_END(machine_check, 0x200, 0x300)
221 EXC_VIRT_NONE(0x4200, 0x4300)
222 TRAMP_REAL_BEGIN(machine_check_powernv_early)
224 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
229 * Original R9 to R13 is saved on PACA_EXMC
231 * Switch to mc_emergency stack and handle re-entrancy (we limit
232 * the nested MCE upto level 4 to avoid stack overflow).
233 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
235 * We use paca->in_mce to check whether this is the first entry or
236 * nested machine check. We increment paca->in_mce to track nested
239 * If this is the first entry then set stack pointer to
240 * paca->mc_emergency_sp, otherwise r1 is already pointing to
241 * stack frame on mc_emergency stack.
243 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
244 * checkstop if we get another machine check exception before we do
245 * rfid with MSR_ME=1.
247 mr r11,r1 /* Save r1 */
248 lhz r10,PACA_IN_MCE(r13)
249 cmpwi r10,0 /* Are we in nested machine check */
250 bne 0f /* Yes, we are. */
251 /* First machine check entry */
252 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
253 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
254 addi r10,r10,1 /* increment paca->in_mce */
255 sth r10,PACA_IN_MCE(r13)
256 /* Limit nested MCE to level 4 to avoid stack overflow */
258 bgt 2f /* Check if we hit limit of 4 */
259 std r11,GPR1(r1) /* Save r1 on the stack. */
260 std r11,0(r1) /* make stack chain pointer */
261 mfspr r11,SPRN_SRR0 /* Save SRR0 */
263 mfspr r11,SPRN_SRR1 /* Save SRR1 */
265 mfspr r11,SPRN_DAR /* Save DAR */
267 mfspr r11,SPRN_DSISR /* Save DSISR */
269 std r9,_CCR(r1) /* Save CR in stackframe */
270 /* Save r9 through r13 from EXMC save area to stack frame. */
271 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
272 mfmsr r11 /* get MSR value */
273 ori r11,r11,MSR_ME /* turn on ME bit */
274 ori r11,r11,MSR_RI /* turn on RI bit */
275 LOAD_HANDLER(r12, machine_check_handle_early)
276 1: mtspr SPRN_SRR0,r12
279 b . /* prevent speculative execution */
281 /* Stack overflow. Stay on emergency stack and panic.
282 * Keep the ME bit off while panic-ing, so that if we hit
283 * another machine check we checkstop.
285 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
287 LOAD_HANDLER(r12, unrecover_mce)
289 andc r11,r11,r10 /* Turn off MSR_ME */
291 b . /* prevent speculative execution */
292 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
294 TRAMP_REAL_BEGIN(machine_check_pSeries)
295 .globl machine_check_fwnmi
297 SET_SCRATCH0(r13) /* save r13 */
298 EXCEPTION_PROLOG_0(PACA_EXMC)
299 machine_check_pSeries_0:
300 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
302 * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the
303 * difference that MSR_RI is not enabled, because PACA_EXMC is being
304 * used, so nested machine check corrupts it. machine_check_common
310 LOAD_HANDLER(r12, machine_check_common)
315 b . /* prevent speculative execution */
317 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
319 EXC_COMMON_BEGIN(machine_check_common)
321 * Machine check is different because we use a different
322 * save area: PACA_EXMC instead of PACA_EXGEN.
325 std r10,PACA_EXMC+EX_DAR(r13)
327 stw r10,PACA_EXMC+EX_DSISR(r13)
328 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
330 RECONCILE_IRQ_STATE(r10, r11)
331 ld r3,PACA_EXMC+EX_DAR(r13)
332 lwz r4,PACA_EXMC+EX_DSISR(r13)
333 /* Enable MSR_RI when finished with PACA_EXMC */
339 addi r3,r1,STACK_FRAME_OVERHEAD
340 bl machine_check_exception
343 #define MACHINE_CHECK_HANDLER_WINDUP \
344 /* Clear MSR_RI before setting SRR0 and SRR1. */\
346 mfmsr r9; /* get MSR value */ \
348 mtmsrd r9,1; /* Clear MSR_RI */ \
349 /* Move original SRR0 and SRR1 into the respective regs */ \
351 mtspr SPRN_SRR1,r9; \
353 mtspr SPRN_SRR0,r3; \
365 /* Decrement paca->in_mce. */ \
366 lhz r12,PACA_IN_MCE(r13); \
368 sth r12,PACA_IN_MCE(r13); \
370 REST_2GPRS(12, r1); \
371 /* restore original r1. */ \
375 * Handle machine check early in real mode. We come here with
376 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
378 EXC_COMMON_BEGIN(machine_check_handle_early)
379 std r0,GPR0(r1) /* Save r0 */
380 EXCEPTION_PROLOG_COMMON_3(0x200)
382 addi r3,r1,STACK_FRAME_OVERHEAD
383 bl machine_check_early
384 std r3,RESULT(r1) /* Save result */
386 #ifdef CONFIG_PPC_P7_NAP
388 * Check if thread was in power saving mode. We come here when any
389 * of the following is true:
390 * a. thread wasn't in power saving mode
391 * b. thread was in power saving mode with no state loss,
392 * supervisor state loss or hypervisor state loss.
394 * Go back to nap/sleep/winkle mode again if (b) is true.
396 rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */
397 beq 4f /* No, it wasn;t */
398 /* Thread was in power saving mode. Go back to nap again. */
401 /* Supervisor/Hypervisor state loss */
403 stb r0,PACA_NAPSTATELOST(r13)
404 3: bl machine_check_queue_event
405 MACHINE_CHECK_HANDLER_WINDUP
409 * Check what idle state this CPU was in and go back to same mode
412 lbz r3,PACA_THREAD_IDLE_STATE(r13)
413 cmpwi r3,PNV_THREAD_NAP
415 IDLE_STATE_ENTER_SEQ(PPC_NAP)
418 cmpwi r3,PNV_THREAD_SLEEP
420 IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
425 * Go back to winkle. Please note that this thread was woken up in
426 * machine check from winkle and have not restored the per-subcore
427 * state. Hence before going back to winkle, set last bit of HSPGR0
428 * to 1. This will make sure that if this thread gets woken up
429 * again at reset vector 0x100 then it will get chance to restore
434 IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
439 * Check if we are coming from hypervisor userspace. If yes then we
440 * continue in host kernel in V mode to deliver the MC event.
442 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
444 andi. r11,r12,MSR_PR /* See if coming from user. */
445 bne 9f /* continue in V mode if we are. */
448 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
450 * We are coming from kernel context. Check if we are coming from
451 * guest. if yes, then we can continue. We will fall through
452 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
454 lbz r11,HSTATE_IN_GUEST(r13)
455 cmpwi r11,0 /* Check if coming from guest */
456 bne 9f /* continue if we are. */
459 * At this point we are not sure about what context we come from.
460 * Queue up the MCE event and return from the interrupt.
461 * But before that, check if this is an un-recoverable exception.
462 * If yes, then stay on emergency stack and panic.
466 1: mfspr r11,SPRN_SRR0
467 LOAD_HANDLER(r10,unrecover_mce)
471 * We are going down. But there are chances that we might get hit by
472 * another MCE during panic path and we may run into unstable state
473 * with no way out. Hence, turn ME bit off while going down, so that
474 * when another MCE is hit during panic path, system will checkstop
475 * and hypervisor will get restarted cleanly by SP.
478 andc r10,r10,r3 /* Turn off MSR_ME */
484 * Check if we have successfully handled/recovered from error, if not
485 * then stay on emergency stack and panic.
487 ld r3,RESULT(r1) /* Load result */
488 cmpdi r3,0 /* see if we handled MCE successfully */
490 beq 1b /* if !handled then panic */
492 * Return from MC interrupt.
493 * Queue up the MCE event so that we can log it later, while
494 * returning from kernel or opal call.
496 bl machine_check_queue_event
497 MACHINE_CHECK_HANDLER_WINDUP
500 /* Deliver the machine check to host kernel in V mode. */
501 MACHINE_CHECK_HANDLER_WINDUP
502 b machine_check_pSeries
504 EXC_COMMON_BEGIN(unrecover_mce)
505 /* Invoke machine_check_exception to print MCE event and panic. */
506 addi r3,r1,STACK_FRAME_OVERHEAD
507 bl machine_check_exception
509 * We will not reach here. Even if we did, there is no way out. Call
510 * unrecoverable_exception and die.
512 1: addi r3,r1,STACK_FRAME_OVERHEAD
513 bl unrecoverable_exception
517 EXC_REAL(data_access, 0x300, 0x380)
518 EXC_VIRT(data_access, 0x4300, 0x4380, 0x300)
519 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
521 EXC_COMMON_BEGIN(data_access_common)
523 * Here r13 points to the paca, r9 contains the saved CR,
524 * SRR0 and SRR1 are saved in r11 and r12,
525 * r9 - r13 are saved in paca->exgen.
528 std r10,PACA_EXGEN+EX_DAR(r13)
530 stw r10,PACA_EXGEN+EX_DSISR(r13)
531 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
532 RECONCILE_IRQ_STATE(r10, r11)
534 ld r3,PACA_EXGEN+EX_DAR(r13)
535 lwz r4,PACA_EXGEN+EX_DSISR(r13)
539 BEGIN_MMU_FTR_SECTION
540 b do_hash_page /* Try to handle as hpte fault */
543 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
546 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400)
548 EXCEPTION_PROLOG_0(PACA_EXSLB)
549 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
550 std r3,PACA_EXSLB+EX_R3(r13)
554 #ifndef CONFIG_RELOCATABLE
558 * We can't just use a direct branch to slb_miss_realmode
559 * because the distance from here to there depends on where
560 * the kernel ends up being put.
563 LOAD_HANDLER(r10, slb_miss_realmode)
567 EXC_REAL_END(data_access_slb, 0x380, 0x400)
569 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400)
571 EXCEPTION_PROLOG_0(PACA_EXSLB)
572 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
573 std r3,PACA_EXSLB+EX_R3(r13)
577 #ifndef CONFIG_RELOCATABLE
581 * We can't just use a direct branch to slb_miss_realmode
582 * because the distance from here to there depends on where
583 * the kernel ends up being put.
586 LOAD_HANDLER(r10, slb_miss_realmode)
590 EXC_VIRT_END(data_access_slb, 0x4380, 0x4400)
591 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
594 EXC_REAL(instruction_access, 0x400, 0x480)
596 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500)
598 EXCEPTION_PROLOG_0(PACA_EXSLB)
599 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
600 std r3,PACA_EXSLB+EX_R3(r13)
601 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
604 #ifndef CONFIG_RELOCATABLE
608 LOAD_HANDLER(r10, slb_miss_realmode)
612 EXC_REAL_END(instruction_access_slb, 0x480, 0x500)
614 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600)
615 .globl hardware_interrupt_hv;
616 hardware_interrupt_hv:
618 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
619 EXC_HV, SOFTEN_TEST_HV)
621 KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502)
623 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
624 EXC_STD, SOFTEN_TEST_PR)
626 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500)
627 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
628 EXC_REAL_END(hardware_interrupt, 0x500, 0x600)
630 EXC_REAL(alignment, 0x600, 0x700)
632 TRAMP_KVM(PACA_EXGEN, 0x600)
634 EXC_REAL(program_check, 0x700, 0x800)
636 TRAMP_KVM(PACA_EXGEN, 0x700)
638 EXC_REAL(fp_unavailable, 0x800, 0x900)
640 TRAMP_KVM(PACA_EXGEN, 0x800)
642 EXC_REAL_MASKABLE(decrementer, 0x900, 0x980)
644 EXC_REAL_HV(hdecrementer, 0x980, 0xa00)
646 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00)
648 TRAMP_KVM(PACA_EXGEN, 0xa00)
650 EXC_REAL(trap_0b, 0xb00, 0xc00)
652 TRAMP_KVM(PACA_EXGEN, 0xb00)
654 EXC_REAL_BEGIN(system_call, 0xc00, 0xd00)
656 * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems
657 * that support it) before changing to HMT_MEDIUM. That allows the KVM
658 * code to save that value into the guest state (it is the guest's PPR
659 * value). Otherwise just change to HMT_MEDIUM as userspace has
660 * already saved the PPR.
662 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
665 std r9,PACA_EXGEN+EX_R9(r13)
666 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR);
668 std r10,PACA_EXGEN+EX_R10(r13)
669 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR);
677 SYSCALL_PSERIES_2_RFID
679 EXC_REAL_END(system_call, 0xc00, 0xd00)
681 TRAMP_KVM(PACA_EXGEN, 0xc00)
683 EXC_REAL(single_step, 0xd00, 0xe00)
685 TRAMP_KVM(PACA_EXGEN, 0xd00)
688 /* At 0xe??? we have a bunch of hypervisor exceptions, we branch
689 * out of line to handle them
691 __EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20)
693 __EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40)
695 __EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60)
697 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early)
699 __EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0)
701 __EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0)
703 EXC_REAL_NONE(0xec0, 0xf00)
705 __EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20)
707 __EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40)
709 __EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60)
711 __EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80)
713 __EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0)
715 EXC_REAL_NONE(0xfa0, 0x1200)
717 #ifdef CONFIG_CBE_RAS
718 EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300)
720 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
722 #else /* CONFIG_CBE_RAS */
723 EXC_REAL_NONE(0x1200, 0x1300)
726 EXC_REAL(instruction_breakpoint, 0x1300, 0x1400)
728 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
730 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600)
731 mtspr SPRN_SPRG_HSCRATCH0,r13
732 EXCEPTION_PROLOG_0(PACA_EXGEN)
733 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
735 #ifdef CONFIG_PPC_DENORMALISATION
737 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
738 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
739 addi r11,r11,-4 /* HSRR0 is next instruction */
744 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
745 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600)
747 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
749 #ifdef CONFIG_CBE_RAS
750 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700)
752 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
754 #else /* CONFIG_CBE_RAS */
755 EXC_REAL_NONE(0x1600, 0x1700)
758 EXC_REAL(altivec_assist, 0x1700, 0x1800)
760 TRAMP_KVM(PACA_EXGEN, 0x1700)
762 #ifdef CONFIG_CBE_RAS
763 EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900)
765 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
767 #else /* CONFIG_CBE_RAS */
768 EXC_REAL_NONE(0x1800, 0x1900)
772 /*** Out of line interrupts support ***/
774 /* moved from 0x200 */
775 TRAMP_KVM(PACA_EXGEN, 0x400)
776 TRAMP_KVM(PACA_EXSLB, 0x480)
777 TRAMP_KVM(PACA_EXGEN, 0x900)
778 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
780 #ifdef CONFIG_PPC_DENORMALISATION
781 TRAMP_REAL_BEGIN(denorm_assist)
784 * To denormalise we need to move a copy of the register to itself.
785 * For POWER6 do that here for all FP regs.
788 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
789 xori r10,r10,(MSR_FE0|MSR_FE1)
793 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
794 #define FMR4(n) FMR2(n) ; FMR2(n+2)
795 #define FMR8(n) FMR4(n) ; FMR4(n+4)
796 #define FMR16(n) FMR8(n) ; FMR8(n+8)
797 #define FMR32(n) FMR16(n) ; FMR16(n+16)
802 * To denormalise we need to move a copy of the register to itself.
803 * For POWER7 do that here for the first 32 VSX registers only.
806 oris r10,r10,MSR_VSX@h
810 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
811 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
812 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
813 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
814 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
817 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
821 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
823 * To denormalise we need to move a copy of the register to itself.
824 * For POWER8 we need to do that for all 64 VSX registers
830 ld r9,PACA_EXGEN+EX_R9(r13)
831 RESTORE_PPR_PACA(PACA_EXGEN, r10)
833 ld r10,PACA_EXGEN+EX_CFAR(r13)
835 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
836 ld r10,PACA_EXGEN+EX_R10(r13)
837 ld r11,PACA_EXGEN+EX_R11(r13)
838 ld r12,PACA_EXGEN+EX_R12(r13)
839 ld r13,PACA_EXGEN+EX_R13(r13)
844 /* moved from 0xe00 */
845 __TRAMP_REAL_REAL_OOL_HV(h_data_storage, 0xe00)
846 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
848 __TRAMP_REAL_REAL_OOL_HV(h_instr_storage, 0xe20)
849 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
851 __TRAMP_REAL_REAL_OOL_HV(emulation_assist, 0xe40)
852 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
854 __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
855 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
857 __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80)
858 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
860 __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0)
861 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
863 /* moved from 0xf00 */
864 __TRAMP_REAL_REAL_OOL(performance_monitor, 0xf00)
865 TRAMP_KVM(PACA_EXGEN, 0xf00)
867 __TRAMP_REAL_REAL_OOL(altivec_unavailable, 0xf20)
868 TRAMP_KVM(PACA_EXGEN, 0xf20)
870 __TRAMP_REAL_REAL_OOL(vsx_unavailable, 0xf40)
871 TRAMP_KVM(PACA_EXGEN, 0xf40)
873 __TRAMP_REAL_REAL_OOL(facility_unavailable, 0xf60)
874 TRAMP_KVM(PACA_EXGEN, 0xf60)
876 __TRAMP_REAL_REAL_OOL_HV(h_facility_unavailable, 0xf80)
877 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
880 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
881 * - If it was a decrementer interrupt, we bump the dec to max and and return.
882 * - If it was a doorbell we return immediately since doorbells are edge
883 * triggered and won't automatically refire.
884 * - If it was a HMI we return immediately since we handled it in realmode
885 * and it won't refire.
886 * - else we hard disable and return.
887 * This is called with r10 containing the value to OR to the paca field.
889 #define MASKED_INTERRUPT(_H) \
890 masked_##_H##interrupt: \
891 std r11,PACA_EXGEN+EX_R11(r13); \
892 lbz r11,PACAIRQHAPPENED(r13); \
894 stb r11,PACAIRQHAPPENED(r13); \
895 cmpwi r10,PACA_IRQ_DEC; \
898 ori r10,r10,0xffff; \
899 mtspr SPRN_DEC,r10; \
901 1: cmpwi r10,PACA_IRQ_DBELL; \
903 cmpwi r10,PACA_IRQ_HMI; \
905 mfspr r10,SPRN_##_H##SRR1; \
906 rldicl r10,r10,48,1; /* clear MSR_EE */ \
908 mtspr SPRN_##_H##SRR1,r10; \
910 ld r9,PACA_EXGEN+EX_R9(r13); \
911 ld r10,PACA_EXGEN+EX_R10(r13); \
912 ld r11,PACA_EXGEN+EX_R11(r13); \
918 * Real mode exceptions actually use this too, but alternate
919 * instruction code patches (which end up in the common .text area)
920 * cannot reach these if they are put there.
922 USE_FIXED_SECTION(virt_trampolines)
927 * Called from arch_local_irq_enable when an interrupt needs
928 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
929 * which kind of interrupt. MSR:EE is already off. We generate a
930 * stackframe like if a real interrupt had happened.
932 * Note: While MSR:EE is off, we need to make sure that _MSR
933 * in the generated frame has EE set to 1 or the exception
934 * handler will not properly re-enable them.
937 _GLOBAL(__replay_interrupt)
938 /* We are going to jump to the exception common code which
939 * will retrieve various register values from the PACA which
940 * we don't give a damn about, so we don't bother storing them.
947 beq decrementer_common
949 beq hardware_interrupt_common
952 beq h_doorbell_common
954 beq h_virt_irq_common
956 beq hmi_exception_common
959 beq doorbell_super_common
960 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
963 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
964 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
966 * Here all GPRs are unchanged from when the interrupt happened
967 * except for r13, which is saved in SPRG_SCRATCH0.
976 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
978 * Here all GPRs are unchanged from when the interrupt happened
979 * except for r13, which is saved in SPRG_SCRATCH0.
981 mfspr r13, SPRN_HSRR0
983 mtspr SPRN_HSRR0, r13
990 * Ensure that any handlers that get invoked from the exception prologs
991 * above are below the first 64KB (0x10000) of the kernel image because
992 * the prologs assemble the addresses of these handlers using the
993 * LOAD_HANDLER macro, which uses an ori instruction.
996 /*** Common interrupt handlers ***/
998 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
999 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
1000 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
1002 #ifdef CONFIG_PPC_DOORBELL
1003 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
1005 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
1007 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
1008 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1009 EXC_COMMON(trap_0e_common, 0xe00, unknown_exception)
1010 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1011 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1012 #ifdef CONFIG_PPC_DOORBELL
1013 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1015 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1017 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1018 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1019 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1020 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1021 #ifdef CONFIG_ALTIVEC
1022 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1024 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1028 * Relocation-on interrupts: A subset of the interrupts can be delivered
1029 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1030 * it. Addresses are the same as the original interrupt addresses, but
1031 * offset by 0xc000000000004000.
1032 * It's impossible to receive interrupts below 0x300 via this mechanism.
1033 * KVM: None of these traps are from the guest ; anything that escalated
1034 * to HV=1 from HV=0 is delivered via real mode handlers.
1038 * This uses the standard macro, since the original 0x300 vector
1039 * only has extra guff for STAB-based processors -- which never
1043 EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400)
1045 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500)
1047 EXCEPTION_PROLOG_0(PACA_EXSLB)
1048 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
1049 std r3,PACA_EXSLB+EX_R3(r13)
1050 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
1053 #ifndef CONFIG_RELOCATABLE
1057 LOAD_HANDLER(r10, slb_miss_realmode)
1061 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500)
1063 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600)
1064 .globl hardware_interrupt_relon_hv;
1065 hardware_interrupt_relon_hv:
1067 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
1069 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
1070 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1071 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600)
1073 EXC_VIRT(alignment, 0x4600, 0x4700, 0x600)
1074 EXC_VIRT(program_check, 0x4700, 0x4800, 0x700)
1075 EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800)
1076 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900)
1077 EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980)
1078 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00)
1079 EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00)
1081 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00)
1084 SYSCALL_PSERIES_2_DIRECT
1086 EXC_VIRT_END(system_call, 0x4c00, 0x4d00)
1088 EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00)
1090 EXC_VIRT_BEGIN(unused, 0x4e00, 0x4e20)
1091 b . /* Can't happen, see v2.07 Book III-S section 6.5 */
1092 EXC_VIRT_END(unused, 0x4e00, 0x4e20)
1094 EXC_VIRT_BEGIN(unused, 0x4e20, 0x4e40)
1095 b . /* Can't happen, see v2.07 Book III-S section 6.5 */
1096 EXC_VIRT_END(unused, 0x4e20, 0x4e40)
1098 __EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60)
1100 EXC_VIRT_BEGIN(unused, 0x4e60, 0x4e80)
1101 b . /* Can't happen, see v2.07 Book III-S section 6.5 */
1102 EXC_VIRT_END(unused, 0x4e60, 0x4e80)
1104 __EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0)
1106 __EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0)
1108 EXC_VIRT_NONE(0x4ec0, 0x4f00)
1110 __EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20)
1112 __EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40)
1114 __EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60)
1116 __EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80)
1118 __EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0)
1120 EXC_VIRT_NONE(0x4fa0, 0x5200)
1122 EXC_VIRT_NONE(0x5200, 0x5300)
1124 EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300)
1126 #ifdef CONFIG_PPC_DENORMALISATION
1127 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600)
1128 b exc_real_0x1500_denorm_exception_hv
1129 EXC_VIRT_END(denorm_exception, 0x5500, 0x5600)
1131 EXC_VIRT_NONE(0x5500, 0x5600)
1134 EXC_VIRT_NONE(0x5600, 0x5700)
1136 EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700)
1138 EXC_VIRT_NONE(0x5800, 0x5900)
1140 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1141 b __ppc64_runlatch_on
1143 EXC_COMMON_BEGIN(h_data_storage_common)
1145 std r10,PACA_EXGEN+EX_DAR(r13)
1146 mfspr r10,SPRN_HDSISR
1147 stw r10,PACA_EXGEN+EX_DSISR(r13)
1148 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
1150 RECONCILE_IRQ_STATE(r10, r11)
1151 addi r3,r1,STACK_FRAME_OVERHEAD
1152 bl unknown_exception
1155 EXC_COMMON_BEGIN(instruction_access_common)
1156 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
1157 RECONCILE_IRQ_STATE(r10, r11)
1160 andis. r4,r12,0x5820
1164 BEGIN_MMU_FTR_SECTION
1165 b do_hash_page /* Try to handle as hpte fault */
1166 MMU_FTR_SECTION_ELSE
1168 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1170 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1172 EXC_COMMON_BEGIN(alignment_common)
1174 std r10,PACA_EXGEN+EX_DAR(r13)
1175 mfspr r10,SPRN_DSISR
1176 stw r10,PACA_EXGEN+EX_DSISR(r13)
1177 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1178 ld r3,PACA_EXGEN+EX_DAR(r13)
1179 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1183 RECONCILE_IRQ_STATE(r10, r11)
1184 addi r3,r1,STACK_FRAME_OVERHEAD
1185 bl alignment_exception
1188 EXC_COMMON_BEGIN(program_check_common)
1189 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1191 RECONCILE_IRQ_STATE(r10, r11)
1192 addi r3,r1,STACK_FRAME_OVERHEAD
1193 bl program_check_exception
1196 EXC_COMMON_BEGIN(fp_unavailable_common)
1197 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1198 bne 1f /* if from user, just load it up */
1200 RECONCILE_IRQ_STATE(r10, r11)
1201 addi r3,r1,STACK_FRAME_OVERHEAD
1202 bl kernel_fp_unavailable_exception
1205 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1207 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1208 * transaction), go do TM stuff
1210 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1212 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1215 b fast_exception_return
1216 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1217 2: /* User process was in a transaction */
1219 RECONCILE_IRQ_STATE(r10, r11)
1220 addi r3,r1,STACK_FRAME_OVERHEAD
1221 bl fp_unavailable_tm
1225 EXC_COMMON_BEGIN(altivec_unavailable_common)
1226 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1227 #ifdef CONFIG_ALTIVEC
1230 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1231 BEGIN_FTR_SECTION_NESTED(69)
1232 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1233 * transaction), go do TM stuff
1235 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1237 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1240 b fast_exception_return
1241 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1242 2: /* User process was in a transaction */
1244 RECONCILE_IRQ_STATE(r10, r11)
1245 addi r3,r1,STACK_FRAME_OVERHEAD
1246 bl altivec_unavailable_tm
1250 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1253 RECONCILE_IRQ_STATE(r10, r11)
1254 addi r3,r1,STACK_FRAME_OVERHEAD
1255 bl altivec_unavailable_exception
1258 EXC_COMMON_BEGIN(vsx_unavailable_common)
1259 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1263 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1264 BEGIN_FTR_SECTION_NESTED(69)
1265 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1266 * transaction), go do TM stuff
1268 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1270 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1273 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1274 2: /* User process was in a transaction */
1276 RECONCILE_IRQ_STATE(r10, r11)
1277 addi r3,r1,STACK_FRAME_OVERHEAD
1278 bl vsx_unavailable_tm
1282 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1285 RECONCILE_IRQ_STATE(r10, r11)
1286 addi r3,r1,STACK_FRAME_OVERHEAD
1287 bl vsx_unavailable_exception
1290 /* Equivalents to the above handlers for relocation-on interrupt vectors */
1291 __TRAMP_REAL_VIRT_OOL_HV(emulation_assist, 0xe40)
1292 __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_doorbell, 0xe80)
1293 __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0xea0)
1294 __TRAMP_REAL_VIRT_OOL(performance_monitor, 0xf00)
1295 __TRAMP_REAL_VIRT_OOL(altivec_unavailable, 0xf20)
1296 __TRAMP_REAL_VIRT_OOL(vsx_unavailable, 0xf40)
1297 __TRAMP_REAL_VIRT_OOL(facility_unavailable, 0xf60)
1298 __TRAMP_REAL_VIRT_OOL_HV(h_facility_unavailable, 0xf80)
1300 USE_FIXED_SECTION(virt_trampolines)
1302 * The __end_interrupts marker must be past the out-of-line (OOL)
1303 * handlers, so that they are copied to real address 0x100 when running
1304 * a relocatable kernel. This ensures they can be reached from the short
1305 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1306 * directly, without using LOAD_HANDLER().
1309 .globl __end_interrupts
1311 DEFINE_FIXED_SYMBOL(__end_interrupts)
1313 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1314 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1316 #ifdef CONFIG_CBE_RAS
1317 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1318 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1319 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1320 #endif /* CONFIG_CBE_RAS */
1323 TRAMP_REAL_BEGIN(hmi_exception_early)
1324 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1325 mr r10,r1 /* Save r1 */
1326 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1327 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1328 std r9,_CCR(r1) /* save CR in stackframe */
1329 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1330 std r11,_NIP(r1) /* save HSRR0 in stackframe */
1331 mfspr r12,SPRN_HSRR1 /* Save SRR1 */
1332 std r12,_MSR(r1) /* save SRR1 in stackframe */
1333 std r10,0(r1) /* make stack chain pointer */
1334 std r0,GPR0(r1) /* save r0 in stackframe */
1335 std r10,GPR1(r1) /* save r1 in stackframe */
1336 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1337 EXCEPTION_PROLOG_COMMON_3(0xe60)
1338 addi r3,r1,STACK_FRAME_OVERHEAD
1339 bl hmi_exception_realmode
1340 /* Windup the stack. */
1341 /* Move original HSRR0 and HSRR1 into the respective regs */
1359 /* restore original r1. */
1363 * Go to virtual mode and pull the HMI event information from
1366 .globl hmi_exception_after_realmode
1367 hmi_exception_after_realmode:
1369 EXCEPTION_PROLOG_0(PACA_EXGEN)
1370 b tramp_real_hmi_exception
1373 * r13 points to the PACA, r9 contains the saved CR,
1374 * r12 contain the saved SRR1, SRR0 is still ready for return
1375 * r3 has the faulting address
1376 * r9 - r13 are saved in paca->exslb.
1377 * r3 is saved in paca->slb_r3
1378 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
1379 * We assume we aren't going to take any exceptions during this procedure.
1381 EXC_COMMON_BEGIN(slb_miss_realmode)
1383 #ifdef CONFIG_RELOCATABLE
1387 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1388 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1389 std r3,PACA_EXSLB+EX_DAR(r13)
1392 #ifdef CONFIG_PPC_STD_MMU_64
1393 BEGIN_MMU_FTR_SECTION
1394 bl slb_allocate_realmode
1395 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
1398 ld r10,PACA_EXSLB+EX_LR(r13)
1399 ld r3,PACA_EXSLB+EX_R3(r13)
1400 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1403 beq 8f /* if bad address, make full stack frame */
1405 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1408 /* All done -- return from exception. */
1413 mtcrf 0x02,r9 /* I/D indication is in cr6 */
1414 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1417 RESTORE_PPR_PACA(PACA_EXSLB, r9)
1418 ld r9,PACA_EXSLB+EX_R9(r13)
1419 ld r10,PACA_EXSLB+EX_R10(r13)
1420 ld r11,PACA_EXSLB+EX_R11(r13)
1421 ld r12,PACA_EXSLB+EX_R12(r13)
1422 ld r13,PACA_EXSLB+EX_R13(r13)
1424 b . /* prevent speculative execution */
1426 2: mfspr r11,SPRN_SRR0
1427 LOAD_HANDLER(r10,unrecov_slb)
1429 ld r10,PACAKMSR(r13)
1434 8: mfspr r11,SPRN_SRR0
1435 LOAD_HANDLER(r10,bad_addr_slb)
1437 ld r10,PACAKMSR(r13)
1442 EXC_COMMON_BEGIN(unrecov_slb)
1443 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1444 RECONCILE_IRQ_STATE(r10, r11)
1446 1: addi r3,r1,STACK_FRAME_OVERHEAD
1447 bl unrecoverable_exception
1451 EXC_COMMON_BEGIN(bad_addr_slb)
1452 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
1453 RECONCILE_IRQ_STATE(r10, r11)
1454 ld r3, PACA_EXSLB+EX_DAR(r13)
1457 li r10, 0x480 /* fix trap number for I-SLB miss */
1460 addi r3, r1, STACK_FRAME_OVERHEAD
1461 bl slb_miss_bad_addr
1464 #ifdef CONFIG_PPC_970_NAP
1465 TRAMP_REAL_BEGIN(power4_fixup_nap)
1467 std r9,TI_LOCAL_FLAGS(r11)
1468 ld r10,_LINK(r1) /* make idle task do the */
1469 std r10,_NIP(r1) /* equivalent of a blr */
1473 CLOSE_FIXED_SECTION(real_vectors);
1474 CLOSE_FIXED_SECTION(real_trampolines);
1475 CLOSE_FIXED_SECTION(virt_vectors);
1476 CLOSE_FIXED_SECTION(virt_trampolines);
1485 #ifdef CONFIG_PPC_STD_MMU_64
1486 andis. r0,r4,0xa410 /* weird error? */
1487 bne- handle_page_fault /* if not, try to insert a HPTE */
1488 andis. r0,r4,DSISR_DABRMATCH@h
1489 bne- handle_dabr_fault
1490 CURRENT_THREAD_INFO(r11, r1)
1491 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1492 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1493 bne 77f /* then don't call hash_page now */
1496 * r3 contains the faulting address
1498 * r5 contains the trap number
1501 * at return r3 = 0 for success, 1 for page fault, negative for error
1505 bl __hash_page /* build HPTE if possible */
1506 cmpdi r3,0 /* see if __hash_page succeeded */
1509 beq fast_exc_return_irq /* Return from exception on success */
1513 #endif /* CONFIG_PPC_STD_MMU_64 */
1515 /* Here we have a page fault that hash_page can't handle. */
1519 addi r3,r1,STACK_FRAME_OVERHEAD
1525 addi r3,r1,STACK_FRAME_OVERHEAD
1530 /* We have a data breakpoint exception - handle it */
1535 addi r3,r1,STACK_FRAME_OVERHEAD
1537 12: b ret_from_except_lite
1540 #ifdef CONFIG_PPC_STD_MMU_64
1541 /* We have a page fault that hash_page could handle but HV refused
1546 addi r3,r1,STACK_FRAME_OVERHEAD
1553 * We come here as a result of a DSI at a point where we don't want
1554 * to call hash_page, such as when we are accessing memory (possibly
1555 * user memory) inside a PMU interrupt that occurred while interrupts
1556 * were soft-disabled. We want to invoke the exception handler for
1557 * the access, or panic if there isn't a handler.
1561 addi r3,r1,STACK_FRAME_OVERHEAD
1567 * Here we have detected that the kernel stack pointer is bad.
1568 * R9 contains the saved CR, r13 points to the paca,
1569 * r10 contains the (bad) kernel stack pointer,
1570 * r11 and r12 contain the saved SRR0 and SRR1.
1571 * We switch to using an emergency stack, save the registers there,
1572 * and call kernel_bad_stack(), which panics.
1575 ld r1,PACAEMERGSP(r13)
1576 subi r1,r1,64+INT_FRAME_SIZE
1582 mfspr r12,SPRN_DSISR
1608 std r10,ORIG_GPR3(r1)
1609 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1612 lhz r12,PACA_TRAP_SAVE(r13)
1614 addi r11,r1,INT_FRAME_SIZE
1619 ld r11,exception_marker@toc(r2)
1621 std r11,STACK_FRAME_OVERHEAD-16(r1)
1622 1: addi r3,r1,STACK_FRAME_OVERHEAD