2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
25 #include <linux/vmalloc.h>
27 #include <asm/processor.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
35 unsigned long pci_probe_only = 1;
37 /* pci_io_base -- the base address from which io bars are offsets.
38 * This is the lowest I/O base address (so bar values are always positive),
39 * and it *must* be the start of ISA space if an ISA bus exists because
40 * ISA drivers use hard coded offsets. If no ISA bus exists nothing
41 * is mapped on the first 64K of IO space
43 unsigned long pci_io_base = ISA_IO_BASE;
44 EXPORT_SYMBOL(pci_io_base);
46 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
51 prop = of_get_property(np, name, &len);
57 static unsigned int pci_parse_of_flags(u32 addr0, int bridge)
59 unsigned int flags = 0;
61 if (addr0 & 0x02000000) {
62 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
63 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
64 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
65 if (addr0 & 0x40000000)
66 flags |= IORESOURCE_PREFETCH
67 | PCI_BASE_ADDRESS_MEM_PREFETCH;
68 /* Note: We don't know whether the ROM has been left enabled
69 * by the firmware or not. We mark it as disabled (ie, we do
70 * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
71 * do a config space read, it will be force-enabled if needed
73 if (!bridge && (addr0 & 0xff) == 0x30)
74 flags |= IORESOURCE_READONLY;
75 } else if (addr0 & 0x01000000)
76 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
78 flags |= IORESOURCE_SIZEALIGN;
83 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
92 addrs = of_get_property(node, "assigned-addresses", &proplen);
95 pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
96 for (; proplen >= 20; proplen -= 20, addrs += 5) {
97 flags = pci_parse_of_flags(addrs[0], 0);
100 base = of_read_number(&addrs[1], 2);
101 size = of_read_number(&addrs[3], 2);
105 pr_debug(" base: %llx, size: %llx, i: %x\n",
106 (unsigned long long)base,
107 (unsigned long long)size, i);
109 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
110 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
111 } else if (i == dev->rom_base_reg) {
112 res = &dev->resource[PCI_ROM_RESOURCE];
113 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
115 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
119 res->end = base + size - 1;
121 res->name = pci_name(dev);
125 struct pci_dev *of_create_pci_dev(struct device_node *node,
126 struct pci_bus *bus, int devfn)
131 dev = alloc_pci_dev();
134 type = of_get_property(node, "device_type", NULL);
138 pr_debug(" create device, devfn: %x, type: %s\n", devfn, type);
142 dev->dev.parent = bus->bridge;
143 dev->dev.bus = &pci_bus_type;
145 dev->multifunction = 0; /* maybe a lie? */
146 dev->needs_freset = 0; /* pcie fundamental reset required */
148 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
149 dev->device = get_int_prop(node, "device-id", 0xffff);
150 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
151 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
153 dev->cfg_size = pci_cfg_space_size(dev);
155 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
156 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
157 dev->class = get_int_prop(node, "class-code", 0);
158 dev->revision = get_int_prop(node, "revision-id", 0);
160 pr_debug(" class: 0x%x\n", dev->class);
161 pr_debug(" revision: 0x%x\n", dev->revision);
163 dev->current_state = 4; /* unknown power state */
164 dev->error_state = pci_channel_io_normal;
165 dev->dma_mask = 0xffffffff;
167 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
168 /* a PCI-PCI bridge */
169 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
170 dev->rom_base_reg = PCI_ROM_ADDRESS1;
171 } else if (!strcmp(type, "cardbus")) {
172 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
174 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
175 dev->rom_base_reg = PCI_ROM_ADDRESS;
176 /* Maybe do a default OF mapping here */
180 pci_parse_of_addrs(node, dev);
182 pr_debug(" adding to system ...\n");
184 pci_device_add(dev, bus);
188 EXPORT_SYMBOL(of_create_pci_dev);
190 static void __devinit __of_scan_bus(struct device_node *node,
191 struct pci_bus *bus, int rescan_existing)
193 struct device_node *child;
198 pr_debug("of_scan_bus(%s) bus no %d... \n",
199 node->full_name, bus->number);
201 /* Scan direct children */
202 for_each_child_of_node(node, child) {
203 pr_debug(" * %s\n", child->full_name);
204 reg = of_get_property(child, "reg", ®len);
205 if (reg == NULL || reglen < 20)
207 devfn = (reg[0] >> 8) & 0xff;
209 /* create a new pci_dev for this device */
210 dev = of_create_pci_dev(child, bus, devfn);
213 pr_debug(" dev header type: %x\n", dev->hdr_type);
216 /* Apply all fixups necessary. We don't fixup the bus "self"
217 * for an existing bridge that is being rescanned
219 if (!rescan_existing)
220 pcibios_setup_bus_self(bus);
221 pcibios_setup_bus_devices(bus);
223 /* Now scan child busses */
224 list_for_each_entry(dev, &bus->devices, bus_list) {
225 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
226 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
227 struct device_node *child = pci_device_to_OF_node(dev);
229 of_scan_pci_bridge(child, dev);
234 void __devinit of_scan_bus(struct device_node *node,
237 __of_scan_bus(node, bus, 0);
239 EXPORT_SYMBOL_GPL(of_scan_bus);
241 void __devinit of_rescan_bus(struct device_node *node,
244 __of_scan_bus(node, bus, 1);
246 EXPORT_SYMBOL_GPL(of_rescan_bus);
248 void __devinit of_scan_pci_bridge(struct device_node *node,
252 const u32 *busrange, *ranges;
254 struct resource *res;
258 pr_debug("of_scan_pci_bridge(%s)\n", node->full_name);
260 /* parse bus-range property */
261 busrange = of_get_property(node, "bus-range", &len);
262 if (busrange == NULL || len != 8) {
263 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
267 ranges = of_get_property(node, "ranges", &len);
268 if (ranges == NULL) {
269 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
274 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
276 printk(KERN_ERR "Failed to create pci bus for %s\n",
281 bus->primary = dev->bus->number;
282 bus->subordinate = busrange[1];
286 /* parse ranges property */
287 /* PCI #address-cells == 3 and #size-cells == 2 always */
288 res = &dev->resource[PCI_BRIDGE_RESOURCES];
289 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
291 bus->resource[i] = res;
295 for (; len >= 32; len -= 32, ranges += 8) {
296 flags = pci_parse_of_flags(ranges[0], 1);
297 size = of_read_number(&ranges[6], 2);
298 if (flags == 0 || size == 0)
300 if (flags & IORESOURCE_IO) {
301 res = bus->resource[0];
303 printk(KERN_ERR "PCI: ignoring extra I/O range"
304 " for bridge %s\n", node->full_name);
308 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
309 printk(KERN_ERR "PCI: too many memory ranges"
310 " for bridge %s\n", node->full_name);
313 res = bus->resource[i];
316 res->start = of_read_number(&ranges[1], 2);
317 res->end = res->start + size - 1;
320 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
322 pr_debug(" bus name: %s\n", bus->name);
324 mode = PCI_PROBE_NORMAL;
325 if (ppc_md.pci_probe_mode)
326 mode = ppc_md.pci_probe_mode(bus);
327 pr_debug(" probe mode: %d\n", mode);
329 if (mode == PCI_PROBE_DEVTREE)
330 of_scan_bus(node, bus);
331 else if (mode == PCI_PROBE_NORMAL)
332 pci_scan_child_bus(bus);
334 EXPORT_SYMBOL(of_scan_pci_bridge);
336 void __devinit scan_phb(struct pci_controller *hose)
339 struct device_node *node = hose->dn;
342 pr_debug("PCI: Scanning PHB %s\n",
343 node ? node->full_name : "<NO NAME>");
345 /* Create an empty bus for the toplevel */
346 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
348 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
349 hose->global_number);
352 bus->secondary = hose->first_busno;
355 /* Get some IO space for the new PHB */
356 pcibios_map_io_space(bus);
358 /* Wire up PHB bus resources */
359 pcibios_setup_phb_resources(hose);
361 /* Get probe mode and perform scan */
362 mode = PCI_PROBE_NORMAL;
363 if (node && ppc_md.pci_probe_mode)
364 mode = ppc_md.pci_probe_mode(bus);
365 pr_debug(" probe mode: %d\n", mode);
366 if (mode == PCI_PROBE_DEVTREE) {
367 bus->subordinate = hose->last_busno;
368 of_scan_bus(node, bus);
371 if (mode == PCI_PROBE_NORMAL)
372 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
375 static int __init pcibios_init(void)
377 struct pci_controller *hose, *tmp;
379 printk(KERN_INFO "PCI: Probing PCI hardware\n");
381 /* For now, override phys_mem_access_prot. If we need it,g
382 * later, we may move that initialization to each ppc_md
384 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
387 ppc_pci_flags |= PPC_PCI_PROBE_ONLY;
389 /* On ppc64, we always enable PCI domains and we keep domain 0
390 * backward compatible in /proc for video cards
392 ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
394 /* Scan all of the recorded PCI controllers. */
395 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
397 pci_bus_add_devices(hose->bus);
400 /* Call common code to handle resource allocation */
401 pcibios_resource_survey();
403 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
408 subsys_initcall(pcibios_init);
410 #ifdef CONFIG_HOTPLUG
412 int pcibios_unmap_io_space(struct pci_bus *bus)
414 struct pci_controller *hose;
416 WARN_ON(bus == NULL);
418 /* If this is not a PHB, we only flush the hash table over
419 * the area mapped by this bridge. We don't play with the PTE
420 * mappings since we might have to deal with sub-page alignemnts
421 * so flushing the hash table is the only sane way to make sure
422 * that no hash entries are covering that removed bridge area
423 * while still allowing other busses overlapping those pages
425 * Note: If we ever support P2P hotplug on Book3E, we'll have
426 * to do an appropriate TLB flush here too
429 struct resource *res = bus->resource[0];
431 pr_debug("IO unmapping for PCI-PCI bridge %s\n",
432 pci_name(bus->self));
434 #ifdef CONFIG_PPC_STD_MMU_64
435 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
436 res->end + _IO_BASE + 1);
441 /* Get the host bridge */
442 hose = pci_bus_to_host(bus);
444 /* Check if we have IOs allocated */
445 if (hose->io_base_alloc == 0)
448 pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
449 pr_debug(" alloc=0x%p\n", hose->io_base_alloc);
451 /* This is a PHB, we fully unmap the IO area */
452 vunmap(hose->io_base_alloc);
456 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
458 #endif /* CONFIG_HOTPLUG */
460 int __devinit pcibios_map_io_space(struct pci_bus *bus)
462 struct vm_struct *area;
463 unsigned long phys_page;
464 unsigned long size_page;
465 unsigned long io_virt_offset;
466 struct pci_controller *hose;
468 WARN_ON(bus == NULL);
470 /* If this not a PHB, nothing to do, page tables still exist and
471 * thus HPTEs will be faulted in when needed
474 pr_debug("IO mapping for PCI-PCI bridge %s\n",
475 pci_name(bus->self));
476 pr_debug(" virt=0x%016llx...0x%016llx\n",
477 bus->resource[0]->start + _IO_BASE,
478 bus->resource[0]->end + _IO_BASE);
482 /* Get the host bridge */
483 hose = pci_bus_to_host(bus);
484 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
485 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
487 /* Make sure IO area address is clear */
488 hose->io_base_alloc = NULL;
490 /* If there's no IO to map on that bus, get away too */
491 if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
494 /* Let's allocate some IO space for that guy. We don't pass
495 * VM_IOREMAP because we don't care about alignment tricks that
496 * the core does in that case. Maybe we should due to stupid card
497 * with incomplete address decoding but I'd rather not deal with
498 * those outside of the reserved 64K legacy region.
500 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
503 hose->io_base_alloc = area->addr;
504 hose->io_base_virt = (void __iomem *)(area->addr +
505 hose->io_base_phys - phys_page);
507 pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
508 pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
509 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
510 pr_debug(" size=0x%016llx (alloc=0x%016lx)\n",
511 hose->pci_io_size, size_page);
513 /* Establish the mapping */
514 if (__ioremap_at(phys_page, area->addr, size_page,
515 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
518 /* Fixup hose IO resource */
519 io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
520 hose->io_resource.start += io_virt_offset;
521 hose->io_resource.end += io_virt_offset;
523 pr_debug(" hose->io_resource=0x%016llx...0x%016llx\n",
524 hose->io_resource.start, hose->io_resource.end);
528 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
530 #define IOBASE_BRIDGE_NUMBER 0
531 #define IOBASE_MEMORY 1
533 #define IOBASE_ISA_IO 3
534 #define IOBASE_ISA_MEM 4
536 long sys_pciconfig_iobase(long which, unsigned long in_bus,
537 unsigned long in_devfn)
539 struct pci_controller* hose;
540 struct list_head *ln;
541 struct pci_bus *bus = NULL;
542 struct device_node *hose_node;
544 /* Argh ! Please forgive me for that hack, but that's the
545 * simplest way to get existing XFree to not lockup on some
546 * G5 machines... So when something asks for bus 0 io base
547 * (bus 0 is HT root), we return the AGP one instead.
549 if (in_bus == 0 && machine_is_compatible("MacRISC4")) {
550 struct device_node *agp;
552 agp = of_find_compatible_node(NULL, NULL, "u3-agp");
558 /* That syscall isn't quite compatible with PCI domains, but it's
559 * used on pre-domains setup. We return the first match
562 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
564 if (in_bus >= bus->number && in_bus <= bus->subordinate)
568 if (bus == NULL || bus->sysdata == NULL)
571 hose_node = (struct device_node *)bus->sysdata;
572 hose = PCI_DN(hose_node)->phb;
575 case IOBASE_BRIDGE_NUMBER:
576 return (long)hose->first_busno;
578 return (long)hose->pci_mem_offset;
580 return (long)hose->io_base_phys;
582 return (long)isa_io_base;
591 int pcibus_to_node(struct pci_bus *bus)
593 struct pci_controller *phb = pci_bus_to_host(bus);
596 EXPORT_SYMBOL(pcibus_to_node);