arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41
  42 #include <asm/pgtable.h>
  43 #include <asm/io.h>
  44 #include <asm/processor.h>
  45 #include <asm/mmu.h>
  46 #include <asm/prom.h>
  47 #include <asm/machdep.h>
  48 #include <asm/time.h>
  49 #include <asm/runlatch.h>
  50 #include <asm/syscalls.h>
  51 #include <asm/switch_to.h>
  52 #include <asm/tm.h>
  53 #include <asm/debug.h>
  54 #ifdef CONFIG_PPC64
  55 #include <asm/firmware.h>
  56 #endif
  57 #include <asm/code-patching.h>
  58 #include <linux/kprobes.h>
  59 #include <linux/kdebug.h>
  60
  61 /* Transactional Memory debug */
  62 #ifdef TM_DEBUG_SW
  63 #define TM_DEBUG(x...) printk(KERN_INFO x)
  64 #else
  65 #define TM_DEBUG(x...) do { } while(0)
  66 #endif
  67
  68 extern unsigned long _get_SP(void);
  69
  70 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  71 void giveup_fpu_maybe_transactional(struct task_struct *tsk)
  72 {
  73         /*
  74          * If we are saving the current thread's registers, and the
  75          * thread is in a transactional state, set the TIF_RESTORE_TM
  76          * bit so that we know to restore the registers before
  77          * returning to userspace.
  78          */
  79         if (tsk == current && tsk->thread.regs &&
  80             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  81             !test_thread_flag(TIF_RESTORE_TM)) {
  82                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  83                 set_thread_flag(TIF_RESTORE_TM);
  84         }
  85
  86         giveup_fpu(tsk);
  87 }
  88
  89 void giveup_altivec_maybe_transactional(struct task_struct *tsk)
  90 {
  91         /*
  92          * If we are saving the current thread's registers, and the
  93          * thread is in a transactional state, set the TIF_RESTORE_TM
  94          * bit so that we know to restore the registers before
  95          * returning to userspace.
  96          */
  97         if (tsk == current && tsk->thread.regs &&
  98             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  99             !test_thread_flag(TIF_RESTORE_TM)) {
 100                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
 101                 set_thread_flag(TIF_RESTORE_TM);
 102         }
 103
 104         giveup_altivec(tsk);
 105 }
 106
 107 #else
 108 #define giveup_fpu_maybe_transactional(tsk)     giveup_fpu(tsk)
 109 #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk)
 110 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 111
 112 #ifdef CONFIG_PPC_FPU
 113 /*
 114  * Make sure the floating-point register state in the
 115  * the thread_struct is up to date for task tsk.
 116  */
 117 void flush_fp_to_thread(struct task_struct *tsk)
 118 {
 119         if (tsk->thread.regs) {
 120                 /*
 121                  * We need to disable preemption here because if we didn't,
 122                  * another process could get scheduled after the regs->msr
 123                  * test but before we have finished saving the FP registers
 124                  * to the thread_struct.  That process could take over the
 125                  * FPU, and then when we get scheduled again we would store
 126                  * bogus values for the remaining FP registers.
 127                  */
 128                 preempt_disable();
 129                 if (tsk->thread.regs->msr & MSR_FP) {
 130                         /*
 131                          * This should only ever be called for current or
 132                          * for a stopped child process.  Since we save away
 133                          * the FP register state on context switch,
 134                          * there is something wrong if a stopped child appears
 135                          * to still have its FP state in the CPU registers.
 136                          */
 137                         BUG_ON(tsk != current);
 138                         giveup_fpu_maybe_transactional(tsk);
 139                 }
 140                 preempt_enable();
 141         }
 142 }
 143 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 144 #endif /* CONFIG_PPC_FPU */
 145
 146 void enable_kernel_fp(void)
 147 {
 148         WARN_ON(preemptible());
 149
 150         if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
 151                 giveup_fpu_maybe_transactional(current);
 152         else
 153                 giveup_fpu(NULL);       /* just enables FP for kernel */
 154 }
 155 EXPORT_SYMBOL(enable_kernel_fp);
 156
 157 #ifdef CONFIG_ALTIVEC
 158 void enable_kernel_altivec(void)
 159 {
 160         WARN_ON(preemptible());
 161
 162         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
 163                 giveup_altivec_maybe_transactional(current);
 164         else
 165                 giveup_altivec_notask();
 166 }
 167 EXPORT_SYMBOL(enable_kernel_altivec);
 168
 169 /*
 170  * Make sure the VMX/Altivec register state in the
 171  * the thread_struct is up to date for task tsk.
 172  */
 173 void flush_altivec_to_thread(struct task_struct *tsk)
 174 {
 175         if (tsk->thread.regs) {
 176                 preempt_disable();
 177                 if (tsk->thread.regs->msr & MSR_VEC) {
 178                         BUG_ON(tsk != current);
 179                         giveup_altivec_maybe_transactional(tsk);
 180                 }
 181                 preempt_enable();
 182         }
 183 }
 184 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 185 #endif /* CONFIG_ALTIVEC */
 186
 187 #ifdef CONFIG_VSX
 188 void enable_kernel_vsx(void)
 189 {
 190         WARN_ON(preemptible());
 191
 192         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
 193                 giveup_vsx(current);
 194         else
 195                 giveup_vsx(NULL);       /* just enable vsx for kernel - force */
 196 }
 197 EXPORT_SYMBOL(enable_kernel_vsx);
 198
 199 void giveup_vsx(struct task_struct *tsk)
 200 {
 201         giveup_fpu_maybe_transactional(tsk);
 202         giveup_altivec_maybe_transactional(tsk);
 203         __giveup_vsx(tsk);
 204 }
 205 EXPORT_SYMBOL(giveup_vsx);
 206
 207 void flush_vsx_to_thread(struct task_struct *tsk)
 208 {
 209         if (tsk->thread.regs) {
 210                 preempt_disable();
 211                 if (tsk->thread.regs->msr & MSR_VSX) {
 212                         BUG_ON(tsk != current);
 213                         giveup_vsx(tsk);
 214                 }
 215                 preempt_enable();
 216         }
 217 }
 218 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 219 #endif /* CONFIG_VSX */
 220
 221 #ifdef CONFIG_SPE
 222
 223 void enable_kernel_spe(void)
 224 {
 225         WARN_ON(preemptible());
 226
 227         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
 228                 giveup_spe(current);
 229         else
 230                 giveup_spe(NULL);       /* just enable SPE for kernel - force */
 231 }
 232 EXPORT_SYMBOL(enable_kernel_spe);
 233
 234 void flush_spe_to_thread(struct task_struct *tsk)
 235 {
 236         if (tsk->thread.regs) {
 237                 preempt_disable();
 238                 if (tsk->thread.regs->msr & MSR_SPE) {
 239                         BUG_ON(tsk != current);
 240                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 241                         giveup_spe(tsk);
 242                 }
 243                 preempt_enable();
 244         }
 245 }
 246 #endif /* CONFIG_SPE */
 247
 248 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 249 void do_send_trap(struct pt_regs *regs, unsigned long address,
 250                   unsigned long error_code, int signal_code, int breakpt)
 251 {
 252         siginfo_t info;
 253
 254         current->thread.trap_nr = signal_code;
 255         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 256                         11, SIGSEGV) == NOTIFY_STOP)
 257                 return;
 258
 259         /* Deliver the signal to userspace */
 260         info.si_signo = SIGTRAP;
 261         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 262         info.si_code = signal_code;
 263         info.si_addr = (void __user *)address;
 264         force_sig_info(SIGTRAP, &info, current);
 265 }
 266 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 267 void do_break (struct pt_regs *regs, unsigned long address,
 268                     unsigned long error_code)
 269 {
 270         siginfo_t info;
 271
 272         current->thread.trap_nr = TRAP_HWBKPT;
 273         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 274                         11, SIGSEGV) == NOTIFY_STOP)
 275                 return;
 276
 277         if (debugger_break_match(regs))
 278                 return;
 279
 280         /* Clear the breakpoint */
 281         hw_breakpoint_disable();
 282
 283         /* Deliver the signal to userspace */
 284         info.si_signo = SIGTRAP;
 285         info.si_errno = 0;
 286         info.si_code = TRAP_HWBKPT;
 287         info.si_addr = (void __user *)address;
 288         force_sig_info(SIGTRAP, &info, current);
 289 }
 290 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 291
 292 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 293
 294 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 295 /*
 296  * Set the debug registers back to their default "safe" values.
 297  */
 298 static void set_debug_reg_defaults(struct thread_struct *thread)
 299 {
 300         thread->debug.iac1 = thread->debug.iac2 = 0;
 301 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 302         thread->debug.iac3 = thread->debug.iac4 = 0;
 303 #endif
 304         thread->debug.dac1 = thread->debug.dac2 = 0;
 305 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 306         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 307 #endif
 308         thread->debug.dbcr0 = 0;
 309 #ifdef CONFIG_BOOKE
 310         /*
 311          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 312          */
 313         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 314                         DBCR1_IAC3US | DBCR1_IAC4US;
 315         /*
 316          * Force Data Address Compare User/Supervisor bits to be User-only
 317          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 318          */
 319         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 320 #else
 321         thread->debug.dbcr1 = 0;
 322 #endif
 323 }
 324
 325 static void prime_debug_regs(struct debug_reg *debug)
 326 {
 327         /*
 328          * We could have inherited MSR_DE from userspace, since
 329          * it doesn't get cleared on exception entry.  Make sure
 330          * MSR_DE is clear before we enable any debug events.
 331          */
 332         mtmsr(mfmsr() & ~MSR_DE);
 333
 334         mtspr(SPRN_IAC1, debug->iac1);
 335         mtspr(SPRN_IAC2, debug->iac2);
 336 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 337         mtspr(SPRN_IAC3, debug->iac3);
 338         mtspr(SPRN_IAC4, debug->iac4);
 339 #endif
 340         mtspr(SPRN_DAC1, debug->dac1);
 341         mtspr(SPRN_DAC2, debug->dac2);
 342 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 343         mtspr(SPRN_DVC1, debug->dvc1);
 344         mtspr(SPRN_DVC2, debug->dvc2);
 345 #endif
 346         mtspr(SPRN_DBCR0, debug->dbcr0);
 347         mtspr(SPRN_DBCR1, debug->dbcr1);
 348 #ifdef CONFIG_BOOKE
 349         mtspr(SPRN_DBCR2, debug->dbcr2);
 350 #endif
 351 }
 352 /*
 353  * Unless neither the old or new thread are making use of the
 354  * debug registers, set the debug registers from the values
 355  * stored in the new thread.
 356  */
 357 void switch_booke_debug_regs(struct debug_reg *new_debug)
 358 {
 359         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 360                 || (new_debug->dbcr0 & DBCR0_IDM))
 361                         prime_debug_regs(new_debug);
 362 }
 363 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 364 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 365 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 366 static void set_debug_reg_defaults(struct thread_struct *thread)
 367 {
 368         thread->hw_brk.address = 0;
 369         thread->hw_brk.type = 0;
 370         set_breakpoint(&thread->hw_brk);
 371 }
 372 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 373 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 374
 375 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 376 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 377 {
 378         mtspr(SPRN_DAC1, dabr);
 379 #ifdef CONFIG_PPC_47x
 380         isync();
 381 #endif
 382         return 0;
 383 }
 384 #elif defined(CONFIG_PPC_BOOK3S)
 385 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 386 {
 387         mtspr(SPRN_DABR, dabr);
 388         if (cpu_has_feature(CPU_FTR_DABRX))
 389                 mtspr(SPRN_DABRX, dabrx);
 390         return 0;
 391 }
 392 #else
 393 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 394 {
 395         return -EINVAL;
 396 }
 397 #endif
 398
 399 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 400 {
 401         unsigned long dabr, dabrx;
 402
 403         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 404         dabrx = ((brk->type >> 3) & 0x7);
 405
 406         if (ppc_md.set_dabr)
 407                 return ppc_md.set_dabr(dabr, dabrx);
 408
 409         return __set_dabr(dabr, dabrx);
 410 }
 411
 412 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 413 {
 414         unsigned long dawr, dawrx, mrd;
 415
 416         dawr = brk->address;
 417
 418         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 419                                    << (63 - 58); //* read/write bits */
 420         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 421                                    << (63 - 59); //* translate */
 422         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 423                                    >> 3; //* PRIM bits */
 424         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 425            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 426            0b111111=64DW.
 427            brk->len is in bytes.
 428            This aligns up to double word size, shifts and does the bias.
 429         */
 430         mrd = ((brk->len + 7) >> 3) - 1;
 431         dawrx |= (mrd & 0x3f) << (63 - 53);
 432
 433         if (ppc_md.set_dawr)
 434                 return ppc_md.set_dawr(dawr, dawrx);
 435         mtspr(SPRN_DAWR, dawr);
 436         mtspr(SPRN_DAWRX, dawrx);
 437         return 0;
 438 }
 439
 440 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 441 {
 442         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 443
 444         if (cpu_has_feature(CPU_FTR_DAWR))
 445                 set_dawr(brk);
 446         else
 447                 set_dabr(brk);
 448 }
 449
 450 void set_breakpoint(struct arch_hw_breakpoint *brk)
 451 {
 452         preempt_disable();
 453         __set_breakpoint(brk);
 454         preempt_enable();
 455 }
 456
 457 #ifdef CONFIG_PPC64
 458 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 459 #endif
 460
 461 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 462                               struct arch_hw_breakpoint *b)
 463 {
 464         if (a->address != b->address)
 465                 return false;
 466         if (a->type != b->type)
 467                 return false;
 468         if (a->len != b->len)
 469                 return false;
 470         return true;
 471 }
 472
 473 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 474 static void tm_reclaim_thread(struct thread_struct *thr,
 475                               struct thread_info *ti, uint8_t cause)
 476 {
 477         unsigned long msr_diff = 0;
 478
 479         /*
 480          * If FP/VSX registers have been already saved to the
 481          * thread_struct, move them to the transact_fp array.
 482          * We clear the TIF_RESTORE_TM bit since after the reclaim
 483          * the thread will no longer be transactional.
 484          */
 485         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 486                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
 487                 if (msr_diff & MSR_FP)
 488                         memcpy(&thr->transact_fp, &thr->fp_state,
 489                                sizeof(struct thread_fp_state));
 490                 if (msr_diff & MSR_VEC)
 491                         memcpy(&thr->transact_vr, &thr->vr_state,
 492                                sizeof(struct thread_vr_state));
 493                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 494                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 495         }
 496
 497         tm_reclaim(thr, thr->regs->msr, cause);
 498
 499         /* Having done the reclaim, we now have the checkpointed
 500          * FP/VSX values in the registers.  These might be valid
 501          * even if we have previously called enable_kernel_fp() or
 502          * flush_fp_to_thread(), so update thr->regs->msr to
 503          * indicate their current validity.
 504          */
 505         thr->regs->msr |= msr_diff;
 506 }
 507
 508 void tm_reclaim_current(uint8_t cause)
 509 {
 510         tm_enable();
 511         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 512 }
 513
 514 static inline void tm_reclaim_task(struct task_struct *tsk)
 515 {
 516         /* We have to work out if we're switching from/to a task that's in the
 517          * middle of a transaction.
 518          *
 519          * In switching we need to maintain a 2nd register state as
 520          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 521          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 522          * (current) FPRs into oldtask->thread.transact_fpr[].
 523          *
 524          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 525          */
 526         struct thread_struct *thr = &tsk->thread;
 527
 528         if (!thr->regs)
 529                 return;
 530
 531         if (!MSR_TM_ACTIVE(thr->regs->msr))
 532                 goto out_and_saveregs;
 533
 534         /* Stash the original thread MSR, as giveup_fpu et al will
 535          * modify it.  We hold onto it to see whether the task used
 536          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 537          * ckpt_regs.msr is already set.
 538          */
 539         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 540                 thr->ckpt_regs.msr = thr->regs->msr;
 541
 542         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 543                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 544                  tsk->pid, thr->regs->nip,
 545                  thr->regs->ccr, thr->regs->msr,
 546                  thr->regs->trap);
 547
 548         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 549
 550         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 551                  tsk->pid);
 552
 553 out_and_saveregs:
 554         /* Always save the regs here, even if a transaction's not active.
 555          * This context-switches a thread's TM info SPRs.  We do it here to
 556          * be consistent with the restore path (in recheckpoint) which
 557          * cannot happen later in _switch().
 558          */
 559         tm_save_sprs(thr);
 560 }
 561
 562 extern void __tm_recheckpoint(struct thread_struct *thread,
 563                               unsigned long orig_msr);
 564
 565 void tm_recheckpoint(struct thread_struct *thread,
 566                      unsigned long orig_msr)
 567 {
 568         unsigned long flags;
 569
 570         /* We really can't be interrupted here as the TEXASR registers can't
 571          * change and later in the trecheckpoint code, we have a userspace R1.
 572          * So let's hard disable over this region.
 573          */
 574         local_irq_save(flags);
 575         hard_irq_disable();
 576
 577         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 578          * before the trecheckpoint and no explosion occurs.
 579          */
 580         tm_restore_sprs(thread);
 581
 582         __tm_recheckpoint(thread, orig_msr);
 583
 584         local_irq_restore(flags);
 585 }
 586
 587 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 588 {
 589         unsigned long msr;
 590
 591         if (!cpu_has_feature(CPU_FTR_TM))
 592                 return;
 593
 594         /* Recheckpoint the registers of the thread we're about to switch to.
 595          *
 596          * If the task was using FP, we non-lazily reload both the original and
 597          * the speculative FP register states.  This is because the kernel
 598          * doesn't see if/when a TM rollback occurs, so if we take an FP
 599          * unavoidable later, we are unable to determine which set of FP regs
 600          * need to be restored.
 601          */
 602         if (!new->thread.regs)
 603                 return;
 604
 605         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 606                 tm_restore_sprs(&new->thread);
 607                 return;
 608         }
 609         msr = new->thread.ckpt_regs.msr;
 610         /* Recheckpoint to restore original checkpointed register state. */
 611         TM_DEBUG("*** tm_recheckpoint of pid %d "
 612                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 613                  new->pid, new->thread.regs->msr, msr);
 614
 615         /* This loads the checkpointed FP/VEC state, if used */
 616         tm_recheckpoint(&new->thread, msr);
 617
 618         /* This loads the speculative FP/VEC state, if used */
 619         if (msr & MSR_FP) {
 620                 do_load_up_transact_fpu(&new->thread);
 621                 new->thread.regs->msr |=
 622                         (MSR_FP | new->thread.fpexc_mode);
 623         }
 624 #ifdef CONFIG_ALTIVEC
 625         if (msr & MSR_VEC) {
 626                 do_load_up_transact_altivec(&new->thread);
 627                 new->thread.regs->msr |= MSR_VEC;
 628         }
 629 #endif
 630         /* We may as well turn on VSX too since all the state is restored now */
 631         if (msr & MSR_VSX)
 632                 new->thread.regs->msr |= MSR_VSX;
 633
 634         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 635                  "(kernel msr 0x%lx)\n",
 636                  new->pid, mfmsr());
 637 }
 638
 639 static inline void __switch_to_tm(struct task_struct *prev)
 640 {
 641         if (cpu_has_feature(CPU_FTR_TM)) {
 642                 tm_enable();
 643                 tm_reclaim_task(prev);
 644         }
 645 }
 646
 647 /*
 648  * This is called if we are on the way out to userspace and the
 649  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 650  * FP and/or vector state and does so if necessary.
 651  * If userspace is inside a transaction (whether active or
 652  * suspended) and FP/VMX/VSX instructions have ever been enabled
 653  * inside that transaction, then we have to keep them enabled
 654  * and keep the FP/VMX/VSX state loaded while ever the transaction
 655  * continues.  The reason is that if we didn't, and subsequently
 656  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 657  * we don't know whether it's the same transaction, and thus we
 658  * don't know which of the checkpointed state and the transactional
 659  * state to use.
 660  */
 661 void restore_tm_state(struct pt_regs *regs)
 662 {
 663         unsigned long msr_diff;
 664
 665         clear_thread_flag(TIF_RESTORE_TM);
 666         if (!MSR_TM_ACTIVE(regs->msr))
 667                 return;
 668
 669         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 670         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 671         if (msr_diff & MSR_FP) {
 672                 fp_enable();
 673                 load_fp_state(&current->thread.fp_state);
 674                 regs->msr |= current->thread.fpexc_mode;
 675         }
 676         if (msr_diff & MSR_VEC) {
 677                 vec_enable();
 678                 load_vr_state(&current->thread.vr_state);
 679         }
 680         regs->msr |= msr_diff;
 681 }
 682
 683 #else
 684 #define tm_recheckpoint_new_task(new)
 685 #define __switch_to_tm(prev)
 686 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 687
 688 static inline void save_sprs(struct thread_struct *t)
 689 {
 690 #ifdef CONFIG_ALTIVEC
 691         if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
 692                 t->vrsave = mfspr(SPRN_VRSAVE);
 693 #endif
 694 #ifdef CONFIG_PPC_BOOK3S_64
 695         if (cpu_has_feature(CPU_FTR_DSCR))
 696                 t->dscr = mfspr(SPRN_DSCR);
 697
 698         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
 699                 t->bescr = mfspr(SPRN_BESCR);
 700                 t->ebbhr = mfspr(SPRN_EBBHR);
 701                 t->ebbrr = mfspr(SPRN_EBBRR);
 702
 703                 t->fscr = mfspr(SPRN_FSCR);
 704
 705                 /*
 706                  * Note that the TAR is not available for use in the kernel.
 707                  * (To provide this, the TAR should be backed up/restored on
 708                  * exception entry/exit instead, and be in pt_regs.  FIXME,
 709                  * this should be in pt_regs anyway (for debug).)
 710                  */
 711                 t->tar = mfspr(SPRN_TAR);
 712         }
 713 #endif
 714 }
 715
 716 static inline void restore_sprs(struct thread_struct *old_thread,
 717                                 struct thread_struct *new_thread)
 718 {
 719 #ifdef CONFIG_ALTIVEC
 720         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 721             old_thread->vrsave != new_thread->vrsave)
 722                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
 723 #endif
 724 #ifdef CONFIG_PPC_BOOK3S_64
 725         if (cpu_has_feature(CPU_FTR_DSCR)) {
 726                 u64 dscr = get_paca()->dscr_default;
 727                 u64 fscr = old_thread->fscr & ~FSCR_DSCR;
 728
 729                 if (new_thread->dscr_inherit) {
 730                         dscr = new_thread->dscr;
 731                         fscr |= FSCR_DSCR;
 732                 }
 733
 734                 if (old_thread->dscr != dscr)
 735                         mtspr(SPRN_DSCR, dscr);
 736
 737                 if (old_thread->fscr != fscr)
 738                         mtspr(SPRN_FSCR, fscr);
 739         }
 740
 741         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
 742                 if (old_thread->bescr != new_thread->bescr)
 743                         mtspr(SPRN_BESCR, new_thread->bescr);
 744                 if (old_thread->ebbhr != new_thread->ebbhr)
 745                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
 746                 if (old_thread->ebbrr != new_thread->ebbrr)
 747                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
 748
 749                 if (old_thread->tar != new_thread->tar)
 750                         mtspr(SPRN_TAR, new_thread->tar);
 751         }
 752 #endif
 753 }
 754
 755 struct task_struct *__switch_to(struct task_struct *prev,
 756         struct task_struct *new)
 757 {
 758         struct thread_struct *new_thread, *old_thread;
 759         struct task_struct *last;
 760 #ifdef CONFIG_PPC_BOOK3S_64
 761         struct ppc64_tlb_batch *batch;
 762 #endif
 763
 764         new_thread = &new->thread;
 765         old_thread = &current->thread;
 766
 767         WARN_ON(!irqs_disabled());
 768
 769         /*
 770          * We need to save SPRs before treclaim/trecheckpoint as these will
 771          * change a number of them.
 772          */
 773         save_sprs(&prev->thread);
 774
 775         __switch_to_tm(prev);
 776
 777         if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
 778                 giveup_fpu(prev);
 779 #ifdef CONFIG_ALTIVEC
 780         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
 781                 giveup_altivec(prev);
 782 #endif /* CONFIG_ALTIVEC */
 783 #ifdef CONFIG_VSX
 784         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
 785                 /* VMX and FPU registers are already save here */
 786                 __giveup_vsx(prev);
 787 #endif /* CONFIG_VSX */
 788 #ifdef CONFIG_SPE
 789         if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
 790                 giveup_spe(prev);
 791 #endif /* CONFIG_SPE */
 792
 793 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 794         switch_booke_debug_regs(&new->thread.debug);
 795 #else
 796 /*
 797  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
 798  * schedule DABR
 799  */
 800 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 801         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
 802                 __set_breakpoint(&new->thread.hw_brk);
 803 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 804 #endif
 805
 806 #ifdef CONFIG_PPC64
 807         /*
 808          * Collect processor utilization data per process
 809          */
 810         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
 811                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
 812                 long unsigned start_tb, current_tb;
 813                 start_tb = old_thread->start_tb;
 814                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
 815                 old_thread->accum_tb += (current_tb - start_tb);
 816                 new_thread->start_tb = current_tb;
 817         }
 818 #endif /* CONFIG_PPC64 */
 819
 820 #ifdef CONFIG_PPC_BOOK3S_64
 821         batch = this_cpu_ptr(&ppc64_tlb_batch);
 822         if (batch->active) {
 823                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
 824                 if (batch->index)
 825                         __flush_tlb_pending(batch);
 826                 batch->active = 0;
 827         }
 828 #endif /* CONFIG_PPC_BOOK3S_64 */
 829
 830         /*
 831          * We can't take a PMU exception inside _switch() since there is a
 832          * window where the kernel stack SLB and the kernel stack are out
 833          * of sync. Hard disable here.
 834          */
 835         hard_irq_disable();
 836
 837         tm_recheckpoint_new_task(new);
 838
 839         last = _switch(old_thread, new_thread);
 840
 841         /* Need to recalculate these after calling _switch() */
 842         old_thread = &last->thread;
 843         new_thread = &current->thread;
 844
 845 #ifdef CONFIG_PPC_BOOK3S_64
 846         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
 847                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
 848                 batch = this_cpu_ptr(&ppc64_tlb_batch);
 849                 batch->active = 1;
 850         }
 851 #endif /* CONFIG_PPC_BOOK3S_64 */
 852
 853         restore_sprs(old_thread, new_thread);
 854
 855         return last;
 856 }
 857
 858 static int instructions_to_print = 16;
 859
 860 static void show_instructions(struct pt_regs *regs)
 861 {
 862         int i;
 863         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
 864                         sizeof(int));
 865
 866         printk("Instruction dump:");
 867
 868         for (i = 0; i < instructions_to_print; i++) {
 869                 int instr;
 870
 871                 if (!(i % 8))
 872                         printk("\n");
 873
 874 #if !defined(CONFIG_BOOKE)
 875                 /* If executing with the IMMU off, adjust pc rather
 876                  * than print XXXXXXXX.
 877                  */
 878                 if (!(regs->msr & MSR_IR))
 879                         pc = (unsigned long)phys_to_virt(pc);
 880 #endif
 881
 882                 if (!__kernel_text_address(pc) ||
 883                      probe_kernel_address((unsigned int __user *)pc, instr)) {
 884                         printk(KERN_CONT "XXXXXXXX ");
 885                 } else {
 886                         if (regs->nip == pc)
 887                                 printk(KERN_CONT "<%08x> ", instr);
 888                         else
 889                                 printk(KERN_CONT "%08x ", instr);
 890                 }
 891
 892                 pc += sizeof(int);
 893         }
 894
 895         printk("\n");
 896 }
 897
 898 static struct regbit {
 899         unsigned long bit;
 900         const char *name;
 901 } msr_bits[] = {
 902 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
 903         {MSR_SF,        "SF"},
 904         {MSR_HV,        "HV"},
 905 #endif
 906         {MSR_VEC,       "VEC"},
 907         {MSR_VSX,       "VSX"},
 908 #ifdef CONFIG_BOOKE
 909         {MSR_CE,        "CE"},
 910 #endif
 911         {MSR_EE,        "EE"},
 912         {MSR_PR,        "PR"},
 913         {MSR_FP,        "FP"},
 914         {MSR_ME,        "ME"},
 915 #ifdef CONFIG_BOOKE
 916         {MSR_DE,        "DE"},
 917 #else
 918         {MSR_SE,        "SE"},
 919         {MSR_BE,        "BE"},
 920 #endif
 921         {MSR_IR,        "IR"},
 922         {MSR_DR,        "DR"},
 923         {MSR_PMM,       "PMM"},
 924 #ifndef CONFIG_BOOKE
 925         {MSR_RI,        "RI"},
 926         {MSR_LE,        "LE"},
 927 #endif
 928         {0,             NULL}
 929 };
 930
 931 static void printbits(unsigned long val, struct regbit *bits)
 932 {
 933         const char *sep = "";
 934
 935         printk("<");
 936         for (; bits->bit; ++bits)
 937                 if (val & bits->bit) {
 938                         printk("%s%s", sep, bits->name);
 939                         sep = ",";
 940                 }
 941         printk(">");
 942 }
 943
 944 #ifdef CONFIG_PPC64
 945 #define REG             "%016lx"
 946 #define REGS_PER_LINE   4
 947 #define LAST_VOLATILE   13
 948 #else
 949 #define REG             "%08lx"
 950 #define REGS_PER_LINE   8
 951 #define LAST_VOLATILE   12
 952 #endif
 953
 954 void show_regs(struct pt_regs * regs)
 955 {
 956         int i, trap;
 957
 958         show_regs_print_info(KERN_DEFAULT);
 959
 960         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
 961                regs->nip, regs->link, regs->ctr);
 962         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
 963                regs, regs->trap, print_tainted(), init_utsname()->release);
 964         printk("MSR: "REG" ", regs->msr);
 965         printbits(regs->msr, msr_bits);
 966         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
 967         trap = TRAP(regs);
 968         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
 969                 printk("CFAR: "REG" ", regs->orig_gpr3);
 970         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
 971 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
 972                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
 973 #else
 974                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
 975 #endif
 976 #ifdef CONFIG_PPC64
 977         printk("SOFTE: %ld ", regs->softe);
 978 #endif
 979 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 980         if (MSR_TM_ACTIVE(regs->msr))
 981                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
 982 #endif
 983
 984         for (i = 0;  i < 32;  i++) {
 985                 if ((i % REGS_PER_LINE) == 0)
 986                         printk("\nGPR%02d: ", i);
 987                 printk(REG " ", regs->gpr[i]);
 988                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
 989                         break;
 990         }
 991         printk("\n");
 992 #ifdef CONFIG_KALLSYMS
 993         /*
 994          * Lookup NIP late so we have the best change of getting the
 995          * above info out without failing
 996          */
 997         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
 998         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
 999 #endif
1000         show_stack(current, (unsigned long *) regs->gpr[1]);
1001         if (!user_mode(regs))
1002                 show_instructions(regs);
1003 }
1004
1005 void exit_thread(void)
1006 {
1007 }
1008
1009 void flush_thread(void)
1010 {
1011 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1012         flush_ptrace_hw_breakpoint(current);
1013 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1014         set_debug_reg_defaults(&current->thread);
1015 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1016 }
1017
1018 void
1019 release_thread(struct task_struct *t)
1020 {
1021 }
1022
1023 /*
1024  * this gets called so that we can store coprocessor state into memory and
1025  * copy the current task into the new thread.
1026  */
1027 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1028 {
1029         flush_fp_to_thread(src);
1030         flush_altivec_to_thread(src);
1031         flush_vsx_to_thread(src);
1032         flush_spe_to_thread(src);
1033         /*
1034          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1035          * flush but it removes the checkpointed state from the current CPU and
1036          * transitions the CPU out of TM mode.  Hence we need to call
1037          * tm_recheckpoint_new_task() (on the same task) to restore the
1038          * checkpointed state back and the TM mode.
1039          */
1040         __switch_to_tm(src);
1041         tm_recheckpoint_new_task(src);
1042
1043         *dst = *src;
1044
1045         clear_task_ebb(dst);
1046
1047         return 0;
1048 }
1049
1050 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1051 {
1052 #ifdef CONFIG_PPC_STD_MMU_64
1053         unsigned long sp_vsid;
1054         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1055
1056         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1057                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1058                         << SLB_VSID_SHIFT_1T;
1059         else
1060                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1061                         << SLB_VSID_SHIFT;
1062         sp_vsid |= SLB_VSID_KERNEL | llp;
1063         p->thread.ksp_vsid = sp_vsid;
1064 #endif
1065 }
1066
1067 /*
1068  * Copy a thread..
1069  */
1070
1071 /*
1072  * Copy architecture-specific thread state
1073  */
1074 int copy_thread(unsigned long clone_flags, unsigned long usp,
1075                 unsigned long kthread_arg, struct task_struct *p)
1076 {
1077         struct pt_regs *childregs, *kregs;
1078         extern void ret_from_fork(void);
1079         extern void ret_from_kernel_thread(void);
1080         void (*f)(void);
1081         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1082
1083         /* Copy registers */
1084         sp -= sizeof(struct pt_regs);
1085         childregs = (struct pt_regs *) sp;
1086         if (unlikely(p->flags & PF_KTHREAD)) {
1087                 /* kernel thread */
1088                 struct thread_info *ti = (void *)task_stack_page(p);
1089                 memset(childregs, 0, sizeof(struct pt_regs));
1090                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1091                 /* function */
1092                 if (usp)
1093                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1094 #ifdef CONFIG_PPC64
1095                 clear_tsk_thread_flag(p, TIF_32BIT);
1096                 childregs->softe = 1;
1097 #endif
1098                 childregs->gpr[15] = kthread_arg;
1099                 p->thread.regs = NULL;  /* no user register state */
1100                 ti->flags |= _TIF_RESTOREALL;
1101                 f = ret_from_kernel_thread;
1102         } else {
1103                 /* user thread */
1104                 struct pt_regs *regs = current_pt_regs();
1105                 CHECK_FULL_REGS(regs);
1106                 *childregs = *regs;
1107                 if (usp)
1108                         childregs->gpr[1] = usp;
1109                 p->thread.regs = childregs;
1110                 childregs->gpr[3] = 0;  /* Result from fork() */
1111                 if (clone_flags & CLONE_SETTLS) {
1112 #ifdef CONFIG_PPC64
1113                         if (!is_32bit_task())
1114                                 childregs->gpr[13] = childregs->gpr[6];
1115                         else
1116 #endif
1117                                 childregs->gpr[2] = childregs->gpr[6];
1118                 }
1119
1120                 f = ret_from_fork;
1121         }
1122         sp -= STACK_FRAME_OVERHEAD;
1123
1124         /*
1125          * The way this works is that at some point in the future
1126          * some task will call _switch to switch to the new task.
1127          * That will pop off the stack frame created below and start
1128          * the new task running at ret_from_fork.  The new task will
1129          * do some house keeping and then return from the fork or clone
1130          * system call, using the stack frame created above.
1131          */
1132         ((unsigned long *)sp)[0] = 0;
1133         sp -= sizeof(struct pt_regs);
1134         kregs = (struct pt_regs *) sp;
1135         sp -= STACK_FRAME_OVERHEAD;
1136         p->thread.ksp = sp;
1137 #ifdef CONFIG_PPC32
1138         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1139                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1140 #endif
1141 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1142         p->thread.ptrace_bps[0] = NULL;
1143 #endif
1144
1145         p->thread.fp_save_area = NULL;
1146 #ifdef CONFIG_ALTIVEC
1147         p->thread.vr_save_area = NULL;
1148 #endif
1149
1150         setup_ksp_vsid(p, sp);
1151
1152 #ifdef CONFIG_PPC64
1153         if (cpu_has_feature(CPU_FTR_DSCR)) {
1154                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1155                 p->thread.dscr = current->thread.dscr;
1156         }
1157         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1158                 p->thread.ppr = INIT_PPR;
1159 #endif
1160         kregs->nip = ppc_function_entry(f);
1161         return 0;
1162 }
1163
1164 /*
1165  * Set up a thread for executing a new program
1166  */
1167 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1168 {
1169 #ifdef CONFIG_PPC64
1170         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1171 #endif
1172
1173         /*
1174          * If we exec out of a kernel thread then thread.regs will not be
1175          * set.  Do it now.
1176          */
1177         if (!current->thread.regs) {
1178                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1179                 current->thread.regs = regs - 1;
1180         }
1181
1182         memset(regs->gpr, 0, sizeof(regs->gpr));
1183         regs->ctr = 0;
1184         regs->link = 0;
1185         regs->xer = 0;
1186         regs->ccr = 0;
1187         regs->gpr[1] = sp;
1188
1189         /*
1190          * We have just cleared all the nonvolatile GPRs, so make
1191          * FULL_REGS(regs) return true.  This is necessary to allow
1192          * ptrace to examine the thread immediately after exec.
1193          */
1194         regs->trap &= ~1UL;
1195
1196 #ifdef CONFIG_PPC32
1197         regs->mq = 0;
1198         regs->nip = start;
1199         regs->msr = MSR_USER;
1200 #else
1201         if (!is_32bit_task()) {
1202                 unsigned long entry;
1203
1204                 if (is_elf2_task()) {
1205                         /* Look ma, no function descriptors! */
1206                         entry = start;
1207
1208                         /*
1209                          * Ulrich says:
1210                          *   The latest iteration of the ABI requires that when
1211                          *   calling a function (at its global entry point),
1212                          *   the caller must ensure r12 holds the entry point
1213                          *   address (so that the function can quickly
1214                          *   establish addressability).
1215                          */
1216                         regs->gpr[12] = start;
1217                         /* Make sure that's restored on entry to userspace. */
1218                         set_thread_flag(TIF_RESTOREALL);
1219                 } else {
1220                         unsigned long toc;
1221
1222                         /* start is a relocated pointer to the function
1223                          * descriptor for the elf _start routine.  The first
1224                          * entry in the function descriptor is the entry
1225                          * address of _start and the second entry is the TOC
1226                          * value we need to use.
1227                          */
1228                         __get_user(entry, (unsigned long __user *)start);
1229                         __get_user(toc, (unsigned long __user *)start+1);
1230
1231                         /* Check whether the e_entry function descriptor entries
1232                          * need to be relocated before we can use them.
1233                          */
1234                         if (load_addr != 0) {
1235                                 entry += load_addr;
1236                                 toc   += load_addr;
1237                         }
1238                         regs->gpr[2] = toc;
1239                 }
1240                 regs->nip = entry;
1241                 regs->msr = MSR_USER64;
1242         } else {
1243                 regs->nip = start;
1244                 regs->gpr[2] = 0;
1245                 regs->msr = MSR_USER32;
1246         }
1247 #endif
1248 #ifdef CONFIG_VSX
1249         current->thread.used_vsr = 0;
1250 #endif
1251         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1252         current->thread.fp_save_area = NULL;
1253 #ifdef CONFIG_ALTIVEC
1254         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1255         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1256         current->thread.vr_save_area = NULL;
1257         current->thread.vrsave = 0;
1258         current->thread.used_vr = 0;
1259 #endif /* CONFIG_ALTIVEC */
1260 #ifdef CONFIG_SPE
1261         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1262         current->thread.acc = 0;
1263         current->thread.spefscr = 0;
1264         current->thread.used_spe = 0;
1265 #endif /* CONFIG_SPE */
1266 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1267         if (cpu_has_feature(CPU_FTR_TM))
1268                 regs->msr |= MSR_TM;
1269         current->thread.tm_tfhar = 0;
1270         current->thread.tm_texasr = 0;
1271         current->thread.tm_tfiar = 0;
1272 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1273 }
1274 EXPORT_SYMBOL(start_thread);
1275
1276 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1277                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1278
1279 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1280 {
1281         struct pt_regs *regs = tsk->thread.regs;
1282
1283         /* This is a bit hairy.  If we are an SPE enabled  processor
1284          * (have embedded fp) we store the IEEE exception enable flags in
1285          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1286          * mode (asyn, precise, disabled) for 'Classic' FP. */
1287         if (val & PR_FP_EXC_SW_ENABLE) {
1288 #ifdef CONFIG_SPE
1289                 if (cpu_has_feature(CPU_FTR_SPE)) {
1290                         /*
1291                          * When the sticky exception bits are set
1292                          * directly by userspace, it must call prctl
1293                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1294                          * in the existing prctl settings) or
1295                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1296                          * the bits being set).  <fenv.h> functions
1297                          * saving and restoring the whole
1298                          * floating-point environment need to do so
1299                          * anyway to restore the prctl settings from
1300                          * the saved environment.
1301                          */
1302                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1303                         tsk->thread.fpexc_mode = val &
1304                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1305                         return 0;
1306                 } else {
1307                         return -EINVAL;
1308                 }
1309 #else
1310                 return -EINVAL;
1311 #endif
1312         }
1313
1314         /* on a CONFIG_SPE this does not hurt us.  The bits that
1315          * __pack_fe01 use do not overlap with bits used for
1316          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1317          * on CONFIG_SPE implementations are reserved so writing to
1318          * them does not change anything */
1319         if (val > PR_FP_EXC_PRECISE)
1320                 return -EINVAL;
1321         tsk->thread.fpexc_mode = __pack_fe01(val);
1322         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1323                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1324                         | tsk->thread.fpexc_mode;
1325         return 0;
1326 }
1327
1328 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1329 {
1330         unsigned int val;
1331
1332         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1333 #ifdef CONFIG_SPE
1334                 if (cpu_has_feature(CPU_FTR_SPE)) {
1335                         /*
1336                          * When the sticky exception bits are set
1337                          * directly by userspace, it must call prctl
1338                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1339                          * in the existing prctl settings) or
1340                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1341                          * the bits being set).  <fenv.h> functions
1342                          * saving and restoring the whole
1343                          * floating-point environment need to do so
1344                          * anyway to restore the prctl settings from
1345                          * the saved environment.
1346                          */
1347                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1348                         val = tsk->thread.fpexc_mode;
1349                 } else
1350                         return -EINVAL;
1351 #else
1352                 return -EINVAL;
1353 #endif
1354         else
1355                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1356         return put_user(val, (unsigned int __user *) adr);
1357 }
1358
1359 int set_endian(struct task_struct *tsk, unsigned int val)
1360 {
1361         struct pt_regs *regs = tsk->thread.regs;
1362
1363         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1364             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1365                 return -EINVAL;
1366
1367         if (regs == NULL)
1368                 return -EINVAL;
1369
1370         if (val == PR_ENDIAN_BIG)
1371                 regs->msr &= ~MSR_LE;
1372         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1373                 regs->msr |= MSR_LE;
1374         else
1375                 return -EINVAL;
1376
1377         return 0;
1378 }
1379
1380 int get_endian(struct task_struct *tsk, unsigned long adr)
1381 {
1382         struct pt_regs *regs = tsk->thread.regs;
1383         unsigned int val;
1384
1385         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1386             !cpu_has_feature(CPU_FTR_REAL_LE))
1387                 return -EINVAL;
1388
1389         if (regs == NULL)
1390                 return -EINVAL;
1391
1392         if (regs->msr & MSR_LE) {
1393                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1394                         val = PR_ENDIAN_LITTLE;
1395                 else
1396                         val = PR_ENDIAN_PPC_LITTLE;
1397         } else
1398                 val = PR_ENDIAN_BIG;
1399
1400         return put_user(val, (unsigned int __user *)adr);
1401 }
1402
1403 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1404 {
1405         tsk->thread.align_ctl = val;
1406         return 0;
1407 }
1408
1409 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1410 {
1411         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1412 }
1413
1414 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1415                                   unsigned long nbytes)
1416 {
1417         unsigned long stack_page;
1418         unsigned long cpu = task_cpu(p);
1419
1420         /*
1421          * Avoid crashing if the stack has overflowed and corrupted
1422          * task_cpu(p), which is in the thread_info struct.
1423          */
1424         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1425                 stack_page = (unsigned long) hardirq_ctx[cpu];
1426                 if (sp >= stack_page + sizeof(struct thread_struct)
1427                     && sp <= stack_page + THREAD_SIZE - nbytes)
1428                         return 1;
1429
1430                 stack_page = (unsigned long) softirq_ctx[cpu];
1431                 if (sp >= stack_page + sizeof(struct thread_struct)
1432                     && sp <= stack_page + THREAD_SIZE - nbytes)
1433                         return 1;
1434         }
1435         return 0;
1436 }
1437
1438 int validate_sp(unsigned long sp, struct task_struct *p,
1439                        unsigned long nbytes)
1440 {
1441         unsigned long stack_page = (unsigned long)task_stack_page(p);
1442
1443         if (sp >= stack_page + sizeof(struct thread_struct)
1444             && sp <= stack_page + THREAD_SIZE - nbytes)
1445                 return 1;
1446
1447         return valid_irq_stack(sp, p, nbytes);
1448 }
1449
1450 EXPORT_SYMBOL(validate_sp);
1451
1452 unsigned long get_wchan(struct task_struct *p)
1453 {
1454         unsigned long ip, sp;
1455         int count = 0;
1456
1457         if (!p || p == current || p->state == TASK_RUNNING)
1458                 return 0;
1459
1460         sp = p->thread.ksp;
1461         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1462                 return 0;
1463
1464         do {
1465                 sp = *(unsigned long *)sp;
1466                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1467                         return 0;
1468                 if (count > 0) {
1469                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1470                         if (!in_sched_functions(ip))
1471                                 return ip;
1472                 }
1473         } while (count++ < 16);
1474         return 0;
1475 }
1476
1477 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1478
1479 void show_stack(struct task_struct *tsk, unsigned long *stack)
1480 {
1481         unsigned long sp, ip, lr, newsp;
1482         int count = 0;
1483         int firstframe = 1;
1484 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1485         int curr_frame = current->curr_ret_stack;
1486         extern void return_to_handler(void);
1487         unsigned long rth = (unsigned long)return_to_handler;
1488 #endif
1489
1490         sp = (unsigned long) stack;
1491         if (tsk == NULL)
1492                 tsk = current;
1493         if (sp == 0) {
1494                 if (tsk == current)
1495                         sp = current_stack_pointer();
1496                 else
1497                         sp = tsk->thread.ksp;
1498         }
1499
1500         lr = 0;
1501         printk("Call Trace:\n");
1502         do {
1503                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1504                         return;
1505
1506                 stack = (unsigned long *) sp;
1507                 newsp = stack[0];
1508                 ip = stack[STACK_FRAME_LR_SAVE];
1509                 if (!firstframe || ip != lr) {
1510                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1511 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1512                         if ((ip == rth) && curr_frame >= 0) {
1513                                 printk(" (%pS)",
1514                                        (void *)current->ret_stack[curr_frame].ret);
1515                                 curr_frame--;
1516                         }
1517 #endif
1518                         if (firstframe)
1519                                 printk(" (unreliable)");
1520                         printk("\n");
1521                 }
1522                 firstframe = 0;
1523
1524                 /*
1525                  * See if this is an exception frame.
1526                  * We look for the "regshere" marker in the current frame.
1527                  */
1528                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1529                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1530                         struct pt_regs *regs = (struct pt_regs *)
1531                                 (sp + STACK_FRAME_OVERHEAD);
1532                         lr = regs->link;
1533                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1534                                regs->trap, (void *)regs->nip, (void *)lr);
1535                         firstframe = 1;
1536                 }
1537
1538                 sp = newsp;
1539         } while (count++ < kstack_depth_to_print);
1540 }
1541
1542 #ifdef CONFIG_PPC64
1543 /* Called with hard IRQs off */
1544 void notrace __ppc64_runlatch_on(void)
1545 {
1546         struct thread_info *ti = current_thread_info();
1547         unsigned long ctrl;
1548
1549         ctrl = mfspr(SPRN_CTRLF);
1550         ctrl |= CTRL_RUNLATCH;
1551         mtspr(SPRN_CTRLT, ctrl);
1552
1553         ti->local_flags |= _TLF_RUNLATCH;
1554 }
1555
1556 /* Called with hard IRQs off */
1557 void notrace __ppc64_runlatch_off(void)
1558 {
1559         struct thread_info *ti = current_thread_info();
1560         unsigned long ctrl;
1561
1562         ti->local_flags &= ~_TLF_RUNLATCH;
1563
1564         ctrl = mfspr(SPRN_CTRLF);
1565         ctrl &= ~CTRL_RUNLATCH;
1566         mtspr(SPRN_CTRLT, ctrl);
1567 }
1568 #endif /* CONFIG_PPC64 */
1569
1570 unsigned long arch_align_stack(unsigned long sp)
1571 {
1572         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1573                 sp -= get_random_int() & ~PAGE_MASK;
1574         return sp & ~0xf;
1575 }
1576
1577 static inline unsigned long brk_rnd(void)
1578 {
1579         unsigned long rnd = 0;
1580
1581         /* 8MB for 32bit, 1GB for 64bit */
1582         if (is_32bit_task())
1583                 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1584         else
1585                 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1586
1587         return rnd << PAGE_SHIFT;
1588 }
1589
1590 unsigned long arch_randomize_brk(struct mm_struct *mm)
1591 {
1592         unsigned long base = mm->brk;
1593         unsigned long ret;
1594
1595 #ifdef CONFIG_PPC_STD_MMU_64
1596         /*
1597          * If we are using 1TB segments and we are allowed to randomise
1598          * the heap, we can put it above 1TB so it is backed by a 1TB
1599          * segment. Otherwise the heap will be in the bottom 1TB
1600          * which always uses 256MB segments and this may result in a
1601          * performance penalty.
1602          */
1603         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1604                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1605 #endif
1606
1607         ret = PAGE_ALIGN(base + brk_rnd());
1608
1609         if (ret < mm->brk)
1610                 return mm->brk;
1611
1612         return ret;
1613 }
1614