2 * TLB flush routines for radix kernels.
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
13 #include <linux/hugetlb.h>
14 #include <linux/memblock.h>
15 #include <asm/ppc-opcode.h>
18 #include <asm/tlbflush.h>
20 static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
22 #define RIC_FLUSH_TLB 0
23 #define RIC_FLUSH_PWC 1
24 #define RIC_FLUSH_ALL 2
26 static inline void __tlbiel_pid(unsigned long pid, int set,
29 unsigned long rb,rs,prs,r;
31 rb = PPC_BIT(53); /* IS = 1 */
32 rb |= set << PPC_BITLSHIFT(51);
33 rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
34 prs = 1; /* process scoped */
35 r = 1; /* raidx format */
37 asm volatile("ptesync": : :"memory");
38 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
39 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
40 asm volatile("ptesync": : :"memory");
44 * We use 128 set in radix mode and 256 set in hpt mode.
46 static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
50 for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
51 __tlbiel_pid(pid, set, ric);
56 static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
58 unsigned long rb,rs,prs,r;
60 rb = PPC_BIT(53); /* IS = 1 */
61 rs = pid << PPC_BITLSHIFT(31);
62 prs = 1; /* process scoped */
63 r = 1; /* raidx format */
65 asm volatile("ptesync": : :"memory");
66 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
67 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
68 asm volatile("eieio; tlbsync; ptesync": : :"memory");
71 static inline void _tlbiel_va(unsigned long va, unsigned long pid,
72 unsigned long ap, unsigned long ric)
74 unsigned long rb,rs,prs,r;
76 rb = va & ~(PPC_BITMASK(52, 63));
77 rb |= ap << PPC_BITLSHIFT(58);
78 rs = pid << PPC_BITLSHIFT(31);
79 prs = 1; /* process scoped */
80 r = 1; /* raidx format */
82 asm volatile("ptesync": : :"memory");
83 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
84 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
85 asm volatile("ptesync": : :"memory");
88 static inline void _tlbie_va(unsigned long va, unsigned long pid,
89 unsigned long ap, unsigned long ric)
91 unsigned long rb,rs,prs,r;
93 rb = va & ~(PPC_BITMASK(52, 63));
94 rb |= ap << PPC_BITLSHIFT(58);
95 rs = pid << PPC_BITLSHIFT(31);
96 prs = 1; /* process scoped */
97 r = 1; /* raidx format */
99 asm volatile("ptesync": : :"memory");
100 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
101 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
102 asm volatile("eieio; tlbsync; ptesync": : :"memory");
106 * Base TLB flushing operations:
108 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
109 * - flush_tlb_page(vma, vmaddr) flushes one page
110 * - flush_tlb_range(vma, start, end) flushes a range of pages
111 * - flush_tlb_kernel_range(start, end) flushes kernel pages
113 * - local_* variants of page and mm only apply to the current
116 void radix__local_flush_tlb_mm(struct mm_struct *mm)
121 pid = mm->context.id;
122 if (pid != MMU_NO_CONTEXT)
123 _tlbiel_pid(pid, RIC_FLUSH_ALL);
126 EXPORT_SYMBOL(radix__local_flush_tlb_mm);
128 void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
131 struct mm_struct *mm = tlb->mm;
135 pid = mm->context.id;
136 if (pid != MMU_NO_CONTEXT)
137 _tlbiel_pid(pid, RIC_FLUSH_PWC);
141 EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
143 void radix___local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
144 unsigned long ap, int nid)
149 pid = mm ? mm->context.id : 0;
150 if (pid != MMU_NO_CONTEXT)
151 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
155 void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
157 #ifdef CONFIG_HUGETLB_PAGE
158 /* need the return fix for nohash.c */
159 if (vma && is_vm_hugetlb_page(vma))
160 return __local_flush_hugetlb_page(vma, vmaddr);
162 radix___local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
163 mmu_get_ap(mmu_virtual_psize), 0);
165 EXPORT_SYMBOL(radix__local_flush_tlb_page);
168 static int mm_is_core_local(struct mm_struct *mm)
170 return cpumask_subset(mm_cpumask(mm),
171 topology_sibling_cpumask(smp_processor_id()));
174 void radix__flush_tlb_mm(struct mm_struct *mm)
179 pid = mm->context.id;
180 if (unlikely(pid == MMU_NO_CONTEXT))
183 if (!mm_is_core_local(mm)) {
184 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
187 raw_spin_lock(&native_tlbie_lock);
188 _tlbie_pid(pid, RIC_FLUSH_ALL);
190 raw_spin_unlock(&native_tlbie_lock);
192 _tlbiel_pid(pid, RIC_FLUSH_ALL);
196 EXPORT_SYMBOL(radix__flush_tlb_mm);
198 void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
201 struct mm_struct *mm = tlb->mm;
205 pid = mm->context.id;
206 if (unlikely(pid == MMU_NO_CONTEXT))
209 if (!mm_is_core_local(mm)) {
210 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
213 raw_spin_lock(&native_tlbie_lock);
214 _tlbie_pid(pid, RIC_FLUSH_PWC);
216 raw_spin_unlock(&native_tlbie_lock);
218 _tlbiel_pid(pid, RIC_FLUSH_PWC);
222 EXPORT_SYMBOL(radix__flush_tlb_pwc);
224 void radix___flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
225 unsigned long ap, int nid)
230 pid = mm ? mm->context.id : 0;
231 if (unlikely(pid == MMU_NO_CONTEXT))
233 if (!mm_is_core_local(mm)) {
234 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
237 raw_spin_lock(&native_tlbie_lock);
238 _tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
240 raw_spin_unlock(&native_tlbie_lock);
242 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
247 void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
249 #ifdef CONFIG_HUGETLB_PAGE
250 if (vma && is_vm_hugetlb_page(vma))
251 return flush_hugetlb_page(vma, vmaddr);
253 radix___flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
254 mmu_get_ap(mmu_virtual_psize), 0);
256 EXPORT_SYMBOL(radix__flush_tlb_page);
258 #endif /* CONFIG_SMP */
260 void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
262 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
265 raw_spin_lock(&native_tlbie_lock);
266 _tlbie_pid(0, RIC_FLUSH_ALL);
268 raw_spin_unlock(&native_tlbie_lock);
270 EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
273 * Currently, for range flushing, we just do a full mm flush. Because
274 * we use this in code path where we don' track the page size.
276 void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
280 struct mm_struct *mm = vma->vm_mm;
281 radix__flush_tlb_mm(mm);
283 EXPORT_SYMBOL(radix__flush_tlb_range);
285 static int radix_get_mmu_psize(int page_size)
289 if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
290 psize = mmu_virtual_psize;
291 else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
293 else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
300 void radix__tlb_flush(struct mmu_gather *tlb)
302 struct mm_struct *mm = tlb->mm;
303 radix__flush_tlb_mm(mm);
306 void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
307 unsigned long page_size)
309 unsigned long rb,rs,prs,r;
311 unsigned long ric = RIC_FLUSH_TLB;
313 ap = mmu_get_ap(radix_get_mmu_psize(page_size));
314 rb = gpa & ~(PPC_BITMASK(52, 63));
315 rb |= ap << PPC_BITLSHIFT(58);
316 rs = lpid & ((1UL << 32) - 1);
317 prs = 0; /* process scoped */
318 r = 1; /* raidx format */
320 asm volatile("ptesync": : :"memory");
321 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
322 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
323 asm volatile("eieio; tlbsync; ptesync": : :"memory");
325 EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
327 void radix__flush_tlb_lpid(unsigned long lpid)
329 unsigned long rb,rs,prs,r;
330 unsigned long ric = RIC_FLUSH_ALL;
332 rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
333 rs = lpid & ((1UL << 32) - 1);
334 prs = 0; /* partition scoped */
335 r = 1; /* raidx format */
337 asm volatile("ptesync": : :"memory");
338 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
339 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
340 asm volatile("eieio; tlbsync; ptesync": : :"memory");
342 EXPORT_SYMBOL(radix__flush_tlb_lpid);