arch/powerpc/platforms/cell/spufs/switch.c

   1 /*
   2  * spu_switch.c
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  *
   6  * Author: Mark Nutter <mnutter@us.ibm.com>
   7  *
   8  * Host-side part of SPU context switch sequence outlined in
   9  * Synergistic Processor Element, Book IV.
  10  *
  11  * A fully premptive switch of an SPE is very expensive in terms
  12  * of time and system resources.  SPE Book IV indicates that SPE
  13  * allocation should follow a "serially reusable device" model,
  14  * in which the SPE is assigned a task until it completes.  When
  15  * this is not possible, this sequence may be used to premptively
  16  * save, and then later (optionally) restore the context of a
  17  * program executing on an SPE.
  18  *
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2, or (at your option)
  23  * any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/errno.h>
  37 #include <linux/hardirq.h>
  38 #include <linux/sched.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/smp.h>
  43 #include <linux/stddef.h>
  44 #include <linux/unistd.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/spu.h>
  48 #include <asm/spu_priv1.h>
  49 #include <asm/spu_csa.h>
  50 #include <asm/mmu_context.h>
  51
  52 #include "spufs.h"
  53
  54 #include "spu_save_dump.h"
  55 #include "spu_restore_dump.h"
  56
  57 #if 0
  58 #define POLL_WHILE_TRUE(_c) {                           \
  59     do {                                                \
  60     } while (_c);                                       \
  61   }
  62 #else
  63 #define RELAX_SPIN_COUNT                                1000
  64 #define POLL_WHILE_TRUE(_c) {                           \
  65     do {                                                \
  66         int _i;                                         \
  67         for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
  68             cpu_relax();                                \
  69         }                                               \
  70         if (unlikely(_c)) yield();                      \
  71         else break;                                     \
  72     } while (_c);                                       \
  73   }
  74 #endif                          /* debug */
  75
  76 #define POLL_WHILE_FALSE(_c)    POLL_WHILE_TRUE(!(_c))
  77
  78 static inline void acquire_spu_lock(struct spu *spu)
  79 {
  80         /* Save, Step 1:
  81          * Restore, Step 1:
  82          *    Acquire SPU-specific mutual exclusion lock.
  83          *    TBD.
  84          */
  85 }
  86
  87 static inline void release_spu_lock(struct spu *spu)
  88 {
  89         /* Restore, Step 76:
  90          *    Release SPU-specific mutual exclusion lock.
  91          *    TBD.
  92          */
  93 }
  94
  95 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
  96 {
  97         struct spu_problem __iomem *prob = spu->problem;
  98         u32 isolate_state;
  99
 100         /* Save, Step 2:
 101          * Save, Step 6:
 102          *     If SPU_Status[E,L,IS] any field is '1', this
 103          *     SPU is in isolate state and cannot be context
 104          *     saved at this time.
 105          */
 106         isolate_state = SPU_STATUS_ISOLATED_STATE |
 107             SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
 108         return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
 109 }
 110
 111 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
 112 {
 113         /* Save, Step 3:
 114          * Restore, Step 2:
 115          *     Save INT_Mask_class0 in CSA.
 116          *     Write INT_MASK_class0 with value of 0.
 117          *     Save INT_Mask_class1 in CSA.
 118          *     Write INT_MASK_class1 with value of 0.
 119          *     Save INT_Mask_class2 in CSA.
 120          *     Write INT_MASK_class2 with value of 0.
 121          *     Synchronize all three interrupts to be sure
 122          *     we no longer execute a handler on another CPU.
 123          */
 124         spin_lock_irq(&spu->register_lock);
 125         if (csa) {
 126                 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
 127                 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
 128                 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
 129         }
 130         spu_int_mask_set(spu, 0, 0ul);
 131         spu_int_mask_set(spu, 1, 0ul);
 132         spu_int_mask_set(spu, 2, 0ul);
 133         eieio();
 134         spin_unlock_irq(&spu->register_lock);
 135         synchronize_irq(spu->irqs[0]);
 136         synchronize_irq(spu->irqs[1]);
 137         synchronize_irq(spu->irqs[2]);
 138 }
 139
 140 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
 141 {
 142         /* Save, Step 4:
 143          * Restore, Step 25.
 144          *    Set a software watchdog timer, which specifies the
 145          *    maximum allowable time for a context save sequence.
 146          *
 147          *    For present, this implementation will not set a global
 148          *    watchdog timer, as virtualization & variable system load
 149          *    may cause unpredictable execution times.
 150          */
 151 }
 152
 153 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
 154 {
 155         /* Save, Step 5:
 156          * Restore, Step 3:
 157          *     Inhibit user-space access (if provided) to this
 158          *     SPU by unmapping the virtual pages assigned to
 159          *     the SPU memory-mapped I/O (MMIO) for problem
 160          *     state. TBD.
 161          */
 162 }
 163
 164 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
 165 {
 166         /* Save, Step 7:
 167          * Restore, Step 5:
 168          *     Set a software context switch pending flag.
 169          */
 170         set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 171         mb();
 172 }
 173
 174 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
 175 {
 176         struct spu_priv2 __iomem *priv2 = spu->priv2;
 177
 178         /* Save, Step 8:
 179          *     Suspend DMA and save MFC_CNTL.
 180          */
 181         switch (in_be64(&priv2->mfc_control_RW) &
 182                MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
 183         case MFC_CNTL_SUSPEND_IN_PROGRESS:
 184                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 185                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 186                                  MFC_CNTL_SUSPEND_COMPLETE);
 187                 /* fall through */
 188         case MFC_CNTL_SUSPEND_COMPLETE:
 189                 if (csa)
 190                         csa->priv2.mfc_control_RW =
 191                                 in_be64(&priv2->mfc_control_RW) |
 192                                 MFC_CNTL_SUSPEND_DMA_QUEUE;
 193                 break;
 194         case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
 195                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
 196                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 197                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 198                                  MFC_CNTL_SUSPEND_COMPLETE);
 199                 if (csa)
 200                         csa->priv2.mfc_control_RW =
 201                                 in_be64(&priv2->mfc_control_RW) &
 202                                 ~MFC_CNTL_SUSPEND_DMA_QUEUE &
 203                                 ~MFC_CNTL_SUSPEND_MASK;
 204                 break;
 205         }
 206 }
 207
 208 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
 209 {
 210         struct spu_problem __iomem *prob = spu->problem;
 211
 212         /* Save, Step 9:
 213          *     Save SPU_Runcntl in the CSA.  This value contains
 214          *     the "Application Desired State".
 215          */
 216         csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
 217 }
 218
 219 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
 220 {
 221         /* Save, Step 10:
 222          *     Save MFC_SR1 in the CSA.
 223          */
 224         csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
 225 }
 226
 227 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
 228 {
 229         struct spu_problem __iomem *prob = spu->problem;
 230
 231         /* Save, Step 11:
 232          *     Read SPU_Status[R], and save to CSA.
 233          */
 234         if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
 235                 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 236         } else {
 237                 u32 stopped;
 238
 239                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
 240                 eieio();
 241                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
 242                                 SPU_STATUS_RUNNING);
 243                 stopped =
 244                     SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
 245                     SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
 246                 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
 247                         csa->prob.spu_status_R = SPU_STATUS_RUNNING;
 248                 else
 249                         csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 250         }
 251 }
 252
 253 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
 254 {
 255         struct spu_priv2 __iomem *priv2 = spu->priv2;
 256
 257         /* Save, Step 12:
 258          *     Read MFC_CNTL[Ds].  Update saved copy of
 259          *     CSA.MFC_CNTL[Ds].
 260          */
 261         csa->priv2.mfc_control_RW |=
 262                 in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING;
 263 }
 264
 265 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
 266 {
 267         struct spu_priv2 __iomem *priv2 = spu->priv2;
 268
 269         /* Save, Step 13:
 270          *     Write MFC_CNTL[Dh] set to a '1' to halt
 271          *     the decrementer.
 272          */
 273         out_be64(&priv2->mfc_control_RW,
 274                  MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK);
 275         eieio();
 276 }
 277
 278 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
 279 {
 280         /* Save, Step 14:
 281          *    Read PPE Timebase High and Timebase low registers
 282          *    and save in CSA.  TBD.
 283          */
 284         csa->suspend_time = get_cycles();
 285 }
 286
 287 static inline void remove_other_spu_access(struct spu_state *csa,
 288                                            struct spu *spu)
 289 {
 290         /* Save, Step 15:
 291          *     Remove other SPU access to this SPU by unmapping
 292          *     this SPU's pages from their address space.  TBD.
 293          */
 294 }
 295
 296 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
 297 {
 298         struct spu_problem __iomem *prob = spu->problem;
 299
 300         /* Save, Step 16:
 301          * Restore, Step 11.
 302          *     Write SPU_MSSync register. Poll SPU_MSSync[P]
 303          *     for a value of 0.
 304          */
 305         out_be64(&prob->spc_mssync_RW, 1UL);
 306         POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
 307 }
 308
 309 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
 310 {
 311         /* Save, Step 17:
 312          * Restore, Step 12.
 313          * Restore, Step 48.
 314          *     Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
 315          *     Then issue a PPE sync instruction.
 316          */
 317         spu_tlb_invalidate(spu);
 318         mb();
 319 }
 320
 321 static inline void handle_pending_interrupts(struct spu_state *csa,
 322                                              struct spu *spu)
 323 {
 324         /* Save, Step 18:
 325          *     Handle any pending interrupts from this SPU
 326          *     here.  This is OS or hypervisor specific.  One
 327          *     option is to re-enable interrupts to handle any
 328          *     pending interrupts, with the interrupt handlers
 329          *     recognizing the software Context Switch Pending
 330          *     flag, to ensure the SPU execution or MFC command
 331          *     queue is not restarted.  TBD.
 332          */
 333 }
 334
 335 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
 336 {
 337         struct spu_priv2 __iomem *priv2 = spu->priv2;
 338         int i;
 339
 340         /* Save, Step 19:
 341          *     If MFC_Cntl[Se]=0 then save
 342          *     MFC command queues.
 343          */
 344         if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
 345                 for (i = 0; i < 8; i++) {
 346                         csa->priv2.puq[i].mfc_cq_data0_RW =
 347                             in_be64(&priv2->puq[i].mfc_cq_data0_RW);
 348                         csa->priv2.puq[i].mfc_cq_data1_RW =
 349                             in_be64(&priv2->puq[i].mfc_cq_data1_RW);
 350                         csa->priv2.puq[i].mfc_cq_data2_RW =
 351                             in_be64(&priv2->puq[i].mfc_cq_data2_RW);
 352                         csa->priv2.puq[i].mfc_cq_data3_RW =
 353                             in_be64(&priv2->puq[i].mfc_cq_data3_RW);
 354                 }
 355                 for (i = 0; i < 16; i++) {
 356                         csa->priv2.spuq[i].mfc_cq_data0_RW =
 357                             in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
 358                         csa->priv2.spuq[i].mfc_cq_data1_RW =
 359                             in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
 360                         csa->priv2.spuq[i].mfc_cq_data2_RW =
 361                             in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
 362                         csa->priv2.spuq[i].mfc_cq_data3_RW =
 363                             in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
 364                 }
 365         }
 366 }
 367
 368 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
 369 {
 370         struct spu_problem __iomem *prob = spu->problem;
 371
 372         /* Save, Step 20:
 373          *     Save the PPU_QueryMask register
 374          *     in the CSA.
 375          */
 376         csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
 377 }
 378
 379 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
 380 {
 381         struct spu_problem __iomem *prob = spu->problem;
 382
 383         /* Save, Step 21:
 384          *     Save the PPU_QueryType register
 385          *     in the CSA.
 386          */
 387         csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
 388 }
 389
 390 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
 391 {
 392         struct spu_problem __iomem *prob = spu->problem;
 393
 394         /* Save the Prxy_TagStatus register in the CSA.
 395          *
 396          * It is unnecessary to restore dma_tagstatus_R, however,
 397          * dma_tagstatus_R in the CSA is accessed via backing_ops, so
 398          * we must save it.
 399          */
 400         csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
 401 }
 402
 403 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
 404 {
 405         struct spu_priv2 __iomem *priv2 = spu->priv2;
 406
 407         /* Save, Step 22:
 408          *     Save the MFC_CSR_TSQ register
 409          *     in the LSCSA.
 410          */
 411         csa->priv2.spu_tag_status_query_RW =
 412             in_be64(&priv2->spu_tag_status_query_RW);
 413 }
 414
 415 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
 416 {
 417         struct spu_priv2 __iomem *priv2 = spu->priv2;
 418
 419         /* Save, Step 23:
 420          *     Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
 421          *     registers in the CSA.
 422          */
 423         csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
 424         csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
 425 }
 426
 427 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
 428 {
 429         struct spu_priv2 __iomem *priv2 = spu->priv2;
 430
 431         /* Save, Step 24:
 432          *     Save the MFC_CSR_ATO register in
 433          *     the CSA.
 434          */
 435         csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
 436 }
 437
 438 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 439 {
 440         /* Save, Step 25:
 441          *     Save the MFC_TCLASS_ID register in
 442          *     the CSA.
 443          */
 444         csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
 445 }
 446
 447 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 448 {
 449         /* Save, Step 26:
 450          * Restore, Step 23.
 451          *     Write the MFC_TCLASS_ID register with
 452          *     the value 0x10000000.
 453          */
 454         spu_mfc_tclass_id_set(spu, 0x10000000);
 455         eieio();
 456 }
 457
 458 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
 459 {
 460         struct spu_priv2 __iomem *priv2 = spu->priv2;
 461
 462         /* Save, Step 27:
 463          * Restore, Step 14.
 464          *     Write MFC_CNTL[Pc]=1 (purge queue).
 465          */
 466         out_be64(&priv2->mfc_control_RW,
 467                         MFC_CNTL_PURGE_DMA_REQUEST |
 468                         MFC_CNTL_SUSPEND_MASK);
 469         eieio();
 470 }
 471
 472 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
 473 {
 474         struct spu_priv2 __iomem *priv2 = spu->priv2;
 475
 476         /* Save, Step 28:
 477          *     Poll MFC_CNTL[Ps] until value '11' is read
 478          *     (purge complete).
 479          */
 480         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 481                          MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
 482                          MFC_CNTL_PURGE_DMA_COMPLETE);
 483 }
 484
 485 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
 486 {
 487         /* Save, Step 30:
 488          * Restore, Step 18:
 489          *     Write MFC_SR1 with MFC_SR1[D=0,S=1] and
 490          *     MFC_SR1[TL,R,Pr,T] set correctly for the
 491          *     OS specific environment.
 492          *
 493          *     Implementation note: The SPU-side code
 494          *     for save/restore is privileged, so the
 495          *     MFC_SR1[Pr] bit is not set.
 496          *
 497          */
 498         spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
 499                               MFC_STATE1_RELOCATE_MASK |
 500                               MFC_STATE1_BUS_TLBIE_MASK));
 501 }
 502
 503 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
 504 {
 505         struct spu_problem __iomem *prob = spu->problem;
 506
 507         /* Save, Step 31:
 508          *     Save SPU_NPC in the CSA.
 509          */
 510         csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
 511 }
 512
 513 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
 514 {
 515         struct spu_priv2 __iomem *priv2 = spu->priv2;
 516
 517         /* Save, Step 32:
 518          *     Save SPU_PrivCntl in the CSA.
 519          */
 520         csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
 521 }
 522
 523 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
 524 {
 525         struct spu_priv2 __iomem *priv2 = spu->priv2;
 526
 527         /* Save, Step 33:
 528          * Restore, Step 16:
 529          *     Write SPU_PrivCntl[S,Le,A] fields reset to 0.
 530          */
 531         out_be64(&priv2->spu_privcntl_RW, 0UL);
 532         eieio();
 533 }
 534
 535 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
 536 {
 537         struct spu_priv2 __iomem *priv2 = spu->priv2;
 538
 539         /* Save, Step 34:
 540          *     Save SPU_LSLR in the CSA.
 541          */
 542         csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
 543 }
 544
 545 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
 546 {
 547         struct spu_priv2 __iomem *priv2 = spu->priv2;
 548
 549         /* Save, Step 35:
 550          * Restore, Step 17.
 551          *     Reset SPU_LSLR.
 552          */
 553         out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
 554         eieio();
 555 }
 556
 557 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
 558 {
 559         struct spu_priv2 __iomem *priv2 = spu->priv2;
 560
 561         /* Save, Step 36:
 562          *     Save SPU_Cfg in the CSA.
 563          */
 564         csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
 565 }
 566
 567 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
 568 {
 569         /* Save, Step 37:
 570          *     Save PM_Trace_Tag_Wait_Mask in the CSA.
 571          *     Not performed by this implementation.
 572          */
 573 }
 574
 575 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
 576 {
 577         /* Save, Step 38:
 578          *     Save RA_GROUP_ID register and the
 579          *     RA_ENABLE reigster in the CSA.
 580          */
 581         csa->priv1.resource_allocation_groupID_RW =
 582                 spu_resource_allocation_groupID_get(spu);
 583         csa->priv1.resource_allocation_enable_RW =
 584                 spu_resource_allocation_enable_get(spu);
 585 }
 586
 587 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
 588 {
 589         struct spu_problem __iomem *prob = spu->problem;
 590
 591         /* Save, Step 39:
 592          *     Save MB_Stat register in the CSA.
 593          */
 594         csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
 595 }
 596
 597 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
 598 {
 599         struct spu_problem __iomem *prob = spu->problem;
 600
 601         /* Save, Step 40:
 602          *     Save the PPU_MB register in the CSA.
 603          */
 604         csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
 605 }
 606
 607 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
 608 {
 609         struct spu_priv2 __iomem *priv2 = spu->priv2;
 610
 611         /* Save, Step 41:
 612          *     Save the PPUINT_MB register in the CSA.
 613          */
 614         csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
 615 }
 616
 617 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
 618 {
 619         struct spu_priv2 __iomem *priv2 = spu->priv2;
 620         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
 621         int i;
 622
 623         /* Save, Step 42:
 624          */
 625
 626         /* Save CH 1, without channel count */
 627         out_be64(&priv2->spu_chnlcntptr_RW, 1);
 628         csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
 629
 630         /* Save the following CH: [0,3,4,24,25,27] */
 631         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
 632                 idx = ch_indices[i];
 633                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 634                 eieio();
 635                 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
 636                 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
 637                 out_be64(&priv2->spu_chnldata_RW, 0UL);
 638                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 639                 eieio();
 640         }
 641 }
 642
 643 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
 644 {
 645         struct spu_priv2 __iomem *priv2 = spu->priv2;
 646         int i;
 647
 648         /* Save, Step 43:
 649          *     Save SPU Read Mailbox Channel.
 650          */
 651         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
 652         eieio();
 653         csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
 654         for (i = 0; i < 4; i++) {
 655                 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
 656         }
 657         out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 658         eieio();
 659 }
 660
 661 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
 662 {
 663         struct spu_priv2 __iomem *priv2 = spu->priv2;
 664
 665         /* Save, Step 44:
 666          *     Save MFC_CMD Channel.
 667          */
 668         out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
 669         eieio();
 670         csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
 671         eieio();
 672 }
 673
 674 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
 675 {
 676         struct spu_priv2 __iomem *priv2 = spu->priv2;
 677         u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
 678         u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
 679         u64 idx;
 680         int i;
 681
 682         /* Save, Step 45:
 683          *     Reset the following CH: [21, 23, 28, 30]
 684          */
 685         for (i = 0; i < 4; i++) {
 686                 idx = ch_indices[i];
 687                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 688                 eieio();
 689                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
 690                 eieio();
 691         }
 692 }
 693
 694 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
 695 {
 696         struct spu_priv2 __iomem *priv2 = spu->priv2;
 697
 698         /* Save, Step 46:
 699          * Restore, Step 25.
 700          *     Write MFC_CNTL[Sc]=0 (resume queue processing).
 701          */
 702         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
 703 }
 704
 705 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu,
 706                 unsigned int *code, int code_size)
 707 {
 708         /* Save, Step 47:
 709          * Restore, Step 30.
 710          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
 711          *     register, then initialize SLB_VSID and SLB_ESID
 712          *     to provide access to SPU context save code and
 713          *     LSCSA.
 714          *
 715          *     This implementation places both the context
 716          *     switch code and LSCSA in kernel address space.
 717          *
 718          *     Further this implementation assumes that the
 719          *     MFC_SR1[R]=1 (in other words, assume that
 720          *     translation is desired by OS environment).
 721          */
 722         spu_invalidate_slbs(spu);
 723         spu_setup_kernel_slbs(spu, csa->lscsa, code, code_size);
 724 }
 725
 726 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
 727 {
 728         /* Save, Step 48:
 729          * Restore, Step 23.
 730          *     Change the software context switch pending flag
 731          *     to context switch active.
 732          *
 733          *     This implementation does not uses a switch active flag.
 734          */
 735         clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 736         mb();
 737 }
 738
 739 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
 740 {
 741         unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
 742             CLASS1_ENABLE_STORAGE_FAULT_INTR;
 743
 744         /* Save, Step 49:
 745          * Restore, Step 22:
 746          *     Reset and then enable interrupts, as
 747          *     needed by OS.
 748          *
 749          *     This implementation enables only class1
 750          *     (translation) interrupts.
 751          */
 752         spin_lock_irq(&spu->register_lock);
 753         spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
 754         spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
 755         spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
 756         spu_int_mask_set(spu, 0, 0ul);
 757         spu_int_mask_set(spu, 1, class1_mask);
 758         spu_int_mask_set(spu, 2, 0ul);
 759         spin_unlock_irq(&spu->register_lock);
 760 }
 761
 762 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
 763                                unsigned int ls_offset, unsigned int size,
 764                                unsigned int tag, unsigned int rclass,
 765                                unsigned int cmd)
 766 {
 767         struct spu_problem __iomem *prob = spu->problem;
 768         union mfc_tag_size_class_cmd command;
 769         unsigned int transfer_size;
 770         volatile unsigned int status = 0x0;
 771
 772         while (size > 0) {
 773                 transfer_size =
 774                     (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
 775                 command.u.mfc_size = transfer_size;
 776                 command.u.mfc_tag = tag;
 777                 command.u.mfc_rclassid = rclass;
 778                 command.u.mfc_cmd = cmd;
 779                 do {
 780                         out_be32(&prob->mfc_lsa_W, ls_offset);
 781                         out_be64(&prob->mfc_ea_W, ea);
 782                         out_be64(&prob->mfc_union_W.all64, command.all64);
 783                         status =
 784                             in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
 785                         if (unlikely(status & 0x2)) {
 786                                 cpu_relax();
 787                         }
 788                 } while (status & 0x3);
 789                 size -= transfer_size;
 790                 ea += transfer_size;
 791                 ls_offset += transfer_size;
 792         }
 793         return 0;
 794 }
 795
 796 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
 797 {
 798         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
 799         unsigned int ls_offset = 0x0;
 800         unsigned int size = 16384;
 801         unsigned int tag = 0;
 802         unsigned int rclass = 0;
 803         unsigned int cmd = MFC_PUT_CMD;
 804
 805         /* Save, Step 50:
 806          *     Issue a DMA command to copy the first 16K bytes
 807          *     of local storage to the CSA.
 808          */
 809         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 810 }
 811
 812 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
 813 {
 814         struct spu_problem __iomem *prob = spu->problem;
 815
 816         /* Save, Step 51:
 817          * Restore, Step 31.
 818          *     Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
 819          *     point address of context save code in local
 820          *     storage.
 821          *
 822          *     This implementation uses SPU-side save/restore
 823          *     programs with entry points at LSA of 0.
 824          */
 825         out_be32(&prob->spu_npc_RW, 0);
 826         eieio();
 827 }
 828
 829 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
 830 {
 831         struct spu_problem __iomem *prob = spu->problem;
 832         union {
 833                 u64 ull;
 834                 u32 ui[2];
 835         } addr64;
 836
 837         /* Save, Step 52:
 838          * Restore, Step 32:
 839          *    Write SPU_Sig_Notify_1 register with upper 32-bits
 840          *    of the CSA.LSCSA effective address.
 841          */
 842         addr64.ull = (u64) csa->lscsa;
 843         out_be32(&prob->signal_notify1, addr64.ui[0]);
 844         eieio();
 845 }
 846
 847 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
 848 {
 849         struct spu_problem __iomem *prob = spu->problem;
 850         union {
 851                 u64 ull;
 852                 u32 ui[2];
 853         } addr64;
 854
 855         /* Save, Step 53:
 856          * Restore, Step 33:
 857          *    Write SPU_Sig_Notify_2 register with lower 32-bits
 858          *    of the CSA.LSCSA effective address.
 859          */
 860         addr64.ull = (u64) csa->lscsa;
 861         out_be32(&prob->signal_notify2, addr64.ui[1]);
 862         eieio();
 863 }
 864
 865 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
 866 {
 867         unsigned long addr = (unsigned long)&spu_save_code[0];
 868         unsigned int ls_offset = 0x0;
 869         unsigned int size = sizeof(spu_save_code);
 870         unsigned int tag = 0;
 871         unsigned int rclass = 0;
 872         unsigned int cmd = MFC_GETFS_CMD;
 873
 874         /* Save, Step 54:
 875          *     Issue a DMA command to copy context save code
 876          *     to local storage and start SPU.
 877          */
 878         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 879 }
 880
 881 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
 882 {
 883         struct spu_problem __iomem *prob = spu->problem;
 884
 885         /* Save, Step 55:
 886          * Restore, Step 38.
 887          *     Write PPU_QueryMask=1 (enable Tag Group 0)
 888          *     and issue eieio instruction.
 889          */
 890         out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
 891         eieio();
 892 }
 893
 894 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
 895 {
 896         struct spu_problem __iomem *prob = spu->problem;
 897         u32 mask = MFC_TAGID_TO_TAGMASK(0);
 898         unsigned long flags;
 899
 900         /* Save, Step 56:
 901          * Restore, Step 39.
 902          * Restore, Step 39.
 903          * Restore, Step 46.
 904          *     Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
 905          *     or write PPU_QueryType[TS]=01 and wait for Tag Group
 906          *     Complete Interrupt.  Write INT_Stat_Class0 or
 907          *     INT_Stat_Class2 with value of 'handled'.
 908          */
 909         POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
 910
 911         local_irq_save(flags);
 912         spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
 913         spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
 914         local_irq_restore(flags);
 915 }
 916
 917 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
 918 {
 919         struct spu_problem __iomem *prob = spu->problem;
 920         unsigned long flags;
 921
 922         /* Save, Step 57:
 923          * Restore, Step 40.
 924          *     Poll until SPU_Status[R]=0 or wait for SPU Class 0
 925          *     or SPU Class 2 interrupt.  Write INT_Stat_class0
 926          *     or INT_Stat_class2 with value of handled.
 927          */
 928         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
 929
 930         local_irq_save(flags);
 931         spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
 932         spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
 933         local_irq_restore(flags);
 934 }
 935
 936 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
 937 {
 938         struct spu_problem __iomem *prob = spu->problem;
 939         u32 complete;
 940
 941         /* Save, Step 54:
 942          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
 943          *     context save succeeded, otherwise context save
 944          *     failed.
 945          */
 946         complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
 947                     SPU_STATUS_STOPPED_BY_STOP);
 948         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
 949 }
 950
 951 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
 952 {
 953         /* Restore, Step 4:
 954          *    If required, notify the "using application" that
 955          *    the SPU task has been terminated.  TBD.
 956          */
 957 }
 958
 959 static inline void suspend_mfc_and_halt_decr(struct spu_state *csa,
 960                 struct spu *spu)
 961 {
 962         struct spu_priv2 __iomem *priv2 = spu->priv2;
 963
 964         /* Restore, Step 7:
 965          *     Write MFC_Cntl[Dh,Sc,Sm]='1','1','0' to suspend
 966          *     the queue and halt the decrementer.
 967          */
 968         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
 969                  MFC_CNTL_DECREMENTER_HALTED);
 970         eieio();
 971 }
 972
 973 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
 974                                              struct spu *spu)
 975 {
 976         struct spu_priv2 __iomem *priv2 = spu->priv2;
 977
 978         /* Restore, Step 8:
 979          * Restore, Step 47.
 980          *     Poll MFC_CNTL[Ss] until 11 is returned.
 981          */
 982         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 983                          MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 984                          MFC_CNTL_SUSPEND_COMPLETE);
 985 }
 986
 987 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
 988 {
 989         struct spu_problem __iomem *prob = spu->problem;
 990
 991         /* Restore, Step 9:
 992          *    If SPU_Status[R]=1, stop SPU execution
 993          *    and wait for stop to complete.
 994          *
 995          *    Returns       1 if SPU_Status[R]=1 on entry.
 996          *                  0 otherwise
 997          */
 998         if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
 999                 if (in_be32(&prob->spu_status_R) &
1000                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1001                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1002                                         SPU_STATUS_RUNNING);
1003                 }
1004                 if ((in_be32(&prob->spu_status_R) &
1005                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1006                     || (in_be32(&prob->spu_status_R) &
1007                         SPU_STATUS_ISOLATED_STATE)) {
1008                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1009                         eieio();
1010                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1011                                         SPU_STATUS_RUNNING);
1012                         out_be32(&prob->spu_runcntl_RW, 0x2);
1013                         eieio();
1014                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1015                                         SPU_STATUS_RUNNING);
1016                 }
1017                 if (in_be32(&prob->spu_status_R) &
1018                     SPU_STATUS_WAITING_FOR_CHANNEL) {
1019                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1020                         eieio();
1021                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1022                                         SPU_STATUS_RUNNING);
1023                 }
1024                 return 1;
1025         }
1026         return 0;
1027 }
1028
1029 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1030 {
1031         struct spu_problem __iomem *prob = spu->problem;
1032
1033         /* Restore, Step 10:
1034          *    If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1035          *    release SPU from isolate state.
1036          */
1037         if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1038                 if (in_be32(&prob->spu_status_R) &
1039                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1040                         spu_mfc_sr1_set(spu,
1041                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1042                         eieio();
1043                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1044                         eieio();
1045                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1046                                         SPU_STATUS_RUNNING);
1047                 }
1048                 if ((in_be32(&prob->spu_status_R) &
1049                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1050                     || (in_be32(&prob->spu_status_R) &
1051                         SPU_STATUS_ISOLATED_STATE)) {
1052                         spu_mfc_sr1_set(spu,
1053                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1054                         eieio();
1055                         out_be32(&prob->spu_runcntl_RW, 0x2);
1056                         eieio();
1057                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1058                                         SPU_STATUS_RUNNING);
1059                 }
1060         }
1061 }
1062
1063 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1064 {
1065         struct spu_priv2 __iomem *priv2 = spu->priv2;
1066         u64 ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1067         u64 idx;
1068         int i;
1069
1070         /* Restore, Step 20:
1071          */
1072
1073         /* Reset CH 1 */
1074         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1075         out_be64(&priv2->spu_chnldata_RW, 0UL);
1076
1077         /* Reset the following CH: [0,3,4,24,25,27] */
1078         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1079                 idx = ch_indices[i];
1080                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1081                 eieio();
1082                 out_be64(&priv2->spu_chnldata_RW, 0UL);
1083                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1084                 eieio();
1085         }
1086 }
1087
1088 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1089 {
1090         struct spu_priv2 __iomem *priv2 = spu->priv2;
1091         u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1092         u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1093         u64 idx;
1094         int i;
1095
1096         /* Restore, Step 21:
1097          *     Reset the following CH: [21, 23, 28, 29, 30]
1098          */
1099         for (i = 0; i < 5; i++) {
1100                 idx = ch_indices[i];
1101                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1102                 eieio();
1103                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1104                 eieio();
1105         }
1106 }
1107
1108 static inline void setup_spu_status_part1(struct spu_state *csa,
1109                                           struct spu *spu)
1110 {
1111         u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1112         u32 status_I = SPU_STATUS_INVALID_INSTR;
1113         u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1114         u32 status_S = SPU_STATUS_SINGLE_STEP;
1115         u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1116         u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1117         u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1118         u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1119         u32 status_code;
1120
1121         /* Restore, Step 27:
1122          *     If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1123          *     instruction sequence to the end of the SPU based restore
1124          *     code (after the "context restored" stop and signal) to
1125          *     restore the correct SPU status.
1126          *
1127          *     NOTE: Rather than modifying the SPU executable, we
1128          *     instead add a new 'stopped_status' field to the
1129          *     LSCSA.  The SPU-side restore reads this field and
1130          *     takes the appropriate action when exiting.
1131          */
1132
1133         status_code =
1134             (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1135         if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1136
1137                 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1138                  * by Stop and Signal instruction, followed by 'br -4'.
1139                  *
1140                  */
1141                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1142                 csa->lscsa->stopped_status.slot[1] = status_code;
1143
1144         } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1145
1146                 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1147                  * by Stop and Signal instruction, followed by
1148                  * 'br -4'.
1149                  */
1150                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1151                 csa->lscsa->stopped_status.slot[1] = status_code;
1152
1153         } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1154
1155                 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1156                  * followed by 'br -4'.
1157                  */
1158                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1159                 csa->lscsa->stopped_status.slot[1] = status_code;
1160
1161         } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1162
1163                 /* SPU_Status[S,I]=1 - Illegal instruction followed
1164                  * by 'br -4'.
1165                  */
1166                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1167                 csa->lscsa->stopped_status.slot[1] = status_code;
1168
1169         } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1170
1171                 /* SPU_Status[P]=1 - Stop and Signal instruction
1172                  * followed by 'br -4'.
1173                  */
1174                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1175                 csa->lscsa->stopped_status.slot[1] = status_code;
1176
1177         } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1178
1179                 /* SPU_Status[H]=1 - Halt Conditional, followed
1180                  * by 'br -4'.
1181                  */
1182                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1183
1184         } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1185
1186                 /* SPU_Status[S]=1 - Two nop instructions.
1187                  */
1188                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1189
1190         } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1191
1192                 /* SPU_Status[I]=1 - Illegal instruction followed
1193                  * by 'br -4'.
1194                  */
1195                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1196
1197         }
1198 }
1199
1200 static inline void setup_spu_status_part2(struct spu_state *csa,
1201                                           struct spu *spu)
1202 {
1203         u32 mask;
1204
1205         /* Restore, Step 28:
1206          *     If the CSA.SPU_Status[I,S,H,P,R]=0 then
1207          *     add a 'br *' instruction to the end of
1208          *     the SPU based restore code.
1209          *
1210          *     NOTE: Rather than modifying the SPU executable, we
1211          *     instead add a new 'stopped_status' field to the
1212          *     LSCSA.  The SPU-side restore reads this field and
1213          *     takes the appropriate action when exiting.
1214          */
1215         mask = SPU_STATUS_INVALID_INSTR |
1216             SPU_STATUS_SINGLE_STEP |
1217             SPU_STATUS_STOPPED_BY_HALT |
1218             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1219         if (!(csa->prob.spu_status_R & mask)) {
1220                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1221         }
1222 }
1223
1224 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1225 {
1226         /* Restore, Step 29:
1227          *     Restore RA_GROUP_ID register and the
1228          *     RA_ENABLE reigster from the CSA.
1229          */
1230         spu_resource_allocation_groupID_set(spu,
1231                         csa->priv1.resource_allocation_groupID_RW);
1232         spu_resource_allocation_enable_set(spu,
1233                         csa->priv1.resource_allocation_enable_RW);
1234 }
1235
1236 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1237 {
1238         unsigned long addr = (unsigned long)&spu_restore_code[0];
1239         unsigned int ls_offset = 0x0;
1240         unsigned int size = sizeof(spu_restore_code);
1241         unsigned int tag = 0;
1242         unsigned int rclass = 0;
1243         unsigned int cmd = MFC_GETFS_CMD;
1244
1245         /* Restore, Step 37:
1246          *     Issue MFC DMA command to copy context
1247          *     restore code to local storage.
1248          */
1249         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1250 }
1251
1252 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1253 {
1254         /* Restore, Step 34:
1255          *     If CSA.MFC_CNTL[Ds]=1 (decrementer was
1256          *     running) then adjust decrementer, set
1257          *     decrementer running status in LSCSA,
1258          *     and set decrementer "wrapped" status
1259          *     in LSCSA.
1260          */
1261         if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1262                 cycles_t resume_time = get_cycles();
1263                 cycles_t delta_time = resume_time - csa->suspend_time;
1264
1265                 csa->lscsa->decr_status.slot[0] = SPU_DECR_STATUS_RUNNING;
1266                 if (csa->lscsa->decr.slot[0] < delta_time) {
1267                         csa->lscsa->decr_status.slot[0] |=
1268                                  SPU_DECR_STATUS_WRAPPED;
1269                 }
1270
1271                 csa->lscsa->decr.slot[0] -= delta_time;
1272         } else {
1273                 csa->lscsa->decr_status.slot[0] = 0;
1274         }
1275 }
1276
1277 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1278 {
1279         /* Restore, Step 35:
1280          *     Copy the CSA.PU_MB data into the LSCSA.
1281          */
1282         csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1283 }
1284
1285 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1286 {
1287         /* Restore, Step 36:
1288          *     Copy the CSA.PUINT_MB data into the LSCSA.
1289          */
1290         csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1291 }
1292
1293 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1294 {
1295         struct spu_problem __iomem *prob = spu->problem;
1296         u32 complete;
1297
1298         /* Restore, Step 40:
1299          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1300          *     context restore succeeded, otherwise context restore
1301          *     failed.
1302          */
1303         complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1304                     SPU_STATUS_STOPPED_BY_STOP);
1305         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1306 }
1307
1308 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1309 {
1310         struct spu_priv2 __iomem *priv2 = spu->priv2;
1311
1312         /* Restore, Step 41:
1313          *     Restore SPU_PrivCntl from the CSA.
1314          */
1315         out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1316         eieio();
1317 }
1318
1319 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1320 {
1321         struct spu_problem __iomem *prob = spu->problem;
1322         u32 mask;
1323
1324         /* Restore, Step 42:
1325          *     If any CSA.SPU_Status[I,S,H,P]=1, then
1326          *     restore the error or single step state.
1327          */
1328         mask = SPU_STATUS_INVALID_INSTR |
1329             SPU_STATUS_SINGLE_STEP |
1330             SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1331         if (csa->prob.spu_status_R & mask) {
1332                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1333                 eieio();
1334                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1335                                 SPU_STATUS_RUNNING);
1336         }
1337 }
1338
1339 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1340 {
1341         struct spu_problem __iomem *prob = spu->problem;
1342         u32 mask;
1343
1344         /* Restore, Step 43:
1345          *     If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1346          *     SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1347          *     then write '00' to SPU_RunCntl[R0R1] and wait
1348          *     for SPU_Status[R]=0.
1349          */
1350         mask = SPU_STATUS_INVALID_INSTR |
1351             SPU_STATUS_SINGLE_STEP |
1352             SPU_STATUS_STOPPED_BY_HALT |
1353             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1354         if (!(csa->prob.spu_status_R & mask)) {
1355                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1356                 eieio();
1357                 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1358                                  SPU_STATUS_RUNNING);
1359                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1360                 eieio();
1361                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1362                                 SPU_STATUS_RUNNING);
1363         }
1364 }
1365
1366 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1367 {
1368         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1369         unsigned int ls_offset = 0x0;
1370         unsigned int size = 16384;
1371         unsigned int tag = 0;
1372         unsigned int rclass = 0;
1373         unsigned int cmd = MFC_GET_CMD;
1374
1375         /* Restore, Step 44:
1376          *     Issue a DMA command to restore the first
1377          *     16kb of local storage from CSA.
1378          */
1379         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1380 }
1381
1382 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
1383 {
1384         struct spu_priv2 __iomem *priv2 = spu->priv2;
1385
1386         /* Restore, Step 47.
1387          *     Write MFC_Cntl[Sc,Sm]='1','0' to suspend
1388          *     the queue.
1389          */
1390         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
1391         eieio();
1392 }
1393
1394 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1395 {
1396         /* Restore, Step 49:
1397          *     Write INT_MASK_class0 with value of 0.
1398          *     Write INT_MASK_class1 with value of 0.
1399          *     Write INT_MASK_class2 with value of 0.
1400          *     Write INT_STAT_class0 with value of -1.
1401          *     Write INT_STAT_class1 with value of -1.
1402          *     Write INT_STAT_class2 with value of -1.
1403          */
1404         spin_lock_irq(&spu->register_lock);
1405         spu_int_mask_set(spu, 0, 0ul);
1406         spu_int_mask_set(spu, 1, 0ul);
1407         spu_int_mask_set(spu, 2, 0ul);
1408         spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
1409         spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
1410         spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
1411         spin_unlock_irq(&spu->register_lock);
1412 }
1413
1414 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1415 {
1416         struct spu_priv2 __iomem *priv2 = spu->priv2;
1417         int i;
1418
1419         /* Restore, Step 50:
1420          *     If MFC_Cntl[Se]!=0 then restore
1421          *     MFC command queues.
1422          */
1423         if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1424                 for (i = 0; i < 8; i++) {
1425                         out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1426                                  csa->priv2.puq[i].mfc_cq_data0_RW);
1427                         out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1428                                  csa->priv2.puq[i].mfc_cq_data1_RW);
1429                         out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1430                                  csa->priv2.puq[i].mfc_cq_data2_RW);
1431                         out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1432                                  csa->priv2.puq[i].mfc_cq_data3_RW);
1433                 }
1434                 for (i = 0; i < 16; i++) {
1435                         out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1436                                  csa->priv2.spuq[i].mfc_cq_data0_RW);
1437                         out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1438                                  csa->priv2.spuq[i].mfc_cq_data1_RW);
1439                         out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1440                                  csa->priv2.spuq[i].mfc_cq_data2_RW);
1441                         out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1442                                  csa->priv2.spuq[i].mfc_cq_data3_RW);
1443                 }
1444         }
1445         eieio();
1446 }
1447
1448 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1449 {
1450         struct spu_problem __iomem *prob = spu->problem;
1451
1452         /* Restore, Step 51:
1453          *     Restore the PPU_QueryMask register from CSA.
1454          */
1455         out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1456         eieio();
1457 }
1458
1459 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1460 {
1461         struct spu_problem __iomem *prob = spu->problem;
1462
1463         /* Restore, Step 52:
1464          *     Restore the PPU_QueryType register from CSA.
1465          */
1466         out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1467         eieio();
1468 }
1469
1470 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1471 {
1472         struct spu_priv2 __iomem *priv2 = spu->priv2;
1473
1474         /* Restore, Step 53:
1475          *     Restore the MFC_CSR_TSQ register from CSA.
1476          */
1477         out_be64(&priv2->spu_tag_status_query_RW,
1478                  csa->priv2.spu_tag_status_query_RW);
1479         eieio();
1480 }
1481
1482 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1483 {
1484         struct spu_priv2 __iomem *priv2 = spu->priv2;
1485
1486         /* Restore, Step 54:
1487          *     Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1488          *     registers from CSA.
1489          */
1490         out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1491         out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1492         eieio();
1493 }
1494
1495 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1496 {
1497         struct spu_priv2 __iomem *priv2 = spu->priv2;
1498
1499         /* Restore, Step 55:
1500          *     Restore the MFC_CSR_ATO register from CSA.
1501          */
1502         out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1503 }
1504
1505 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1506 {
1507         /* Restore, Step 56:
1508          *     Restore the MFC_TCLASS_ID register from CSA.
1509          */
1510         spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1511         eieio();
1512 }
1513
1514 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1515 {
1516         u64 ch0_cnt, ch0_data;
1517         u64 ch1_data;
1518
1519         /* Restore, Step 57:
1520          *    Set the Lock Line Reservation Lost Event by:
1521          *      1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1522          *      2. If CSA.SPU_Channel_0_Count=0 and
1523          *         CSA.SPU_Wr_Event_Mask[Lr]=1 and
1524          *         CSA.SPU_Event_Status[Lr]=0 then set
1525          *         CSA.SPU_Event_Status_Count=1.
1526          */
1527         ch0_cnt = csa->spu_chnlcnt_RW[0];
1528         ch0_data = csa->spu_chnldata_RW[0];
1529         ch1_data = csa->spu_chnldata_RW[1];
1530         csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1531         if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1532             (ch1_data & MFC_LLR_LOST_EVENT)) {
1533                 csa->spu_chnlcnt_RW[0] = 1;
1534         }
1535 }
1536
1537 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1538 {
1539         /* Restore, Step 58:
1540          *     If the status of the CSA software decrementer
1541          *     "wrapped" flag is set, OR in a '1' to
1542          *     CSA.SPU_Event_Status[Tm].
1543          */
1544         if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED))
1545                 return;
1546
1547         if ((csa->spu_chnlcnt_RW[0] == 0) &&
1548             (csa->spu_chnldata_RW[1] & 0x20) &&
1549             !(csa->spu_chnldata_RW[0] & 0x20))
1550                 csa->spu_chnlcnt_RW[0] = 1;
1551
1552         csa->spu_chnldata_RW[0] |= 0x20;
1553 }
1554
1555 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1556 {
1557         struct spu_priv2 __iomem *priv2 = spu->priv2;
1558         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1559         int i;
1560
1561         /* Restore, Step 59:
1562          *      Restore the following CH: [0,3,4,24,25,27]
1563          */
1564         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1565                 idx = ch_indices[i];
1566                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1567                 eieio();
1568                 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1569                 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1570                 eieio();
1571         }
1572 }
1573
1574 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1575 {
1576         struct spu_priv2 __iomem *priv2 = spu->priv2;
1577         u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1578         u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1579         u64 idx;
1580         int i;
1581
1582         /* Restore, Step 60:
1583          *     Restore the following CH: [9,21,23].
1584          */
1585         ch_counts[0] = 1UL;
1586         ch_counts[1] = csa->spu_chnlcnt_RW[21];
1587         ch_counts[2] = 1UL;
1588         for (i = 0; i < 3; i++) {
1589                 idx = ch_indices[i];
1590                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1591                 eieio();
1592                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1593                 eieio();
1594         }
1595 }
1596
1597 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1598 {
1599         struct spu_priv2 __iomem *priv2 = spu->priv2;
1600
1601         /* Restore, Step 61:
1602          *     Restore the SPU_LSLR register from CSA.
1603          */
1604         out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1605         eieio();
1606 }
1607
1608 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1609 {
1610         struct spu_priv2 __iomem *priv2 = spu->priv2;
1611
1612         /* Restore, Step 62:
1613          *     Restore the SPU_Cfg register from CSA.
1614          */
1615         out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1616         eieio();
1617 }
1618
1619 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1620 {
1621         /* Restore, Step 63:
1622          *     Restore PM_Trace_Tag_Wait_Mask from CSA.
1623          *     Not performed by this implementation.
1624          */
1625 }
1626
1627 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1628 {
1629         struct spu_problem __iomem *prob = spu->problem;
1630
1631         /* Restore, Step 64:
1632          *     Restore SPU_NPC from CSA.
1633          */
1634         out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1635         eieio();
1636 }
1637
1638 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1639 {
1640         struct spu_priv2 __iomem *priv2 = spu->priv2;
1641         int i;
1642
1643         /* Restore, Step 65:
1644          *     Restore MFC_RdSPU_MB from CSA.
1645          */
1646         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1647         eieio();
1648         out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1649         for (i = 0; i < 4; i++) {
1650                 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1651         }
1652         eieio();
1653 }
1654
1655 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1656 {
1657         struct spu_problem __iomem *prob = spu->problem;
1658         u32 dummy = 0;
1659
1660         /* Restore, Step 66:
1661          *     If CSA.MB_Stat[P]=0 (mailbox empty) then
1662          *     read from the PPU_MB register.
1663          */
1664         if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1665                 dummy = in_be32(&prob->pu_mb_R);
1666                 eieio();
1667         }
1668 }
1669
1670 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1671 {
1672         struct spu_priv2 __iomem *priv2 = spu->priv2;
1673         u64 dummy = 0UL;
1674
1675         /* Restore, Step 66:
1676          *     If CSA.MB_Stat[I]=0 (mailbox empty) then
1677          *     read from the PPUINT_MB register.
1678          */
1679         if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1680                 dummy = in_be64(&priv2->puint_mb_R);
1681                 eieio();
1682                 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1683                 eieio();
1684         }
1685 }
1686
1687 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1688 {
1689         /* Restore, Step 69:
1690          *     Restore the MFC_SR1 register from CSA.
1691          */
1692         spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1693         eieio();
1694 }
1695
1696 static inline void restore_other_spu_access(struct spu_state *csa,
1697                                             struct spu *spu)
1698 {
1699         /* Restore, Step 70:
1700          *     Restore other SPU mappings to this SPU. TBD.
1701          */
1702 }
1703
1704 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1705 {
1706         struct spu_problem __iomem *prob = spu->problem;
1707
1708         /* Restore, Step 71:
1709          *     If CSA.SPU_Status[R]=1 then write
1710          *     SPU_RunCntl[R0R1]='01'.
1711          */
1712         if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1713                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1714                 eieio();
1715         }
1716 }
1717
1718 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1719 {
1720         struct spu_priv2 __iomem *priv2 = spu->priv2;
1721
1722         /* Restore, Step 72:
1723          *    Restore the MFC_CNTL register for the CSA.
1724          */
1725         out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1726         eieio();
1727         /*
1728          * FIXME: this is to restart a DMA that we were processing
1729          *        before the save. better remember the fault information
1730          *        in the csa instead.
1731          */
1732         if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1733                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1734                 eieio();
1735         }
1736 }
1737
1738 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1739 {
1740         /* Restore, Step 73:
1741          *     Enable user-space access (if provided) to this
1742          *     SPU by mapping the virtual pages assigned to
1743          *     the SPU memory-mapped I/O (MMIO) for problem
1744          *     state. TBD.
1745          */
1746 }
1747
1748 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1749 {
1750         /* Restore, Step 74:
1751          *     Reset the "context switch active" flag.
1752          *     Not performed by this implementation.
1753          */
1754 }
1755
1756 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1757 {
1758         /* Restore, Step 75:
1759          *     Re-enable SPU interrupts.
1760          */
1761         spin_lock_irq(&spu->register_lock);
1762         spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1763         spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1764         spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1765         spin_unlock_irq(&spu->register_lock);
1766 }
1767
1768 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1769 {
1770         /*
1771          * Combined steps 2-18 of SPU context save sequence, which
1772          * quiesce the SPU state (disable SPU execution, MFC command
1773          * queues, decrementer, SPU interrupts, etc.).
1774          *
1775          * Returns      0 on success.
1776          *              2 if failed step 2.
1777          *              6 if failed step 6.
1778          */
1779
1780         if (check_spu_isolate(prev, spu)) {     /* Step 2. */
1781                 return 2;
1782         }
1783         disable_interrupts(prev, spu);          /* Step 3. */
1784         set_watchdog_timer(prev, spu);          /* Step 4. */
1785         inhibit_user_access(prev, spu);         /* Step 5. */
1786         if (check_spu_isolate(prev, spu)) {     /* Step 6. */
1787                 return 6;
1788         }
1789         set_switch_pending(prev, spu);          /* Step 7. */
1790         save_mfc_cntl(prev, spu);               /* Step 8. */
1791         save_spu_runcntl(prev, spu);            /* Step 9. */
1792         save_mfc_sr1(prev, spu);                /* Step 10. */
1793         save_spu_status(prev, spu);             /* Step 11. */
1794         save_mfc_decr(prev, spu);               /* Step 12. */
1795         halt_mfc_decr(prev, spu);               /* Step 13. */
1796         save_timebase(prev, spu);               /* Step 14. */
1797         remove_other_spu_access(prev, spu);     /* Step 15. */
1798         do_mfc_mssync(prev, spu);               /* Step 16. */
1799         issue_mfc_tlbie(prev, spu);             /* Step 17. */
1800         handle_pending_interrupts(prev, spu);   /* Step 18. */
1801
1802         return 0;
1803 }
1804
1805 static void save_csa(struct spu_state *prev, struct spu *spu)
1806 {
1807         /*
1808          * Combine steps 19-44 of SPU context save sequence, which
1809          * save regions of the privileged & problem state areas.
1810          */
1811
1812         save_mfc_queues(prev, spu);     /* Step 19. */
1813         save_ppu_querymask(prev, spu);  /* Step 20. */
1814         save_ppu_querytype(prev, spu);  /* Step 21. */
1815         save_ppu_tagstatus(prev, spu);  /* NEW.     */
1816         save_mfc_csr_tsq(prev, spu);    /* Step 22. */
1817         save_mfc_csr_cmd(prev, spu);    /* Step 23. */
1818         save_mfc_csr_ato(prev, spu);    /* Step 24. */
1819         save_mfc_tclass_id(prev, spu);  /* Step 25. */
1820         set_mfc_tclass_id(prev, spu);   /* Step 26. */
1821         save_mfc_cmd(prev, spu);        /* Step 26a - moved from 44. */
1822         purge_mfc_queue(prev, spu);     /* Step 27. */
1823         wait_purge_complete(prev, spu); /* Step 28. */
1824         setup_mfc_sr1(prev, spu);       /* Step 30. */
1825         save_spu_npc(prev, spu);        /* Step 31. */
1826         save_spu_privcntl(prev, spu);   /* Step 32. */
1827         reset_spu_privcntl(prev, spu);  /* Step 33. */
1828         save_spu_lslr(prev, spu);       /* Step 34. */
1829         reset_spu_lslr(prev, spu);      /* Step 35. */
1830         save_spu_cfg(prev, spu);        /* Step 36. */
1831         save_pm_trace(prev, spu);       /* Step 37. */
1832         save_mfc_rag(prev, spu);        /* Step 38. */
1833         save_ppu_mb_stat(prev, spu);    /* Step 39. */
1834         save_ppu_mb(prev, spu);         /* Step 40. */
1835         save_ppuint_mb(prev, spu);      /* Step 41. */
1836         save_ch_part1(prev, spu);       /* Step 42. */
1837         save_spu_mb(prev, spu);         /* Step 43. */
1838         reset_ch(prev, spu);            /* Step 45. */
1839 }
1840
1841 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1842 {
1843         /*
1844          * Perform steps 46-57 of SPU context save sequence,
1845          * which save regions of the local store and register
1846          * file.
1847          */
1848
1849         resume_mfc_queue(prev, spu);    /* Step 46. */
1850         /* Step 47. */
1851         setup_mfc_slbs(prev, spu, spu_save_code, sizeof(spu_save_code));
1852         set_switch_active(prev, spu);   /* Step 48. */
1853         enable_interrupts(prev, spu);   /* Step 49. */
1854         save_ls_16kb(prev, spu);        /* Step 50. */
1855         set_spu_npc(prev, spu);         /* Step 51. */
1856         set_signot1(prev, spu);         /* Step 52. */
1857         set_signot2(prev, spu);         /* Step 53. */
1858         send_save_code(prev, spu);      /* Step 54. */
1859         set_ppu_querymask(prev, spu);   /* Step 55. */
1860         wait_tag_complete(prev, spu);   /* Step 56. */
1861         wait_spu_stopped(prev, spu);    /* Step 57. */
1862 }
1863
1864 static void force_spu_isolate_exit(struct spu *spu)
1865 {
1866         struct spu_problem __iomem *prob = spu->problem;
1867         struct spu_priv2 __iomem *priv2 = spu->priv2;
1868
1869         /* Stop SPE execution and wait for completion. */
1870         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1871         iobarrier_rw();
1872         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1873
1874         /* Restart SPE master runcntl. */
1875         spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1876         iobarrier_w();
1877
1878         /* Initiate isolate exit request and wait for completion. */
1879         out_be64(&priv2->spu_privcntl_RW, 4LL);
1880         iobarrier_w();
1881         out_be32(&prob->spu_runcntl_RW, 2);
1882         iobarrier_rw();
1883         POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1884                                 & SPU_STATUS_STOPPED_BY_STOP));
1885
1886         /* Reset load request to normal. */
1887         out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1888         iobarrier_w();
1889 }
1890
1891 /**
1892  * stop_spu_isolate
1893  *      Check SPU run-control state and force isolated
1894  *      exit function as necessary.
1895  */
1896 static void stop_spu_isolate(struct spu *spu)
1897 {
1898         struct spu_problem __iomem *prob = spu->problem;
1899
1900         if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1901                 /* The SPU is in isolated state; the only way
1902                  * to get it out is to perform an isolated
1903                  * exit (clean) operation.
1904                  */
1905                 force_spu_isolate_exit(spu);
1906         }
1907 }
1908
1909 static void harvest(struct spu_state *prev, struct spu *spu)
1910 {
1911         /*
1912          * Perform steps 2-25 of SPU context restore sequence,
1913          * which resets an SPU either after a failed save, or
1914          * when using SPU for first time.
1915          */
1916
1917         disable_interrupts(prev, spu);          /* Step 2.  */
1918         inhibit_user_access(prev, spu);         /* Step 3.  */
1919         terminate_spu_app(prev, spu);           /* Step 4.  */
1920         set_switch_pending(prev, spu);          /* Step 5.  */
1921         stop_spu_isolate(spu);                  /* NEW.     */
1922         remove_other_spu_access(prev, spu);     /* Step 6.  */
1923         suspend_mfc_and_halt_decr(prev, spu);   /* Step 7.  */
1924         wait_suspend_mfc_complete(prev, spu);   /* Step 8.  */
1925         if (!suspend_spe(prev, spu))            /* Step 9.  */
1926                 clear_spu_status(prev, spu);    /* Step 10. */
1927         do_mfc_mssync(prev, spu);               /* Step 11. */
1928         issue_mfc_tlbie(prev, spu);             /* Step 12. */
1929         handle_pending_interrupts(prev, spu);   /* Step 13. */
1930         purge_mfc_queue(prev, spu);             /* Step 14. */
1931         wait_purge_complete(prev, spu);         /* Step 15. */
1932         reset_spu_privcntl(prev, spu);          /* Step 16. */
1933         reset_spu_lslr(prev, spu);              /* Step 17. */
1934         setup_mfc_sr1(prev, spu);               /* Step 18. */
1935         spu_invalidate_slbs(spu);               /* Step 19. */
1936         reset_ch_part1(prev, spu);              /* Step 20. */
1937         reset_ch_part2(prev, spu);              /* Step 21. */
1938         enable_interrupts(prev, spu);           /* Step 22. */
1939         set_switch_active(prev, spu);           /* Step 23. */
1940         set_mfc_tclass_id(prev, spu);           /* Step 24. */
1941         resume_mfc_queue(prev, spu);            /* Step 25. */
1942 }
1943
1944 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1945 {
1946         /*
1947          * Perform steps 26-40 of SPU context restore sequence,
1948          * which restores regions of the local store and register
1949          * file.
1950          */
1951
1952         set_watchdog_timer(next, spu);          /* Step 26. */
1953         setup_spu_status_part1(next, spu);      /* Step 27. */
1954         setup_spu_status_part2(next, spu);      /* Step 28. */
1955         restore_mfc_rag(next, spu);             /* Step 29. */
1956         /* Step 30. */
1957         setup_mfc_slbs(next, spu, spu_restore_code, sizeof(spu_restore_code));
1958         set_spu_npc(next, spu);                 /* Step 31. */
1959         set_signot1(next, spu);                 /* Step 32. */
1960         set_signot2(next, spu);                 /* Step 33. */
1961         setup_decr(next, spu);                  /* Step 34. */
1962         setup_ppu_mb(next, spu);                /* Step 35. */
1963         setup_ppuint_mb(next, spu);             /* Step 36. */
1964         send_restore_code(next, spu);           /* Step 37. */
1965         set_ppu_querymask(next, spu);           /* Step 38. */
1966         wait_tag_complete(next, spu);           /* Step 39. */
1967         wait_spu_stopped(next, spu);            /* Step 40. */
1968 }
1969
1970 static void restore_csa(struct spu_state *next, struct spu *spu)
1971 {
1972         /*
1973          * Combine steps 41-76 of SPU context restore sequence, which
1974          * restore regions of the privileged & problem state areas.
1975          */
1976
1977         restore_spu_privcntl(next, spu);        /* Step 41. */
1978         restore_status_part1(next, spu);        /* Step 42. */
1979         restore_status_part2(next, spu);        /* Step 43. */
1980         restore_ls_16kb(next, spu);             /* Step 44. */
1981         wait_tag_complete(next, spu);           /* Step 45. */
1982         suspend_mfc(next, spu);                 /* Step 46. */
1983         wait_suspend_mfc_complete(next, spu);   /* Step 47. */
1984         issue_mfc_tlbie(next, spu);             /* Step 48. */
1985         clear_interrupts(next, spu);            /* Step 49. */
1986         restore_mfc_queues(next, spu);          /* Step 50. */
1987         restore_ppu_querymask(next, spu);       /* Step 51. */
1988         restore_ppu_querytype(next, spu);       /* Step 52. */
1989         restore_mfc_csr_tsq(next, spu);         /* Step 53. */
1990         restore_mfc_csr_cmd(next, spu);         /* Step 54. */
1991         restore_mfc_csr_ato(next, spu);         /* Step 55. */
1992         restore_mfc_tclass_id(next, spu);       /* Step 56. */
1993         set_llr_event(next, spu);               /* Step 57. */
1994         restore_decr_wrapped(next, spu);        /* Step 58. */
1995         restore_ch_part1(next, spu);            /* Step 59. */
1996         restore_ch_part2(next, spu);            /* Step 60. */
1997         restore_spu_lslr(next, spu);            /* Step 61. */
1998         restore_spu_cfg(next, spu);             /* Step 62. */
1999         restore_pm_trace(next, spu);            /* Step 63. */
2000         restore_spu_npc(next, spu);             /* Step 64. */
2001         restore_spu_mb(next, spu);              /* Step 65. */
2002         check_ppu_mb_stat(next, spu);           /* Step 66. */
2003         check_ppuint_mb_stat(next, spu);        /* Step 67. */
2004         spu_invalidate_slbs(spu);               /* Modified Step 68. */
2005         restore_mfc_sr1(next, spu);             /* Step 69. */
2006         restore_other_spu_access(next, spu);    /* Step 70. */
2007         restore_spu_runcntl(next, spu);         /* Step 71. */
2008         restore_mfc_cntl(next, spu);            /* Step 72. */
2009         enable_user_access(next, spu);          /* Step 73. */
2010         reset_switch_active(next, spu);         /* Step 74. */
2011         reenable_interrupts(next, spu);         /* Step 75. */
2012 }
2013
2014 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2015 {
2016         int rc;
2017
2018         /*
2019          * SPU context save can be broken into three phases:
2020          *
2021          *     (a) quiesce [steps 2-16].
2022          *     (b) save of CSA, performed by PPE [steps 17-42]
2023          *     (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2024          *
2025          * Returns      0 on success.
2026          *              2,6 if failed to quiece SPU
2027          *              53 if SPU-side of save failed.
2028          */
2029
2030         rc = quiece_spu(prev, spu);             /* Steps 2-16. */
2031         switch (rc) {
2032         default:
2033         case 2:
2034         case 6:
2035                 harvest(prev, spu);
2036                 return rc;
2037                 break;
2038         case 0:
2039                 break;
2040         }
2041         save_csa(prev, spu);                    /* Steps 17-43. */
2042         save_lscsa(prev, spu);                  /* Steps 44-53. */
2043         return check_save_status(prev, spu);    /* Step 54.     */
2044 }
2045
2046 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2047 {
2048         int rc;
2049
2050         /*
2051          * SPU context restore can be broken into three phases:
2052          *
2053          *    (a) harvest (or reset) SPU [steps 2-24].
2054          *    (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2055          *    (c) restore CSA [steps 41-76], performed by PPE.
2056          *
2057          * The 'harvest' step is not performed here, but rather
2058          * as needed below.
2059          */
2060
2061         restore_lscsa(next, spu);               /* Steps 24-39. */
2062         rc = check_restore_status(next, spu);   /* Step 40.     */
2063         switch (rc) {
2064         default:
2065                 /* Failed. Return now. */
2066                 return rc;
2067                 break;
2068         case 0:
2069                 /* Fall through to next step. */
2070                 break;
2071         }
2072         restore_csa(next, spu);
2073
2074         return 0;
2075 }
2076
2077 /**
2078  * spu_save - SPU context save, with locking.
2079  * @prev: pointer to SPU context save area, to be saved.
2080  * @spu: pointer to SPU iomem structure.
2081  *
2082  * Acquire locks, perform the save operation then return.
2083  */
2084 int spu_save(struct spu_state *prev, struct spu *spu)
2085 {
2086         int rc;
2087
2088         acquire_spu_lock(spu);          /* Step 1.     */
2089         rc = __do_spu_save(prev, spu);  /* Steps 2-53. */
2090         release_spu_lock(spu);
2091         if (rc != 0 && rc != 2 && rc != 6) {
2092                 panic("%s failed on SPU[%d], rc=%d.\n",
2093                       __func__, spu->number, rc);
2094         }
2095         return 0;
2096 }
2097 EXPORT_SYMBOL_GPL(spu_save);
2098
2099 /**
2100  * spu_restore - SPU context restore, with harvest and locking.
2101  * @new: pointer to SPU context save area, to be restored.
2102  * @spu: pointer to SPU iomem structure.
2103  *
2104  * Perform harvest + restore, as we may not be coming
2105  * from a previous successful save operation, and the
2106  * hardware state is unknown.
2107  */
2108 int spu_restore(struct spu_state *new, struct spu *spu)
2109 {
2110         int rc;
2111
2112         acquire_spu_lock(spu);
2113         harvest(NULL, spu);
2114         spu->slb_replace = 0;
2115         rc = __do_spu_restore(new, spu);
2116         release_spu_lock(spu);
2117         if (rc) {
2118                 panic("%s failed on SPU[%d] rc=%d.\n",
2119                        __func__, spu->number, rc);
2120         }
2121         return rc;
2122 }
2123 EXPORT_SYMBOL_GPL(spu_restore);
2124
2125 static void init_prob(struct spu_state *csa)
2126 {
2127         csa->spu_chnlcnt_RW[9] = 1;
2128         csa->spu_chnlcnt_RW[21] = 16;
2129         csa->spu_chnlcnt_RW[23] = 1;
2130         csa->spu_chnlcnt_RW[28] = 1;
2131         csa->spu_chnlcnt_RW[30] = 1;
2132         csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2133         csa->prob.mb_stat_R = 0x000400;
2134 }
2135
2136 static void init_priv1(struct spu_state *csa)
2137 {
2138         /* Enable decode, relocate, tlbie response, master runcntl. */
2139         csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2140             MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2141             MFC_STATE1_PROBLEM_STATE_MASK |
2142             MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2143
2144         /* Enable OS-specific set of interrupts. */
2145         csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2146             CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2147             CLASS0_ENABLE_SPU_ERROR_INTR;
2148         csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2149             CLASS1_ENABLE_STORAGE_FAULT_INTR;
2150         csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2151             CLASS2_ENABLE_SPU_HALT_INTR |
2152             CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2153 }
2154
2155 static void init_priv2(struct spu_state *csa)
2156 {
2157         csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2158         csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2159             MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2160             MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2161 }
2162
2163 /**
2164  * spu_alloc_csa - allocate and initialize an SPU context save area.
2165  *
2166  * Allocate and initialize the contents of an SPU context save area.
2167  * This includes enabling address translation, interrupt masks, etc.,
2168  * as appropriate for the given OS environment.
2169  *
2170  * Note that storage for the 'lscsa' is allocated separately,
2171  * as it is by far the largest of the context save regions,
2172  * and may need to be pinned or otherwise specially aligned.
2173  */
2174 int spu_init_csa(struct spu_state *csa)
2175 {
2176         int rc;
2177
2178         if (!csa)
2179                 return -EINVAL;
2180         memset(csa, 0, sizeof(struct spu_state));
2181
2182         rc = spu_alloc_lscsa(csa);
2183         if (rc)
2184                 return rc;
2185
2186         spin_lock_init(&csa->register_lock);
2187
2188         init_prob(csa);
2189         init_priv1(csa);
2190         init_priv2(csa);
2191
2192         return 0;
2193 }
2194
2195 void spu_fini_csa(struct spu_state *csa)
2196 {
2197         spu_free_lscsa(csa);
2198 }