arch/powerpc/platforms/powernv/idle.c

   1 /*
   2  * PowerNV cpuidle code
   3  *
   4  * Copyright 2015 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/mm.h>
  14 #include <linux/slab.h>
  15 #include <linux/of.h>
  16 #include <linux/device.h>
  17 #include <linux/cpu.h>
  18
  19 #include <asm/firmware.h>
  20 #include <asm/opal.h>
  21 #include <asm/cputhreads.h>
  22 #include <asm/cpuidle.h>
  23 #include <asm/code-patching.h>
  24 #include <asm/smp.h>
  25
  26 #include "powernv.h"
  27 #include "subcore.h"
  28
  29 static u32 supported_cpuidle_states;
  30
  31 int pnv_save_sprs_for_winkle(void)
  32 {
  33         int cpu;
  34         int rc;
  35
  36         /*
  37          * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric accross
  38          * all cpus at boot. Get these reg values of current cpu and use the
  39          * same accross all cpus.
  40          */
  41         uint64_t lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1;
  42         uint64_t hid0_val = mfspr(SPRN_HID0);
  43         uint64_t hid1_val = mfspr(SPRN_HID1);
  44         uint64_t hid4_val = mfspr(SPRN_HID4);
  45         uint64_t hid5_val = mfspr(SPRN_HID5);
  46         uint64_t hmeer_val = mfspr(SPRN_HMEER);
  47
  48         for_each_possible_cpu(cpu) {
  49                 uint64_t pir = get_hard_smp_processor_id(cpu);
  50                 uint64_t hsprg0_val = (uint64_t)&paca[cpu];
  51
  52                 /*
  53                  * HSPRG0 is used to store the cpu's pointer to paca. Hence last
  54                  * 3 bits are guaranteed to be 0. Program slw to restore HSPRG0
  55                  * with 63rd bit set, so that when a thread wakes up at 0x100 we
  56                  * can use this bit to distinguish between fastsleep and
  57                  * deep winkle.
  58                  */
  59                 hsprg0_val |= 1;
  60
  61                 rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val);
  62                 if (rc != 0)
  63                         return rc;
  64
  65                 rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val);
  66                 if (rc != 0)
  67                         return rc;
  68
  69                 /* HIDs are per core registers */
  70                 if (cpu_thread_in_core(cpu) == 0) {
  71
  72                         rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val);
  73                         if (rc != 0)
  74                                 return rc;
  75
  76                         rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val);
  77                         if (rc != 0)
  78                                 return rc;
  79
  80                         rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val);
  81                         if (rc != 0)
  82                                 return rc;
  83
  84                         rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val);
  85                         if (rc != 0)
  86                                 return rc;
  87
  88                         rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val);
  89                         if (rc != 0)
  90                                 return rc;
  91                 }
  92         }
  93
  94         return 0;
  95 }
  96
  97 static void pnv_alloc_idle_core_states(void)
  98 {
  99         int i, j;
 100         int nr_cores = cpu_nr_cores();
 101         u32 *core_idle_state;
 102
 103         /*
 104          * core_idle_state - First 8 bits track the idle state of each thread
 105          * of the core. The 8th bit is the lock bit. Initially all thread bits
 106          * are set. They are cleared when the thread enters deep idle state
 107          * like sleep and winkle. Initially the lock bit is cleared.
 108          * The lock bit has 2 purposes
 109          * a. While the first thread is restoring core state, it prevents
 110          * other threads in the core from switching to process context.
 111          * b. While the last thread in the core is saving the core state, it
 112          * prevents a different thread from waking up.
 113          */
 114         for (i = 0; i < nr_cores; i++) {
 115                 int first_cpu = i * threads_per_core;
 116                 int node = cpu_to_node(first_cpu);
 117
 118                 core_idle_state = kmalloc_node(sizeof(u32), GFP_KERNEL, node);
 119                 *core_idle_state = PNV_CORE_IDLE_THREAD_BITS;
 120
 121                 for (j = 0; j < threads_per_core; j++) {
 122                         int cpu = first_cpu + j;
 123
 124                         paca[cpu].core_idle_state_ptr = core_idle_state;
 125                         paca[cpu].thread_idle_state = PNV_THREAD_RUNNING;
 126                         paca[cpu].thread_mask = 1 << j;
 127                 }
 128         }
 129
 130         update_subcore_sibling_mask();
 131
 132         if (supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED)
 133                 pnv_save_sprs_for_winkle();
 134 }
 135
 136 u32 pnv_get_supported_cpuidle_states(void)
 137 {
 138         return supported_cpuidle_states;
 139 }
 140 EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states);
 141
 142
 143 static void pnv_fastsleep_workaround_apply(void *info)
 144
 145 {
 146         int rc;
 147         int *err = info;
 148
 149         rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP,
 150                                         OPAL_CONFIG_IDLE_APPLY);
 151         if (rc)
 152                 *err = 1;
 153 }
 154
 155 /*
 156  * Used to store fastsleep workaround state
 157  * 0 - Workaround applied/undone at fastsleep entry/exit path (Default)
 158  * 1 - Workaround applied once, never undone.
 159  */
 160 static u8 fastsleep_workaround_applyonce;
 161
 162 static ssize_t show_fastsleep_workaround_applyonce(struct device *dev,
 163                 struct device_attribute *attr, char *buf)
 164 {
 165         return sprintf(buf, "%u\n", fastsleep_workaround_applyonce);
 166 }
 167
 168 static ssize_t store_fastsleep_workaround_applyonce(struct device *dev,
 169                 struct device_attribute *attr, const char *buf,
 170                 size_t count)
 171 {
 172         cpumask_t primary_thread_mask;
 173         int err;
 174         u8 val;
 175
 176         if (kstrtou8(buf, 0, &val) || val != 1)
 177                 return -EINVAL;
 178
 179         if (fastsleep_workaround_applyonce == 1)
 180                 return count;
 181
 182         /*
 183          * fastsleep_workaround_applyonce = 1 implies
 184          * fastsleep workaround needs to be left in 'applied' state on all
 185          * the cores. Do this by-
 186          * 1. Patching out the call to 'undo' workaround in fastsleep exit path
 187          * 2. Sending ipi to all the cores which have atleast one online thread
 188          * 3. Patching out the call to 'apply' workaround in fastsleep entry
 189          * path
 190          * There is no need to send ipi to cores which have all threads
 191          * offlined, as last thread of the core entering fastsleep or deeper
 192          * state would have applied workaround.
 193          */
 194         err = patch_instruction(
 195                 (unsigned int *)pnv_fastsleep_workaround_at_exit,
 196                 PPC_INST_NOP);
 197         if (err) {
 198                 pr_err("fastsleep_workaround_applyonce change failed while patching pnv_fastsleep_workaround_at_exit");
 199                 goto fail;
 200         }
 201
 202         get_online_cpus();
 203         primary_thread_mask = cpu_online_cores_map();
 204         on_each_cpu_mask(&primary_thread_mask,
 205                                 pnv_fastsleep_workaround_apply,
 206                                 &err, 1);
 207         put_online_cpus();
 208         if (err) {
 209                 pr_err("fastsleep_workaround_applyonce change failed while running pnv_fastsleep_workaround_apply");
 210                 goto fail;
 211         }
 212
 213         err = patch_instruction(
 214                 (unsigned int *)pnv_fastsleep_workaround_at_entry,
 215                 PPC_INST_NOP);
 216         if (err) {
 217                 pr_err("fastsleep_workaround_applyonce change failed while patching pnv_fastsleep_workaround_at_entry");
 218                 goto fail;
 219         }
 220
 221         fastsleep_workaround_applyonce = 1;
 222
 223         return count;
 224 fail:
 225         return -EIO;
 226 }
 227
 228 static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
 229                         show_fastsleep_workaround_applyonce,
 230                         store_fastsleep_workaround_applyonce);
 231
 232 static int __init pnv_init_idle_states(void)
 233 {
 234         struct device_node *power_mgt;
 235         int dt_idle_states;
 236         u32 *flags;
 237         int i;
 238
 239         supported_cpuidle_states = 0;
 240
 241         if (cpuidle_disable != IDLE_NO_OVERRIDE)
 242                 goto out;
 243
 244         if (!firmware_has_feature(FW_FEATURE_OPALv3))
 245                 goto out;
 246
 247         power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
 248         if (!power_mgt) {
 249                 pr_warn("opal: PowerMgmt Node not found\n");
 250                 goto out;
 251         }
 252         dt_idle_states = of_property_count_u32_elems(power_mgt,
 253                         "ibm,cpu-idle-state-flags");
 254         if (dt_idle_states < 0) {
 255                 pr_warn("cpuidle-powernv: no idle states found in the DT\n");
 256                 goto out;
 257         }
 258
 259         flags = kzalloc(sizeof(*flags) * dt_idle_states, GFP_KERNEL);
 260         if (of_property_read_u32_array(power_mgt,
 261                         "ibm,cpu-idle-state-flags", flags, dt_idle_states)) {
 262                 pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n");
 263                 goto out_free;
 264         }
 265
 266         for (i = 0; i < dt_idle_states; i++)
 267                 supported_cpuidle_states |= flags[i];
 268
 269         if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) {
 270                 patch_instruction(
 271                         (unsigned int *)pnv_fastsleep_workaround_at_entry,
 272                         PPC_INST_NOP);
 273                 patch_instruction(
 274                         (unsigned int *)pnv_fastsleep_workaround_at_exit,
 275                         PPC_INST_NOP);
 276         } else {
 277                 /*
 278                  * OPAL_PM_SLEEP_ENABLED_ER1 is set. It indicates that
 279                  * workaround is needed to use fastsleep. Provide sysfs
 280                  * control to choose how this workaround has to be applied.
 281                  */
 282                 device_create_file(cpu_subsys.dev_root,
 283                                 &dev_attr_fastsleep_workaround_applyonce);
 284         }
 285
 286         pnv_alloc_idle_core_states();
 287 out_free:
 288         kfree(flags);
 289 out:
 290         return 0;
 291 }
 292
 293 subsys_initcall(pnv_init_idle_states);