arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26 #include <linux/iommu.h>
  27 #include <linux/rculist.h>
  28 #include <linux/sizes.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/machdep.h>
  35 #include <asm/msi_bitmap.h>
  36 #include <asm/ppc-pci.h>
  37 #include <asm/opal.h>
  38 #include <asm/iommu.h>
  39 #include <asm/tce.h>
  40 #include <asm/xics.h>
  41 #include <asm/debug.h>
  42 #include <asm/firmware.h>
  43 #include <asm/pnv-pci.h>
  44 #include <asm/mmzone.h>
  45
  46 #include <misc/cxl-base.h>
  47
  48 #include "powernv.h"
  49 #include "pci.h"
  50
  51 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
  52 #define TCE32_TABLE_SIZE        ((0x10000000 / 0x1000) * 8)
  53
  54 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  55 #define POWERNV_IOMMU_MAX_LEVELS        5
  56
  57 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  58
  59 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  60                             const char *fmt, ...)
  61 {
  62         struct va_format vaf;
  63         va_list args;
  64         char pfix[32];
  65
  66         va_start(args, fmt);
  67
  68         vaf.fmt = fmt;
  69         vaf.va = &args;
  70
  71         if (pe->flags & PNV_IODA_PE_DEV)
  72                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  73         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  74                 sprintf(pfix, "%04x:%02x     ",
  75                         pci_domain_nr(pe->pbus), pe->pbus->number);
  76 #ifdef CONFIG_PCI_IOV
  77         else if (pe->flags & PNV_IODA_PE_VF)
  78                 sprintf(pfix, "%04x:%02x:%2x.%d",
  79                         pci_domain_nr(pe->parent_dev->bus),
  80                         (pe->rid & 0xff00) >> 8,
  81                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  82 #endif /* CONFIG_PCI_IOV*/
  83
  84         printk("%spci %s: [PE# %.3d] %pV",
  85                level, pfix, pe->pe_number, &vaf);
  86
  87         va_end(args);
  88 }
  89
  90 #define pe_err(pe, fmt, ...)                                    \
  91         pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
  92 #define pe_warn(pe, fmt, ...)                                   \
  93         pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
  94 #define pe_info(pe, fmt, ...)                                   \
  95         pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
  96
  97 static bool pnv_iommu_bypass_disabled __read_mostly;
  98
  99 static int __init iommu_setup(char *str)
 100 {
 101         if (!str)
 102                 return -EINVAL;
 103
 104         while (*str) {
 105                 if (!strncmp(str, "nobypass", 8)) {
 106                         pnv_iommu_bypass_disabled = true;
 107                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 108                         break;
 109                 }
 110                 str += strcspn(str, ",");
 111                 if (*str == ',')
 112                         str++;
 113         }
 114
 115         return 0;
 116 }
 117 early_param("iommu", iommu_setup);
 118
 119 /*
 120  * stdcix is only supposed to be used in hypervisor real mode as per
 121  * the architecture spec
 122  */
 123 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
 124 {
 125         __asm__ __volatile__("stdcix %0,0,%1"
 126                 : : "r" (val), "r" (paddr) : "memory");
 127 }
 128
 129 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
 130 {
 131         return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
 132                 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
 133 }
 134
 135 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 136 {
 137         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) {
 138                 pr_warn("%s: Invalid PE %d on PHB#%x\n",
 139                         __func__, pe_no, phb->hose->global_number);
 140                 return;
 141         }
 142
 143         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 144                 pr_debug("%s: PE %d was reserved on PHB#%x\n",
 145                          __func__, pe_no, phb->hose->global_number);
 146
 147         phb->ioda.pe_array[pe_no].phb = phb;
 148         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 149 }
 150
 151 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
 152 {
 153         unsigned long pe;
 154
 155         do {
 156                 pe = find_next_zero_bit(phb->ioda.pe_alloc,
 157                                         phb->ioda.total_pe, 0);
 158                 if (pe >= phb->ioda.total_pe)
 159                         return IODA_INVALID_PE;
 160         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
 161
 162         phb->ioda.pe_array[pe].phb = phb;
 163         phb->ioda.pe_array[pe].pe_number = pe;
 164         return pe;
 165 }
 166
 167 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
 168 {
 169         WARN_ON(phb->ioda.pe_array[pe].pdev);
 170
 171         memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
 172         clear_bit(pe, phb->ioda.pe_alloc);
 173 }
 174
 175 /* The default M64 BAR is shared by all PEs */
 176 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 177 {
 178         const char *desc;
 179         struct resource *r;
 180         s64 rc;
 181
 182         /* Configure the default M64 BAR */
 183         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 184                                          OPAL_M64_WINDOW_TYPE,
 185                                          phb->ioda.m64_bar_idx,
 186                                          phb->ioda.m64_base,
 187                                          0, /* unused */
 188                                          phb->ioda.m64_size);
 189         if (rc != OPAL_SUCCESS) {
 190                 desc = "configuring";
 191                 goto fail;
 192         }
 193
 194         /* Enable the default M64 BAR */
 195         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 196                                       OPAL_M64_WINDOW_TYPE,
 197                                       phb->ioda.m64_bar_idx,
 198                                       OPAL_ENABLE_M64_SPLIT);
 199         if (rc != OPAL_SUCCESS) {
 200                 desc = "enabling";
 201                 goto fail;
 202         }
 203
 204         /* Mark the M64 BAR assigned */
 205         set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
 206
 207         /*
 208          * Strip off the segment used by the reserved PE, which is
 209          * expected to be 0 or last one of PE capabicity.
 210          */
 211         r = &phb->hose->mem_resources[1];
 212         if (phb->ioda.reserved_pe == 0)
 213                 r->start += phb->ioda.m64_segsize;
 214         else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
 215                 r->end -= phb->ioda.m64_segsize;
 216         else
 217                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 218                         phb->ioda.reserved_pe);
 219
 220         return 0;
 221
 222 fail:
 223         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 224                 rc, desc, phb->ioda.m64_bar_idx);
 225         opal_pci_phb_mmio_enable(phb->opal_id,
 226                                  OPAL_M64_WINDOW_TYPE,
 227                                  phb->ioda.m64_bar_idx,
 228                                  OPAL_DISABLE_M64);
 229         return -EIO;
 230 }
 231
 232 static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev,
 233                                          unsigned long *pe_bitmap)
 234 {
 235         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 236         struct pnv_phb *phb = hose->private_data;
 237         struct resource *r;
 238         resource_size_t base, sgsz, start, end;
 239         int segno, i;
 240
 241         base = phb->ioda.m64_base;
 242         sgsz = phb->ioda.m64_segsize;
 243         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 244                 r = &pdev->resource[i];
 245                 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
 246                         continue;
 247
 248                 start = _ALIGN_DOWN(r->start - base, sgsz);
 249                 end = _ALIGN_UP(r->end - base, sgsz);
 250                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 251                         if (pe_bitmap)
 252                                 set_bit(segno, pe_bitmap);
 253                         else
 254                                 pnv_ioda_reserve_pe(phb, segno);
 255                 }
 256         }
 257 }
 258
 259 static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus,
 260                                      unsigned long *pe_bitmap,
 261                                      bool all)
 262 {
 263         struct pci_dev *pdev;
 264
 265         list_for_each_entry(pdev, &bus->devices, bus_list) {
 266                 pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap);
 267
 268                 if (all && pdev->subordinate)
 269                         pnv_ioda2_reserve_m64_pe(pdev->subordinate,
 270                                                  pe_bitmap, all);
 271         }
 272 }
 273
 274 static int pnv_ioda2_pick_m64_pe(struct pci_bus *bus, bool all)
 275 {
 276         struct pci_controller *hose = pci_bus_to_host(bus);
 277         struct pnv_phb *phb = hose->private_data;
 278         struct pnv_ioda_pe *master_pe, *pe;
 279         unsigned long size, *pe_alloc;
 280         int i;
 281
 282         /* Root bus shouldn't use M64 */
 283         if (pci_is_root_bus(bus))
 284                 return IODA_INVALID_PE;
 285
 286         /* Allocate bitmap */
 287         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
 288         pe_alloc = kzalloc(size, GFP_KERNEL);
 289         if (!pe_alloc) {
 290                 pr_warn("%s: Out of memory !\n",
 291                         __func__);
 292                 return IODA_INVALID_PE;
 293         }
 294
 295         /* Figure out reserved PE numbers by the PE */
 296         pnv_ioda2_reserve_m64_pe(bus, pe_alloc, all);
 297
 298         /*
 299          * the current bus might not own M64 window and that's all
 300          * contributed by its child buses. For the case, we needn't
 301          * pick M64 dependent PE#.
 302          */
 303         if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
 304                 kfree(pe_alloc);
 305                 return IODA_INVALID_PE;
 306         }
 307
 308         /*
 309          * Figure out the master PE and put all slave PEs to master
 310          * PE's list to form compound PE.
 311          */
 312         master_pe = NULL;
 313         i = -1;
 314         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
 315                 phb->ioda.total_pe) {
 316                 pe = &phb->ioda.pe_array[i];
 317
 318                 if (!master_pe) {
 319                         pe->flags |= PNV_IODA_PE_MASTER;
 320                         INIT_LIST_HEAD(&pe->slaves);
 321                         master_pe = pe;
 322                 } else {
 323                         pe->flags |= PNV_IODA_PE_SLAVE;
 324                         pe->master = master_pe;
 325                         list_add_tail(&pe->list, &master_pe->slaves);
 326                 }
 327         }
 328
 329         kfree(pe_alloc);
 330         return master_pe->pe_number;
 331 }
 332
 333 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 334 {
 335         struct pci_controller *hose = phb->hose;
 336         struct device_node *dn = hose->dn;
 337         struct resource *res;
 338         const u32 *r;
 339         u64 pci_addr;
 340
 341         /* FIXME: Support M64 for P7IOC */
 342         if (phb->type != PNV_PHB_IODA2) {
 343                 pr_info("  Not support M64 window\n");
 344                 return;
 345         }
 346
 347         if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
 348                 pr_info("  Firmware too old to support M64 window\n");
 349                 return;
 350         }
 351
 352         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 353         if (!r) {
 354                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 355                         dn->full_name);
 356                 return;
 357         }
 358
 359         res = &hose->mem_resources[1];
 360         res->start = of_translate_address(dn, r + 2);
 361         res->end = res->start + of_read_number(r + 4, 2) - 1;
 362         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 363         pci_addr = of_read_number(r, 2);
 364         hose->mem_offset[1] = res->start - pci_addr;
 365
 366         phb->ioda.m64_size = resource_size(res);
 367         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
 368         phb->ioda.m64_base = pci_addr;
 369
 370         pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
 371                         res->start, res->end, pci_addr);
 372
 373         /* Use last M64 BAR to cover M64 window */
 374         phb->ioda.m64_bar_idx = 15;
 375         phb->init_m64 = pnv_ioda2_init_m64;
 376         phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe;
 377         phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
 378 }
 379
 380 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 381 {
 382         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 383         struct pnv_ioda_pe *slave;
 384         s64 rc;
 385
 386         /* Fetch master PE */
 387         if (pe->flags & PNV_IODA_PE_SLAVE) {
 388                 pe = pe->master;
 389                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 390                         return;
 391
 392                 pe_no = pe->pe_number;
 393         }
 394
 395         /* Freeze master PE */
 396         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 397                                      pe_no,
 398                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 399         if (rc != OPAL_SUCCESS) {
 400                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 401                         __func__, rc, phb->hose->global_number, pe_no);
 402                 return;
 403         }
 404
 405         /* Freeze slave PEs */
 406         if (!(pe->flags & PNV_IODA_PE_MASTER))
 407                 return;
 408
 409         list_for_each_entry(slave, &pe->slaves, list) {
 410                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 411                                              slave->pe_number,
 412                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 413                 if (rc != OPAL_SUCCESS)
 414                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 415                                 __func__, rc, phb->hose->global_number,
 416                                 slave->pe_number);
 417         }
 418 }
 419
 420 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 421 {
 422         struct pnv_ioda_pe *pe, *slave;
 423         s64 rc;
 424
 425         /* Find master PE */
 426         pe = &phb->ioda.pe_array[pe_no];
 427         if (pe->flags & PNV_IODA_PE_SLAVE) {
 428                 pe = pe->master;
 429                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 430                 pe_no = pe->pe_number;
 431         }
 432
 433         /* Clear frozen state for master PE */
 434         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 435         if (rc != OPAL_SUCCESS) {
 436                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 437                         __func__, rc, opt, phb->hose->global_number, pe_no);
 438                 return -EIO;
 439         }
 440
 441         if (!(pe->flags & PNV_IODA_PE_MASTER))
 442                 return 0;
 443
 444         /* Clear frozen state for slave PEs */
 445         list_for_each_entry(slave, &pe->slaves, list) {
 446                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 447                                              slave->pe_number,
 448                                              opt);
 449                 if (rc != OPAL_SUCCESS) {
 450                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 451                                 __func__, rc, opt, phb->hose->global_number,
 452                                 slave->pe_number);
 453                         return -EIO;
 454                 }
 455         }
 456
 457         return 0;
 458 }
 459
 460 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 461 {
 462         struct pnv_ioda_pe *slave, *pe;
 463         u8 fstate, state;
 464         __be16 pcierr;
 465         s64 rc;
 466
 467         /* Sanity check on PE number */
 468         if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
 469                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 470
 471         /*
 472          * Fetch the master PE and the PE instance might be
 473          * not initialized yet.
 474          */
 475         pe = &phb->ioda.pe_array[pe_no];
 476         if (pe->flags & PNV_IODA_PE_SLAVE) {
 477                 pe = pe->master;
 478                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 479                 pe_no = pe->pe_number;
 480         }
 481
 482         /* Check the master PE */
 483         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 484                                         &state, &pcierr, NULL);
 485         if (rc != OPAL_SUCCESS) {
 486                 pr_warn("%s: Failure %lld getting "
 487                         "PHB#%x-PE#%x state\n",
 488                         __func__, rc,
 489                         phb->hose->global_number, pe_no);
 490                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 491         }
 492
 493         /* Check the slave PE */
 494         if (!(pe->flags & PNV_IODA_PE_MASTER))
 495                 return state;
 496
 497         list_for_each_entry(slave, &pe->slaves, list) {
 498                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 499                                                 slave->pe_number,
 500                                                 &fstate,
 501                                                 &pcierr,
 502                                                 NULL);
 503                 if (rc != OPAL_SUCCESS) {
 504                         pr_warn("%s: Failure %lld getting "
 505                                 "PHB#%x-PE#%x state\n",
 506                                 __func__, rc,
 507                                 phb->hose->global_number, slave->pe_number);
 508                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 509                 }
 510
 511                 /*
 512                  * Override the result based on the ascending
 513                  * priority.
 514                  */
 515                 if (fstate > state)
 516                         state = fstate;
 517         }
 518
 519         return state;
 520 }
 521
 522 /* Currently those 2 are only used when MSIs are enabled, this will change
 523  * but in the meantime, we need to protect them to avoid warnings
 524  */
 525 #ifdef CONFIG_PCI_MSI
 526 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 527 {
 528         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 529         struct pnv_phb *phb = hose->private_data;
 530         struct pci_dn *pdn = pci_get_pdn(dev);
 531
 532         if (!pdn)
 533                 return NULL;
 534         if (pdn->pe_number == IODA_INVALID_PE)
 535                 return NULL;
 536         return &phb->ioda.pe_array[pdn->pe_number];
 537 }
 538 #endif /* CONFIG_PCI_MSI */
 539
 540 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 541                                   struct pnv_ioda_pe *parent,
 542                                   struct pnv_ioda_pe *child,
 543                                   bool is_add)
 544 {
 545         const char *desc = is_add ? "adding" : "removing";
 546         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 547                               OPAL_REMOVE_PE_FROM_DOMAIN;
 548         struct pnv_ioda_pe *slave;
 549         long rc;
 550
 551         /* Parent PE affects child PE */
 552         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 553                                 child->pe_number, op);
 554         if (rc != OPAL_SUCCESS) {
 555                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 556                         rc, desc);
 557                 return -ENXIO;
 558         }
 559
 560         if (!(child->flags & PNV_IODA_PE_MASTER))
 561                 return 0;
 562
 563         /* Compound case: parent PE affects slave PEs */
 564         list_for_each_entry(slave, &child->slaves, list) {
 565                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 566                                         slave->pe_number, op);
 567                 if (rc != OPAL_SUCCESS) {
 568                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 569                                 rc, desc);
 570                         return -ENXIO;
 571                 }
 572         }
 573
 574         return 0;
 575 }
 576
 577 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 578                               struct pnv_ioda_pe *pe,
 579                               bool is_add)
 580 {
 581         struct pnv_ioda_pe *slave;
 582         struct pci_dev *pdev = NULL;
 583         int ret;
 584
 585         /*
 586          * Clear PE frozen state. If it's master PE, we need
 587          * clear slave PE frozen state as well.
 588          */
 589         if (is_add) {
 590                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 591                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 592                 if (pe->flags & PNV_IODA_PE_MASTER) {
 593                         list_for_each_entry(slave, &pe->slaves, list)
 594                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 595                                                           slave->pe_number,
 596                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 597                 }
 598         }
 599
 600         /*
 601          * Associate PE in PELT. We need add the PE into the
 602          * corresponding PELT-V as well. Otherwise, the error
 603          * originated from the PE might contribute to other
 604          * PEs.
 605          */
 606         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 607         if (ret)
 608                 return ret;
 609
 610         /* For compound PEs, any one affects all of them */
 611         if (pe->flags & PNV_IODA_PE_MASTER) {
 612                 list_for_each_entry(slave, &pe->slaves, list) {
 613                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 614                         if (ret)
 615                                 return ret;
 616                 }
 617         }
 618
 619         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 620                 pdev = pe->pbus->self;
 621         else if (pe->flags & PNV_IODA_PE_DEV)
 622                 pdev = pe->pdev->bus->self;
 623 #ifdef CONFIG_PCI_IOV
 624         else if (pe->flags & PNV_IODA_PE_VF)
 625                 pdev = pe->parent_dev;
 626 #endif /* CONFIG_PCI_IOV */
 627         while (pdev) {
 628                 struct pci_dn *pdn = pci_get_pdn(pdev);
 629                 struct pnv_ioda_pe *parent;
 630
 631                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 632                         parent = &phb->ioda.pe_array[pdn->pe_number];
 633                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 634                         if (ret)
 635                                 return ret;
 636                 }
 637
 638                 pdev = pdev->bus->self;
 639         }
 640
 641         return 0;
 642 }
 643
 644 #ifdef CONFIG_PCI_IOV
 645 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 646 {
 647         struct pci_dev *parent;
 648         uint8_t bcomp, dcomp, fcomp;
 649         int64_t rc;
 650         long rid_end, rid;
 651
 652         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 653         if (pe->pbus) {
 654                 int count;
 655
 656                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 657                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 658                 parent = pe->pbus->self;
 659                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 660                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 661                 else
 662                         count = 1;
 663
 664                 switch(count) {
 665                 case  1: bcomp = OpalPciBusAll;         break;
 666                 case  2: bcomp = OpalPciBus7Bits;       break;
 667                 case  4: bcomp = OpalPciBus6Bits;       break;
 668                 case  8: bcomp = OpalPciBus5Bits;       break;
 669                 case 16: bcomp = OpalPciBus4Bits;       break;
 670                 case 32: bcomp = OpalPciBus3Bits;       break;
 671                 default:
 672                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 673                                 count);
 674                         /* Do an exact match only */
 675                         bcomp = OpalPciBusAll;
 676                 }
 677                 rid_end = pe->rid + (count << 8);
 678         } else {
 679                 if (pe->flags & PNV_IODA_PE_VF)
 680                         parent = pe->parent_dev;
 681                 else
 682                         parent = pe->pdev->bus->self;
 683                 bcomp = OpalPciBusAll;
 684                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 685                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 686                 rid_end = pe->rid + 1;
 687         }
 688
 689         /* Clear the reverse map */
 690         for (rid = pe->rid; rid < rid_end; rid++)
 691                 phb->ioda.pe_rmap[rid] = 0;
 692
 693         /* Release from all parents PELT-V */
 694         while (parent) {
 695                 struct pci_dn *pdn = pci_get_pdn(parent);
 696                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 697                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 698                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 699                         /* XXX What to do in case of error ? */
 700                 }
 701                 parent = parent->bus->self;
 702         }
 703
 704         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 705                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 706
 707         /* Disassociate PE in PELT */
 708         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 709                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 710         if (rc)
 711                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 712         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 713                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 714         if (rc)
 715                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 716
 717         pe->pbus = NULL;
 718         pe->pdev = NULL;
 719         pe->parent_dev = NULL;
 720
 721         return 0;
 722 }
 723 #endif /* CONFIG_PCI_IOV */
 724
 725 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 726 {
 727         struct pci_dev *parent;
 728         uint8_t bcomp, dcomp, fcomp;
 729         long rc, rid_end, rid;
 730
 731         /* Bus validation ? */
 732         if (pe->pbus) {
 733                 int count;
 734
 735                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 736                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 737                 parent = pe->pbus->self;
 738                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 739                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 740                 else
 741                         count = 1;
 742
 743                 switch(count) {
 744                 case  1: bcomp = OpalPciBusAll;         break;
 745                 case  2: bcomp = OpalPciBus7Bits;       break;
 746                 case  4: bcomp = OpalPciBus6Bits;       break;
 747                 case  8: bcomp = OpalPciBus5Bits;       break;
 748                 case 16: bcomp = OpalPciBus4Bits;       break;
 749                 case 32: bcomp = OpalPciBus3Bits;       break;
 750                 default:
 751                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 752                                 count);
 753                         /* Do an exact match only */
 754                         bcomp = OpalPciBusAll;
 755                 }
 756                 rid_end = pe->rid + (count << 8);
 757         } else {
 758 #ifdef CONFIG_PCI_IOV
 759                 if (pe->flags & PNV_IODA_PE_VF)
 760                         parent = pe->parent_dev;
 761                 else
 762 #endif /* CONFIG_PCI_IOV */
 763                         parent = pe->pdev->bus->self;
 764                 bcomp = OpalPciBusAll;
 765                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 766                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 767                 rid_end = pe->rid + 1;
 768         }
 769
 770         /*
 771          * Associate PE in PELT. We need add the PE into the
 772          * corresponding PELT-V as well. Otherwise, the error
 773          * originated from the PE might contribute to other
 774          * PEs.
 775          */
 776         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 777                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 778         if (rc) {
 779                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 780                 return -ENXIO;
 781         }
 782
 783         /* Configure PELTV */
 784         pnv_ioda_set_peltv(phb, pe, true);
 785
 786         /* Setup reverse map */
 787         for (rid = pe->rid; rid < rid_end; rid++)
 788                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 789
 790         /* Setup one MVTs on IODA1 */
 791         if (phb->type != PNV_PHB_IODA1) {
 792                 pe->mve_number = 0;
 793                 goto out;
 794         }
 795
 796         pe->mve_number = pe->pe_number;
 797         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 798         if (rc != OPAL_SUCCESS) {
 799                 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 800                        rc, pe->mve_number);
 801                 pe->mve_number = -1;
 802         } else {
 803                 rc = opal_pci_set_mve_enable(phb->opal_id,
 804                                              pe->mve_number, OPAL_ENABLE_MVE);
 805                 if (rc) {
 806                         pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 807                                rc, pe->mve_number);
 808                         pe->mve_number = -1;
 809                 }
 810         }
 811
 812 out:
 813         return 0;
 814 }
 815
 816 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
 817                                        struct pnv_ioda_pe *pe)
 818 {
 819         struct pnv_ioda_pe *lpe;
 820
 821         list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
 822                 if (lpe->dma_weight < pe->dma_weight) {
 823                         list_add_tail(&pe->dma_link, &lpe->dma_link);
 824                         return;
 825                 }
 826         }
 827         list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
 828 }
 829
 830 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
 831 {
 832         /* This is quite simplistic. The "base" weight of a device
 833          * is 10. 0 means no DMA is to be accounted for it.
 834          */
 835
 836         /* If it's a bridge, no DMA */
 837         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
 838                 return 0;
 839
 840         /* Reduce the weight of slow USB controllers */
 841         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
 842             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
 843             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
 844                 return 3;
 845
 846         /* Increase the weight of RAID (includes Obsidian) */
 847         if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
 848                 return 15;
 849
 850         /* Default */
 851         return 10;
 852 }
 853
 854 #ifdef CONFIG_PCI_IOV
 855 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 856 {
 857         struct pci_dn *pdn = pci_get_pdn(dev);
 858         int i;
 859         struct resource *res, res2;
 860         resource_size_t size;
 861         u16 num_vfs;
 862
 863         if (!dev->is_physfn)
 864                 return -EINVAL;
 865
 866         /*
 867          * "offset" is in VFs.  The M64 windows are sized so that when they
 868          * are segmented, each segment is the same size as the IOV BAR.
 869          * Each segment is in a separate PE, and the high order bits of the
 870          * address are the PE number.  Therefore, each VF's BAR is in a
 871          * separate PE, and changing the IOV BAR start address changes the
 872          * range of PEs the VFs are in.
 873          */
 874         num_vfs = pdn->num_vfs;
 875         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 876                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 877                 if (!res->flags || !res->parent)
 878                         continue;
 879
 880                 if (!pnv_pci_is_mem_pref_64(res->flags))
 881                         continue;
 882
 883                 /*
 884                  * The actual IOV BAR range is determined by the start address
 885                  * and the actual size for num_vfs VFs BAR.  This check is to
 886                  * make sure that after shifting, the range will not overlap
 887                  * with another device.
 888                  */
 889                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 890                 res2.flags = res->flags;
 891                 res2.start = res->start + (size * offset);
 892                 res2.end = res2.start + (size * num_vfs) - 1;
 893
 894                 if (res2.end > res->end) {
 895                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 896                                 i, &res2, res, num_vfs, offset);
 897                         return -EBUSY;
 898                 }
 899         }
 900
 901         /*
 902          * After doing so, there would be a "hole" in the /proc/iomem when
 903          * offset is a positive value. It looks like the device return some
 904          * mmio back to the system, which actually no one could use it.
 905          */
 906         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 907                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 908                 if (!res->flags || !res->parent)
 909                         continue;
 910
 911                 if (!pnv_pci_is_mem_pref_64(res->flags))
 912                         continue;
 913
 914                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 915                 res2 = *res;
 916                 res->start += size * offset;
 917
 918                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n",
 919                          i, &res2, res, num_vfs, offset);
 920                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
 921         }
 922         return 0;
 923 }
 924 #endif /* CONFIG_PCI_IOV */
 925
 926 #if 0
 927 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 928 {
 929         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 930         struct pnv_phb *phb = hose->private_data;
 931         struct pci_dn *pdn = pci_get_pdn(dev);
 932         struct pnv_ioda_pe *pe;
 933         int pe_num;
 934
 935         if (!pdn) {
 936                 pr_err("%s: Device tree node not associated properly\n",
 937                            pci_name(dev));
 938                 return NULL;
 939         }
 940         if (pdn->pe_number != IODA_INVALID_PE)
 941                 return NULL;
 942
 943         /* PE#0 has been pre-set */
 944         if (dev->bus->number == 0)
 945                 pe_num = 0;
 946         else
 947                 pe_num = pnv_ioda_alloc_pe(phb);
 948         if (pe_num == IODA_INVALID_PE) {
 949                 pr_warning("%s: Not enough PE# available, disabling device\n",
 950                            pci_name(dev));
 951                 return NULL;
 952         }
 953
 954         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 955          * pointer in the PE data structure, both should be destroyed at the
 956          * same time. However, this needs to be looked at more closely again
 957          * once we actually start removing things (Hotplug, SR-IOV, ...)
 958          *
 959          * At some point we want to remove the PDN completely anyways
 960          */
 961         pe = &phb->ioda.pe_array[pe_num];
 962         pci_dev_get(dev);
 963         pdn->pcidev = dev;
 964         pdn->pe_number = pe_num;
 965         pe->pdev = dev;
 966         pe->pbus = NULL;
 967         pe->tce32_seg = -1;
 968         pe->mve_number = -1;
 969         pe->rid = dev->bus->number << 8 | pdn->devfn;
 970
 971         pe_info(pe, "Associated device to PE\n");
 972
 973         if (pnv_ioda_configure_pe(phb, pe)) {
 974                 /* XXX What do we do here ? */
 975                 if (pe_num)
 976                         pnv_ioda_free_pe(phb, pe_num);
 977                 pdn->pe_number = IODA_INVALID_PE;
 978                 pe->pdev = NULL;
 979                 pci_dev_put(dev);
 980                 return NULL;
 981         }
 982
 983         /* Assign a DMA weight to the device */
 984         pe->dma_weight = pnv_ioda_dma_weight(dev);
 985         if (pe->dma_weight != 0) {
 986                 phb->ioda.dma_weight += pe->dma_weight;
 987                 phb->ioda.dma_pe_count++;
 988         }
 989
 990         /* Link the PE */
 991         pnv_ioda_link_pe_by_weight(phb, pe);
 992
 993         return pe;
 994 }
 995 #endif /* Useful for SRIOV case */
 996
 997 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
 998 {
 999         struct pci_dev *dev;
1000
1001         list_for_each_entry(dev, &bus->devices, bus_list) {
1002                 struct pci_dn *pdn = pci_get_pdn(dev);
1003
1004                 if (pdn == NULL) {
1005                         pr_warn("%s: No device node associated with device !\n",
1006                                 pci_name(dev));
1007                         continue;
1008                 }
1009                 pdn->pe_number = pe->pe_number;
1010                 pe->dma_weight += pnv_ioda_dma_weight(dev);
1011                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1012                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1013         }
1014 }
1015
1016 /*
1017  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1018  * single PCI bus. Another one that contains the primary PCI bus and its
1019  * subordinate PCI devices and buses. The second type of PE is normally
1020  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1021  */
1022 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1023 {
1024         struct pci_controller *hose = pci_bus_to_host(bus);
1025         struct pnv_phb *phb = hose->private_data;
1026         struct pnv_ioda_pe *pe;
1027         int pe_num = IODA_INVALID_PE;
1028
1029         /* Check if PE is determined by M64 */
1030         if (phb->pick_m64_pe)
1031                 pe_num = phb->pick_m64_pe(bus, all);
1032
1033         /* The PE number isn't pinned by M64 */
1034         if (pe_num == IODA_INVALID_PE)
1035                 pe_num = pnv_ioda_alloc_pe(phb);
1036
1037         if (pe_num == IODA_INVALID_PE) {
1038                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1039                         __func__, pci_domain_nr(bus), bus->number);
1040                 return;
1041         }
1042
1043         pe = &phb->ioda.pe_array[pe_num];
1044         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1045         pe->pbus = bus;
1046         pe->pdev = NULL;
1047         pe->tce32_seg = -1;
1048         pe->mve_number = -1;
1049         pe->rid = bus->busn_res.start << 8;
1050         pe->dma_weight = 0;
1051
1052         if (all)
1053                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1054                         bus->busn_res.start, bus->busn_res.end, pe_num);
1055         else
1056                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1057                         bus->busn_res.start, pe_num);
1058
1059         if (pnv_ioda_configure_pe(phb, pe)) {
1060                 /* XXX What do we do here ? */
1061                 if (pe_num)
1062                         pnv_ioda_free_pe(phb, pe_num);
1063                 pe->pbus = NULL;
1064                 return;
1065         }
1066
1067         /* Associate it with all child devices */
1068         pnv_ioda_setup_same_PE(bus, pe);
1069
1070         /* Put PE to the list */
1071         list_add_tail(&pe->list, &phb->ioda.pe_list);
1072
1073         /* Account for one DMA PE if at least one DMA capable device exist
1074          * below the bridge
1075          */
1076         if (pe->dma_weight != 0) {
1077                 phb->ioda.dma_weight += pe->dma_weight;
1078                 phb->ioda.dma_pe_count++;
1079         }
1080
1081         /* Link the PE */
1082         pnv_ioda_link_pe_by_weight(phb, pe);
1083 }
1084
1085 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
1086 {
1087         struct pci_dev *dev;
1088
1089         pnv_ioda_setup_bus_PE(bus, false);
1090
1091         list_for_each_entry(dev, &bus->devices, bus_list) {
1092                 if (dev->subordinate) {
1093                         if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1094                                 pnv_ioda_setup_bus_PE(dev->subordinate, true);
1095                         else
1096                                 pnv_ioda_setup_PEs(dev->subordinate);
1097                 }
1098         }
1099 }
1100
1101 /*
1102  * Configure PEs so that the downstream PCI buses and devices
1103  * could have their associated PE#. Unfortunately, we didn't
1104  * figure out the way to identify the PLX bridge yet. So we
1105  * simply put the PCI bus and the subordinate behind the root
1106  * port to PE# here. The game rule here is expected to be changed
1107  * as soon as we can detected PLX bridge correctly.
1108  */
1109 static void pnv_pci_ioda_setup_PEs(void)
1110 {
1111         struct pci_controller *hose, *tmp;
1112         struct pnv_phb *phb;
1113
1114         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1115                 phb = hose->private_data;
1116
1117                 /* M64 layout might affect PE allocation */
1118                 if (phb->reserve_m64_pe)
1119                         phb->reserve_m64_pe(hose->bus, NULL, true);
1120
1121                 pnv_ioda_setup_PEs(hose->bus);
1122         }
1123 }
1124
1125 #ifdef CONFIG_PCI_IOV
1126 static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
1127 {
1128         struct pci_bus        *bus;
1129         struct pci_controller *hose;
1130         struct pnv_phb        *phb;
1131         struct pci_dn         *pdn;
1132         int                    i, j;
1133
1134         bus = pdev->bus;
1135         hose = pci_bus_to_host(bus);
1136         phb = hose->private_data;
1137         pdn = pci_get_pdn(pdev);
1138
1139         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1140                 for (j = 0; j < M64_PER_IOV; j++) {
1141                         if (pdn->m64_wins[i][j] == IODA_INVALID_M64)
1142                                 continue;
1143                         opal_pci_phb_mmio_enable(phb->opal_id,
1144                                 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0);
1145                         clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc);
1146                         pdn->m64_wins[i][j] = IODA_INVALID_M64;
1147                 }
1148
1149         return 0;
1150 }
1151
1152 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1153 {
1154         struct pci_bus        *bus;
1155         struct pci_controller *hose;
1156         struct pnv_phb        *phb;
1157         struct pci_dn         *pdn;
1158         unsigned int           win;
1159         struct resource       *res;
1160         int                    i, j;
1161         int64_t                rc;
1162         int                    total_vfs;
1163         resource_size_t        size, start;
1164         int                    pe_num;
1165         int                    vf_groups;
1166         int                    vf_per_group;
1167
1168         bus = pdev->bus;
1169         hose = pci_bus_to_host(bus);
1170         phb = hose->private_data;
1171         pdn = pci_get_pdn(pdev);
1172         total_vfs = pci_sriov_get_totalvfs(pdev);
1173
1174         /* Initialize the m64_wins to IODA_INVALID_M64 */
1175         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1176                 for (j = 0; j < M64_PER_IOV; j++)
1177                         pdn->m64_wins[i][j] = IODA_INVALID_M64;
1178
1179         if (pdn->m64_per_iov == M64_PER_IOV) {
1180                 vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV;
1181                 vf_per_group = (num_vfs <= M64_PER_IOV)? 1:
1182                         roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1183         } else {
1184                 vf_groups = 1;
1185                 vf_per_group = 1;
1186         }
1187
1188         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1189                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1190                 if (!res->flags || !res->parent)
1191                         continue;
1192
1193                 if (!pnv_pci_is_mem_pref_64(res->flags))
1194                         continue;
1195
1196                 for (j = 0; j < vf_groups; j++) {
1197                         do {
1198                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1199                                                 phb->ioda.m64_bar_idx + 1, 0);
1200
1201                                 if (win >= phb->ioda.m64_bar_idx + 1)
1202                                         goto m64_failed;
1203                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1204
1205                         pdn->m64_wins[i][j] = win;
1206
1207                         if (pdn->m64_per_iov == M64_PER_IOV) {
1208                                 size = pci_iov_resource_size(pdev,
1209                                                         PCI_IOV_RESOURCES + i);
1210                                 size = size * vf_per_group;
1211                                 start = res->start + size * j;
1212                         } else {
1213                                 size = resource_size(res);
1214                                 start = res->start;
1215                         }
1216
1217                         /* Map the M64 here */
1218                         if (pdn->m64_per_iov == M64_PER_IOV) {
1219                                 pe_num = pdn->offset + j;
1220                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1221                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1222                                                 pdn->m64_wins[i][j], 0);
1223                         }
1224
1225                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1226                                                  OPAL_M64_WINDOW_TYPE,
1227                                                  pdn->m64_wins[i][j],
1228                                                  start,
1229                                                  0, /* unused */
1230                                                  size);
1231
1232
1233                         if (rc != OPAL_SUCCESS) {
1234                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1235                                         win, rc);
1236                                 goto m64_failed;
1237                         }
1238
1239                         if (pdn->m64_per_iov == M64_PER_IOV)
1240                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1241                                      OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2);
1242                         else
1243                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1244                                      OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1);
1245
1246                         if (rc != OPAL_SUCCESS) {
1247                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1248                                         win, rc);
1249                                 goto m64_failed;
1250                         }
1251                 }
1252         }
1253         return 0;
1254
1255 m64_failed:
1256         pnv_pci_vf_release_m64(pdev);
1257         return -EBUSY;
1258 }
1259
1260 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1261                 int num);
1262 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1263
1264 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1265 {
1266         struct iommu_table    *tbl;
1267         int64_t               rc;
1268
1269         tbl = pe->table_group.tables[0];
1270         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1271         if (rc)
1272                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1273
1274         pnv_pci_ioda2_set_bypass(pe, false);
1275         if (pe->table_group.group) {
1276                 iommu_group_put(pe->table_group.group);
1277                 BUG_ON(pe->table_group.group);
1278         }
1279         pnv_pci_ioda2_table_free_pages(tbl);
1280         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1281 }
1282
1283 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1284 {
1285         struct pci_bus        *bus;
1286         struct pci_controller *hose;
1287         struct pnv_phb        *phb;
1288         struct pnv_ioda_pe    *pe, *pe_n;
1289         struct pci_dn         *pdn;
1290         u16                    vf_index;
1291         int64_t                rc;
1292
1293         bus = pdev->bus;
1294         hose = pci_bus_to_host(bus);
1295         phb = hose->private_data;
1296         pdn = pci_get_pdn(pdev);
1297
1298         if (!pdev->is_physfn)
1299                 return;
1300
1301         if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1302                 int   vf_group;
1303                 int   vf_per_group;
1304                 int   vf_index1;
1305
1306                 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1307
1308                 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++)
1309                         for (vf_index = vf_group * vf_per_group;
1310                                 vf_index < (vf_group + 1) * vf_per_group &&
1311                                 vf_index < num_vfs;
1312                                 vf_index++)
1313                                 for (vf_index1 = vf_group * vf_per_group;
1314                                         vf_index1 < (vf_group + 1) * vf_per_group &&
1315                                         vf_index1 < num_vfs;
1316                                         vf_index1++){
1317
1318                                         rc = opal_pci_set_peltv(phb->opal_id,
1319                                                 pdn->offset + vf_index,
1320                                                 pdn->offset + vf_index1,
1321                                                 OPAL_REMOVE_PE_FROM_DOMAIN);
1322
1323                                         if (rc)
1324                                             dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n",
1325                                                 __func__,
1326                                                 pdn->offset + vf_index1, rc);
1327                                 }
1328         }
1329
1330         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1331                 if (pe->parent_dev != pdev)
1332                         continue;
1333
1334                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1335
1336                 /* Remove from list */
1337                 mutex_lock(&phb->ioda.pe_list_mutex);
1338                 list_del(&pe->list);
1339                 mutex_unlock(&phb->ioda.pe_list_mutex);
1340
1341                 pnv_ioda_deconfigure_pe(phb, pe);
1342
1343                 pnv_ioda_free_pe(phb, pe->pe_number);
1344         }
1345 }
1346
1347 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1348 {
1349         struct pci_bus        *bus;
1350         struct pci_controller *hose;
1351         struct pnv_phb        *phb;
1352         struct pci_dn         *pdn;
1353         struct pci_sriov      *iov;
1354         u16 num_vfs;
1355
1356         bus = pdev->bus;
1357         hose = pci_bus_to_host(bus);
1358         phb = hose->private_data;
1359         pdn = pci_get_pdn(pdev);
1360         iov = pdev->sriov;
1361         num_vfs = pdn->num_vfs;
1362
1363         /* Release VF PEs */
1364         pnv_ioda_release_vf_PE(pdev, num_vfs);
1365
1366         if (phb->type == PNV_PHB_IODA2) {
1367                 if (pdn->m64_per_iov == 1)
1368                         pnv_pci_vf_resource_shift(pdev, -pdn->offset);
1369
1370                 /* Release M64 windows */
1371                 pnv_pci_vf_release_m64(pdev);
1372
1373                 /* Release PE numbers */
1374                 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1375                 pdn->offset = 0;
1376         }
1377 }
1378
1379 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1380                                        struct pnv_ioda_pe *pe);
1381 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1382 {
1383         struct pci_bus        *bus;
1384         struct pci_controller *hose;
1385         struct pnv_phb        *phb;
1386         struct pnv_ioda_pe    *pe;
1387         int                    pe_num;
1388         u16                    vf_index;
1389         struct pci_dn         *pdn;
1390         int64_t                rc;
1391
1392         bus = pdev->bus;
1393         hose = pci_bus_to_host(bus);
1394         phb = hose->private_data;
1395         pdn = pci_get_pdn(pdev);
1396
1397         if (!pdev->is_physfn)
1398                 return;
1399
1400         /* Reserve PE for each VF */
1401         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1402                 pe_num = pdn->offset + vf_index;
1403
1404                 pe = &phb->ioda.pe_array[pe_num];
1405                 pe->pe_number = pe_num;
1406                 pe->phb = phb;
1407                 pe->flags = PNV_IODA_PE_VF;
1408                 pe->pbus = NULL;
1409                 pe->parent_dev = pdev;
1410                 pe->tce32_seg = -1;
1411                 pe->mve_number = -1;
1412                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1413                            pci_iov_virtfn_devfn(pdev, vf_index);
1414
1415                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1416                         hose->global_number, pdev->bus->number,
1417                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1418                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1419
1420                 if (pnv_ioda_configure_pe(phb, pe)) {
1421                         /* XXX What do we do here ? */
1422                         if (pe_num)
1423                                 pnv_ioda_free_pe(phb, pe_num);
1424                         pe->pdev = NULL;
1425                         continue;
1426                 }
1427
1428                 /* Put PE to the list */
1429                 mutex_lock(&phb->ioda.pe_list_mutex);
1430                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1431                 mutex_unlock(&phb->ioda.pe_list_mutex);
1432
1433                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1434         }
1435
1436         if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1437                 int   vf_group;
1438                 int   vf_per_group;
1439                 int   vf_index1;
1440
1441                 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1442
1443                 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) {
1444                         for (vf_index = vf_group * vf_per_group;
1445                              vf_index < (vf_group + 1) * vf_per_group &&
1446                              vf_index < num_vfs;
1447                              vf_index++) {
1448                                 for (vf_index1 = vf_group * vf_per_group;
1449                                      vf_index1 < (vf_group + 1) * vf_per_group &&
1450                                      vf_index1 < num_vfs;
1451                                      vf_index1++) {
1452
1453                                         rc = opal_pci_set_peltv(phb->opal_id,
1454                                                 pdn->offset + vf_index,
1455                                                 pdn->offset + vf_index1,
1456                                                 OPAL_ADD_PE_TO_DOMAIN);
1457
1458                                         if (rc)
1459                                             dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n",
1460                                                 __func__,
1461                                                 pdn->offset + vf_index1, rc);
1462                                 }
1463                         }
1464                 }
1465         }
1466 }
1467
1468 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1469 {
1470         struct pci_bus        *bus;
1471         struct pci_controller *hose;
1472         struct pnv_phb        *phb;
1473         struct pci_dn         *pdn;
1474         int                    ret;
1475
1476         bus = pdev->bus;
1477         hose = pci_bus_to_host(bus);
1478         phb = hose->private_data;
1479         pdn = pci_get_pdn(pdev);
1480
1481         if (phb->type == PNV_PHB_IODA2) {
1482                 /* Calculate available PE for required VFs */
1483                 mutex_lock(&phb->ioda.pe_alloc_mutex);
1484                 pdn->offset = bitmap_find_next_zero_area(
1485                         phb->ioda.pe_alloc, phb->ioda.total_pe,
1486                         0, num_vfs, 0);
1487                 if (pdn->offset >= phb->ioda.total_pe) {
1488                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1489                         dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1490                         pdn->offset = 0;
1491                         return -EBUSY;
1492                 }
1493                 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1494                 pdn->num_vfs = num_vfs;
1495                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1496
1497                 /* Assign M64 window accordingly */
1498                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1499                 if (ret) {
1500                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1501                         goto m64_failed;
1502                 }
1503
1504                 /*
1505                  * When using one M64 BAR to map one IOV BAR, we need to shift
1506                  * the IOV BAR according to the PE# allocated to the VFs.
1507                  * Otherwise, the PE# for the VF will conflict with others.
1508                  */
1509                 if (pdn->m64_per_iov == 1) {
1510                         ret = pnv_pci_vf_resource_shift(pdev, pdn->offset);
1511                         if (ret)
1512                                 goto m64_failed;
1513                 }
1514         }
1515
1516         /* Setup VF PEs */
1517         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1518
1519         return 0;
1520
1521 m64_failed:
1522         bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1523         pdn->offset = 0;
1524
1525         return ret;
1526 }
1527
1528 int pcibios_sriov_disable(struct pci_dev *pdev)
1529 {
1530         pnv_pci_sriov_disable(pdev);
1531
1532         /* Release PCI data */
1533         remove_dev_pci_data(pdev);
1534         return 0;
1535 }
1536
1537 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1538 {
1539         /* Allocate PCI data */
1540         add_dev_pci_data(pdev);
1541
1542         pnv_pci_sriov_enable(pdev, num_vfs);
1543         return 0;
1544 }
1545 #endif /* CONFIG_PCI_IOV */
1546
1547 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1548 {
1549         struct pci_dn *pdn = pci_get_pdn(pdev);
1550         struct pnv_ioda_pe *pe;
1551
1552         /*
1553          * The function can be called while the PE#
1554          * hasn't been assigned. Do nothing for the
1555          * case.
1556          */
1557         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1558                 return;
1559
1560         pe = &phb->ioda.pe_array[pdn->pe_number];
1561         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1562         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1563         /*
1564          * Note: iommu_add_device() will fail here as
1565          * for physical PE: the device is already added by now;
1566          * for virtual PE: sysfs entries are not ready yet and
1567          * tce_iommu_bus_notifier will add the device to a group later.
1568          */
1569 }
1570
1571 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1572 {
1573         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1574         struct pnv_phb *phb = hose->private_data;
1575         struct pci_dn *pdn = pci_get_pdn(pdev);
1576         struct pnv_ioda_pe *pe;
1577         uint64_t top;
1578         bool bypass = false;
1579
1580         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1581                 return -ENODEV;;
1582
1583         pe = &phb->ioda.pe_array[pdn->pe_number];
1584         if (pe->tce_bypass_enabled) {
1585                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1586                 bypass = (dma_mask >= top);
1587         }
1588
1589         if (bypass) {
1590                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1591                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1592         } else {
1593                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1594                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1595         }
1596         *pdev->dev.dma_mask = dma_mask;
1597         return 0;
1598 }
1599
1600 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1601 {
1602         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1603         struct pnv_phb *phb = hose->private_data;
1604         struct pci_dn *pdn = pci_get_pdn(pdev);
1605         struct pnv_ioda_pe *pe;
1606         u64 end, mask;
1607
1608         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1609                 return 0;
1610
1611         pe = &phb->ioda.pe_array[pdn->pe_number];
1612         if (!pe->tce_bypass_enabled)
1613                 return __dma_get_required_mask(&pdev->dev);
1614
1615
1616         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1617         mask = 1ULL << (fls64(end) - 1);
1618         mask += mask - 1;
1619
1620         return mask;
1621 }
1622
1623 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1624                                    struct pci_bus *bus)
1625 {
1626         struct pci_dev *dev;
1627
1628         list_for_each_entry(dev, &bus->devices, bus_list) {
1629                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1630                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1631                 iommu_add_device(&dev->dev);
1632
1633                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1634                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1635         }
1636 }
1637
1638 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1639                 unsigned long index, unsigned long npages, bool rm)
1640 {
1641         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1642                         &tbl->it_group_list, struct iommu_table_group_link,
1643                         next);
1644         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1645                         struct pnv_ioda_pe, table_group);
1646         __be64 __iomem *invalidate = rm ?
1647                 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1648                 pe->phb->ioda.tce_inval_reg;
1649         unsigned long start, end, inc;
1650         const unsigned shift = tbl->it_page_shift;
1651
1652         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1653         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1654                         npages - 1);
1655
1656         /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1657         if (tbl->it_busno) {
1658                 start <<= shift;
1659                 end <<= shift;
1660                 inc = 128ull << shift;
1661                 start |= tbl->it_busno;
1662                 end |= tbl->it_busno;
1663         } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1664                 /* p7ioc-style invalidation, 2 TCEs per write */
1665                 start |= (1ull << 63);
1666                 end |= (1ull << 63);
1667                 inc = 16;
1668         } else {
1669                 /* Default (older HW) */
1670                 inc = 128;
1671         }
1672
1673         end |= inc - 1; /* round up end to be different than start */
1674
1675         mb(); /* Ensure above stores are visible */
1676         while (start <= end) {
1677                 if (rm)
1678                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1679                 else
1680                         __raw_writeq(cpu_to_be64(start), invalidate);
1681                 start += inc;
1682         }
1683
1684         /*
1685          * The iommu layer will do another mb() for us on build()
1686          * and we don't care on free()
1687          */
1688 }
1689
1690 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1691                 long npages, unsigned long uaddr,
1692                 enum dma_data_direction direction,
1693                 struct dma_attrs *attrs)
1694 {
1695         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1696                         attrs);
1697
1698         if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1699                 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1700
1701         return ret;
1702 }
1703
1704 #ifdef CONFIG_IOMMU_API
1705 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1706                 unsigned long *hpa, enum dma_data_direction *direction)
1707 {
1708         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1709
1710         if (!ret && (tbl->it_type &
1711                         (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1712                 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1713
1714         return ret;
1715 }
1716 #endif
1717
1718 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1719                 long npages)
1720 {
1721         pnv_tce_free(tbl, index, npages);
1722
1723         if (tbl->it_type & TCE_PCI_SWINV_FREE)
1724                 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1725 }
1726
1727 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1728         .set = pnv_ioda1_tce_build,
1729 #ifdef CONFIG_IOMMU_API
1730         .exchange = pnv_ioda1_tce_xchg,
1731 #endif
1732         .clear = pnv_ioda1_tce_free,
1733         .get = pnv_tce_get,
1734 };
1735
1736 static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe)
1737 {
1738         /* 01xb - invalidate TCEs that match the specified PE# */
1739         unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF);
1740         struct pnv_phb *phb = pe->phb;
1741
1742         if (!phb->ioda.tce_inval_reg)
1743                 return;
1744
1745         mb(); /* Ensure above stores are visible */
1746         __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1747 }
1748
1749 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1750                 __be64 __iomem *invalidate, unsigned shift,
1751                 unsigned long index, unsigned long npages)
1752 {
1753         unsigned long start, end, inc;
1754
1755         /* We'll invalidate DMA address in PE scope */
1756         start = 0x2ull << 60;
1757         start |= (pe_number & 0xFF);
1758         end = start;
1759
1760         /* Figure out the start, end and step */
1761         start |= (index << shift);
1762         end |= ((index + npages - 1) << shift);
1763         inc = (0x1ull << shift);
1764         mb();
1765
1766         while (start <= end) {
1767                 if (rm)
1768                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1769                 else
1770                         __raw_writeq(cpu_to_be64(start), invalidate);
1771                 start += inc;
1772         }
1773 }
1774
1775 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1776                 unsigned long index, unsigned long npages, bool rm)
1777 {
1778         struct iommu_table_group_link *tgl;
1779
1780         list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1781                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1782                                 struct pnv_ioda_pe, table_group);
1783                 __be64 __iomem *invalidate = rm ?
1784                         (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1785                         pe->phb->ioda.tce_inval_reg;
1786
1787                 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1788                         invalidate, tbl->it_page_shift,
1789                         index, npages);
1790         }
1791 }
1792
1793 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1794                 long npages, unsigned long uaddr,
1795                 enum dma_data_direction direction,
1796                 struct dma_attrs *attrs)
1797 {
1798         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1799                         attrs);
1800
1801         if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1802                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1803
1804         return ret;
1805 }
1806
1807 #ifdef CONFIG_IOMMU_API
1808 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1809                 unsigned long *hpa, enum dma_data_direction *direction)
1810 {
1811         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1812
1813         if (!ret && (tbl->it_type &
1814                         (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1815                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1816
1817         return ret;
1818 }
1819 #endif
1820
1821 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1822                 long npages)
1823 {
1824         pnv_tce_free(tbl, index, npages);
1825
1826         if (tbl->it_type & TCE_PCI_SWINV_FREE)
1827                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1828 }
1829
1830 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1831 {
1832         pnv_pci_ioda2_table_free_pages(tbl);
1833         iommu_free_table(tbl, "pnv");
1834 }
1835
1836 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1837         .set = pnv_ioda2_tce_build,
1838 #ifdef CONFIG_IOMMU_API
1839         .exchange = pnv_ioda2_tce_xchg,
1840 #endif
1841         .clear = pnv_ioda2_tce_free,
1842         .get = pnv_tce_get,
1843         .free = pnv_ioda2_table_free,
1844 };
1845
1846 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1847                                       struct pnv_ioda_pe *pe, unsigned int base,
1848                                       unsigned int segs)
1849 {
1850
1851         struct page *tce_mem = NULL;
1852         struct iommu_table *tbl;
1853         unsigned int i;
1854         int64_t rc;
1855         void *addr;
1856
1857         /* XXX FIXME: Handle 64-bit only DMA devices */
1858         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1859         /* XXX FIXME: Allocate multi-level tables on PHB3 */
1860
1861         /* We shouldn't already have a 32-bit DMA associated */
1862         if (WARN_ON(pe->tce32_seg >= 0))
1863                 return;
1864
1865         tbl = pnv_pci_table_alloc(phb->hose->node);
1866         iommu_register_group(&pe->table_group, phb->hose->global_number,
1867                         pe->pe_number);
1868         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
1869
1870         /* Grab a 32-bit TCE table */
1871         pe->tce32_seg = base;
1872         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1873                 (base << 28), ((base + segs) << 28) - 1);
1874
1875         /* XXX Currently, we allocate one big contiguous table for the
1876          * TCEs. We only really need one chunk per 256M of TCE space
1877          * (ie per segment) but that's an optimization for later, it
1878          * requires some added smarts with our get/put_tce implementation
1879          */
1880         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1881                                    get_order(TCE32_TABLE_SIZE * segs));
1882         if (!tce_mem) {
1883                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1884                 goto fail;
1885         }
1886         addr = page_address(tce_mem);
1887         memset(addr, 0, TCE32_TABLE_SIZE * segs);
1888
1889         /* Configure HW */
1890         for (i = 0; i < segs; i++) {
1891                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1892                                               pe->pe_number,
1893                                               base + i, 1,
1894                                               __pa(addr) + TCE32_TABLE_SIZE * i,
1895                                               TCE32_TABLE_SIZE, 0x1000);
1896                 if (rc) {
1897                         pe_err(pe, " Failed to configure 32-bit TCE table,"
1898                                " err %ld\n", rc);
1899                         goto fail;
1900                 }
1901         }
1902
1903         /* Setup linux iommu table */
1904         pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
1905                                   base << 28, IOMMU_PAGE_SHIFT_4K);
1906
1907         /* OPAL variant of P7IOC SW invalidated TCEs */
1908         if (phb->ioda.tce_inval_reg)
1909                 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
1910                                  TCE_PCI_SWINV_FREE   |
1911                                  TCE_PCI_SWINV_PAIR);
1912
1913         tbl->it_ops = &pnv_ioda1_iommu_ops;
1914         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
1915         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
1916         iommu_init_table(tbl, phb->hose->node);
1917
1918         if (pe->flags & PNV_IODA_PE_DEV) {
1919                 /*
1920                  * Setting table base here only for carrying iommu_group
1921                  * further down to let iommu_add_device() do the job.
1922                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
1923                  */
1924                 set_iommu_table_base(&pe->pdev->dev, tbl);
1925                 iommu_add_device(&pe->pdev->dev);
1926         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
1927                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
1928
1929         return;
1930  fail:
1931         /* XXX Failure: Try to fallback to 64-bit only ? */
1932         if (pe->tce32_seg >= 0)
1933                 pe->tce32_seg = -1;
1934         if (tce_mem)
1935                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
1936         if (tbl) {
1937                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
1938                 iommu_free_table(tbl, "pnv");
1939         }
1940 }
1941
1942 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
1943                 int num, struct iommu_table *tbl)
1944 {
1945         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1946                         table_group);
1947         struct pnv_phb *phb = pe->phb;
1948         int64_t rc;
1949         const unsigned long size = tbl->it_indirect_levels ?
1950                         tbl->it_level_size : tbl->it_size;
1951         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
1952         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
1953
1954         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
1955                         start_addr, start_addr + win_size - 1,
1956                         IOMMU_PAGE_SIZE(tbl));
1957
1958         /*
1959          * Map TCE table through TVT. The TVE index is the PE number
1960          * shifted by 1 bit for 32-bits DMA space.
1961          */
1962         rc = opal_pci_map_pe_dma_window(phb->opal_id,
1963                         pe->pe_number,
1964                         (pe->pe_number << 1) + num,
1965                         tbl->it_indirect_levels + 1,
1966                         __pa(tbl->it_base),
1967                         size << 3,
1968                         IOMMU_PAGE_SIZE(tbl));
1969         if (rc) {
1970                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
1971                 return rc;
1972         }
1973
1974         pnv_pci_link_table_and_group(phb->hose->node, num,
1975                         tbl, &pe->table_group);
1976         pnv_pci_ioda2_tce_invalidate_entire(pe);
1977
1978         return 0;
1979 }
1980
1981 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
1982 {
1983         uint16_t window_id = (pe->pe_number << 1 ) + 1;
1984         int64_t rc;
1985
1986         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
1987         if (enable) {
1988                 phys_addr_t top = memblock_end_of_DRAM();
1989
1990                 top = roundup_pow_of_two(top);
1991                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1992                                                      pe->pe_number,
1993                                                      window_id,
1994                                                      pe->tce_bypass_base,
1995                                                      top);
1996         } else {
1997                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1998                                                      pe->pe_number,
1999                                                      window_id,
2000                                                      pe->tce_bypass_base,
2001                                                      0);
2002         }
2003         if (rc)
2004                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2005         else
2006                 pe->tce_bypass_enabled = enable;
2007 }
2008
2009 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2010                 __u32 page_shift, __u64 window_size, __u32 levels,
2011                 struct iommu_table *tbl);
2012
2013 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2014                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2015                 struct iommu_table **ptbl)
2016 {
2017         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2018                         table_group);
2019         int nid = pe->phb->hose->node;
2020         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2021         long ret;
2022         struct iommu_table *tbl;
2023
2024         tbl = pnv_pci_table_alloc(nid);
2025         if (!tbl)
2026                 return -ENOMEM;
2027
2028         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2029                         bus_offset, page_shift, window_size,
2030                         levels, tbl);
2031         if (ret) {
2032                 iommu_free_table(tbl, "pnv");
2033                 return ret;
2034         }
2035
2036         tbl->it_ops = &pnv_ioda2_iommu_ops;
2037         if (pe->phb->ioda.tce_inval_reg)
2038                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2039
2040         *ptbl = tbl;
2041
2042         return 0;
2043 }
2044
2045 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2046 {
2047         struct iommu_table *tbl = NULL;
2048         long rc;
2049
2050         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2051                         IOMMU_PAGE_SHIFT_4K,
2052                         pe->table_group.tce32_size,
2053                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2054         if (rc) {
2055                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2056                                 rc);
2057                 return rc;
2058         }
2059
2060         iommu_init_table(tbl, pe->phb->hose->node);
2061
2062         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2063         if (rc) {
2064                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2065                                 rc);
2066                 pnv_ioda2_table_free(tbl);
2067                 return rc;
2068         }
2069
2070         if (!pnv_iommu_bypass_disabled)
2071                 pnv_pci_ioda2_set_bypass(pe, true);
2072
2073         /* OPAL variant of PHB3 invalidated TCEs */
2074         if (pe->phb->ioda.tce_inval_reg)
2075                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2076
2077         /*
2078          * Setting table base here only for carrying iommu_group
2079          * further down to let iommu_add_device() do the job.
2080          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2081          */
2082         if (pe->flags & PNV_IODA_PE_DEV)
2083                 set_iommu_table_base(&pe->pdev->dev, tbl);
2084
2085         return 0;
2086 }
2087
2088 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2089 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2090                 int num)
2091 {
2092         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2093                         table_group);
2094         struct pnv_phb *phb = pe->phb;
2095         long ret;
2096
2097         pe_info(pe, "Removing DMA window #%d\n", num);
2098
2099         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2100                         (pe->pe_number << 1) + num,
2101                         0/* levels */, 0/* table address */,
2102                         0/* table size */, 0/* page size */);
2103         if (ret)
2104                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2105         else
2106                 pnv_pci_ioda2_tce_invalidate_entire(pe);
2107
2108         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2109
2110         return ret;
2111 }
2112 #endif
2113
2114 #ifdef CONFIG_IOMMU_API
2115 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2116                 __u64 window_size, __u32 levels)
2117 {
2118         unsigned long bytes = 0;
2119         const unsigned window_shift = ilog2(window_size);
2120         unsigned entries_shift = window_shift - page_shift;
2121         unsigned table_shift = entries_shift + 3;
2122         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2123         unsigned long direct_table_size;
2124
2125         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2126                         (window_size > memory_hotplug_max()) ||
2127                         !is_power_of_2(window_size))
2128                 return 0;
2129
2130         /* Calculate a direct table size from window_size and levels */
2131         entries_shift = (entries_shift + levels - 1) / levels;
2132         table_shift = entries_shift + 3;
2133         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2134         direct_table_size =  1UL << table_shift;
2135
2136         for ( ; levels; --levels) {
2137                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2138
2139                 tce_table_size /= direct_table_size;
2140                 tce_table_size <<= 3;
2141                 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2142         }
2143
2144         return bytes;
2145 }
2146
2147 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2148 {
2149         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2150                                                 table_group);
2151         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2152         struct iommu_table *tbl = pe->table_group.tables[0];
2153
2154         pnv_pci_ioda2_set_bypass(pe, false);
2155         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2156         pnv_ioda2_table_free(tbl);
2157 }
2158
2159 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2160 {
2161         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2162                                                 table_group);
2163
2164         pnv_pci_ioda2_setup_default_config(pe);
2165 }
2166
2167 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2168         .get_table_size = pnv_pci_ioda2_get_table_size,
2169         .create_table = pnv_pci_ioda2_create_table,
2170         .set_window = pnv_pci_ioda2_set_window,
2171         .unset_window = pnv_pci_ioda2_unset_window,
2172         .take_ownership = pnv_ioda2_take_ownership,
2173         .release_ownership = pnv_ioda2_release_ownership,
2174 };
2175 #endif
2176
2177 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2178 {
2179         const __be64 *swinvp;
2180
2181         /* OPAL variant of PHB3 invalidated TCEs */
2182         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2183         if (!swinvp)
2184                 return;
2185
2186         phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2187         phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2188 }
2189
2190 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2191                 unsigned levels, unsigned long limit,
2192                 unsigned long *current_offset)
2193 {
2194         struct page *tce_mem = NULL;
2195         __be64 *addr, *tmp;
2196         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2197         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2198         unsigned entries = 1UL << (shift - 3);
2199         long i;
2200
2201         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2202         if (!tce_mem) {
2203                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2204                 return NULL;
2205         }
2206         addr = page_address(tce_mem);
2207         memset(addr, 0, allocated);
2208
2209         --levels;
2210         if (!levels) {
2211                 *current_offset += allocated;
2212                 return addr;
2213         }
2214
2215         for (i = 0; i < entries; ++i) {
2216                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2217                                 levels, limit, current_offset);
2218                 if (!tmp)
2219                         break;
2220
2221                 addr[i] = cpu_to_be64(__pa(tmp) |
2222                                 TCE_PCI_READ | TCE_PCI_WRITE);
2223
2224                 if (*current_offset >= limit)
2225                         break;
2226         }
2227
2228         return addr;
2229 }
2230
2231 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2232                 unsigned long size, unsigned level);
2233
2234 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2235                 __u32 page_shift, __u64 window_size, __u32 levels,
2236                 struct iommu_table *tbl)
2237 {
2238         void *addr;
2239         unsigned long offset = 0, level_shift;
2240         const unsigned window_shift = ilog2(window_size);
2241         unsigned entries_shift = window_shift - page_shift;
2242         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2243         const unsigned long tce_table_size = 1UL << table_shift;
2244
2245         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2246                 return -EINVAL;
2247
2248         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2249                 return -EINVAL;
2250
2251         /* Adjust direct table size from window_size and levels */
2252         entries_shift = (entries_shift + levels - 1) / levels;
2253         level_shift = entries_shift + 3;
2254         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2255
2256         /* Allocate TCE table */
2257         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2258                         levels, tce_table_size, &offset);
2259
2260         /* addr==NULL means that the first level allocation failed */
2261         if (!addr)
2262                 return -ENOMEM;
2263
2264         /*
2265          * First level was allocated but some lower level failed as
2266          * we did not allocate as much as we wanted,
2267          * release partially allocated table.
2268          */
2269         if (offset < tce_table_size) {
2270                 pnv_pci_ioda2_table_do_free_pages(addr,
2271                                 1ULL << (level_shift - 3), levels - 1);
2272                 return -ENOMEM;
2273         }
2274
2275         /* Setup linux iommu table */
2276         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2277                         page_shift);
2278         tbl->it_level_size = 1ULL << (level_shift - 3);
2279         tbl->it_indirect_levels = levels - 1;
2280         tbl->it_allocated_size = offset;
2281
2282         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2283                         window_size, tce_table_size, bus_offset);
2284
2285         return 0;
2286 }
2287
2288 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2289                 unsigned long size, unsigned level)
2290 {
2291         const unsigned long addr_ul = (unsigned long) addr &
2292                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2293
2294         if (level) {
2295                 long i;
2296                 u64 *tmp = (u64 *) addr_ul;
2297
2298                 for (i = 0; i < size; ++i) {
2299                         unsigned long hpa = be64_to_cpu(tmp[i]);
2300
2301                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2302                                 continue;
2303
2304                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2305                                         level - 1);
2306                 }
2307         }
2308
2309         free_pages(addr_ul, get_order(size << 3));
2310 }
2311
2312 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2313 {
2314         const unsigned long size = tbl->it_indirect_levels ?
2315                         tbl->it_level_size : tbl->it_size;
2316
2317         if (!tbl->it_size)
2318                 return;
2319
2320         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2321                         tbl->it_indirect_levels);
2322 }
2323
2324 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2325                                        struct pnv_ioda_pe *pe)
2326 {
2327         int64_t rc;
2328
2329         /* We shouldn't already have a 32-bit DMA associated */
2330         if (WARN_ON(pe->tce32_seg >= 0))
2331                 return;
2332
2333         /* TVE #1 is selected by PCI address bit 59 */
2334         pe->tce_bypass_base = 1ull << 59;
2335
2336         iommu_register_group(&pe->table_group, phb->hose->global_number,
2337                         pe->pe_number);
2338
2339         /* The PE will reserve all possible 32-bits space */
2340         pe->tce32_seg = 0;
2341         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2342                 phb->ioda.m32_pci_base);
2343
2344         /* Setup linux iommu table */
2345         pe->table_group.tce32_start = 0;
2346         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2347         pe->table_group.max_dynamic_windows_supported =
2348                         IOMMU_TABLE_GROUP_MAX_TABLES;
2349         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2350         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2351 #ifdef CONFIG_IOMMU_API
2352         pe->table_group.ops = &pnv_pci_ioda2_ops;
2353 #endif
2354
2355         rc = pnv_pci_ioda2_setup_default_config(pe);
2356         if (rc) {
2357                 if (pe->tce32_seg >= 0)
2358                         pe->tce32_seg = -1;
2359                 return;
2360         }
2361
2362         if (pe->flags & PNV_IODA_PE_DEV)
2363                 iommu_add_device(&pe->pdev->dev);
2364         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2365                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2366 }
2367
2368 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
2369 {
2370         struct pci_controller *hose = phb->hose;
2371         unsigned int residual, remaining, segs, tw, base;
2372         struct pnv_ioda_pe *pe;
2373
2374         /* If we have more PE# than segments available, hand out one
2375          * per PE until we run out and let the rest fail. If not,
2376          * then we assign at least one segment per PE, plus more based
2377          * on the amount of devices under that PE
2378          */
2379         if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
2380                 residual = 0;
2381         else
2382                 residual = phb->ioda.tce32_count -
2383                         phb->ioda.dma_pe_count;
2384
2385         pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
2386                 hose->global_number, phb->ioda.tce32_count);
2387         pr_info("PCI: %d PE# for a total weight of %d\n",
2388                 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
2389
2390         pnv_pci_ioda_setup_opal_tce_kill(phb);
2391
2392         /* Walk our PE list and configure their DMA segments, hand them
2393          * out one base segment plus any residual segments based on
2394          * weight
2395          */
2396         remaining = phb->ioda.tce32_count;
2397         tw = phb->ioda.dma_weight;
2398         base = 0;
2399         list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
2400                 if (!pe->dma_weight)
2401                         continue;
2402                 if (!remaining) {
2403                         pe_warn(pe, "No DMA32 resources available\n");
2404                         continue;
2405                 }
2406                 segs = 1;
2407                 if (residual) {
2408                         segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
2409                         if (segs > remaining)
2410                                 segs = remaining;
2411                 }
2412
2413                 /*
2414                  * For IODA2 compliant PHB3, we needn't care about the weight.
2415                  * The all available 32-bits DMA space will be assigned to
2416                  * the specific PE.
2417                  */
2418                 if (phb->type == PNV_PHB_IODA1) {
2419                         pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
2420                                 pe->dma_weight, segs);
2421                         pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
2422                 } else {
2423                         pe_info(pe, "Assign DMA32 space\n");
2424                         segs = 0;
2425                         pnv_pci_ioda2_setup_dma_pe(phb, pe);
2426                 }
2427
2428                 remaining -= segs;
2429                 base += segs;
2430         }
2431 }
2432
2433 #ifdef CONFIG_PCI_MSI
2434 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2435 {
2436         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2437         struct irq_chip *chip = irq_data_get_irq_chip(d);
2438         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2439                                            ioda.irq_chip);
2440         int64_t rc;
2441
2442         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2443         WARN_ON_ONCE(rc);
2444
2445         icp_native_eoi(d);
2446 }
2447
2448
2449 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2450 {
2451         struct irq_data *idata;
2452         struct irq_chip *ichip;
2453
2454         if (phb->type != PNV_PHB_IODA2)
2455                 return;
2456
2457         if (!phb->ioda.irq_chip_init) {
2458                 /*
2459                  * First time we setup an MSI IRQ, we need to setup the
2460                  * corresponding IRQ chip to route correctly.
2461                  */
2462                 idata = irq_get_irq_data(virq);
2463                 ichip = irq_data_get_irq_chip(idata);
2464                 phb->ioda.irq_chip_init = 1;
2465                 phb->ioda.irq_chip = *ichip;
2466                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2467         }
2468         irq_set_chip(virq, &phb->ioda.irq_chip);
2469 }
2470
2471 #ifdef CONFIG_CXL_BASE
2472
2473 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2474 {
2475         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2476
2477         return of_node_get(hose->dn);
2478 }
2479 EXPORT_SYMBOL(pnv_pci_get_phb_node);
2480
2481 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2482 {
2483         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2484         struct pnv_phb *phb = hose->private_data;
2485         struct pnv_ioda_pe *pe;
2486         int rc;
2487
2488         pe = pnv_ioda_get_pe(dev);
2489         if (!pe)
2490                 return -ENODEV;
2491
2492         pe_info(pe, "Switching PHB to CXL\n");
2493
2494         rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2495         if (rc)
2496                 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2497
2498         return rc;
2499 }
2500 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2501
2502 /* Find PHB for cxl dev and allocate MSI hwirqs?
2503  * Returns the absolute hardware IRQ number
2504  */
2505 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2506 {
2507         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2508         struct pnv_phb *phb = hose->private_data;
2509         int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2510
2511         if (hwirq < 0) {
2512                 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2513                 return -ENOSPC;
2514         }
2515
2516         return phb->msi_base + hwirq;
2517 }
2518 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2519
2520 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2521 {
2522         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2523         struct pnv_phb *phb = hose->private_data;
2524
2525         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2526 }
2527 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2528
2529 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2530                                   struct pci_dev *dev)
2531 {
2532         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2533         struct pnv_phb *phb = hose->private_data;
2534         int i, hwirq;
2535
2536         for (i = 1; i < CXL_IRQ_RANGES; i++) {
2537                 if (!irqs->range[i])
2538                         continue;
2539                 pr_devel("cxl release irq range 0x%x: offset: 0x%lx  limit: %ld\n",
2540                          i, irqs->offset[i],
2541                          irqs->range[i]);
2542                 hwirq = irqs->offset[i] - phb->msi_base;
2543                 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2544                                        irqs->range[i]);
2545         }
2546 }
2547 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2548
2549 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2550                                struct pci_dev *dev, int num)
2551 {
2552         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2553         struct pnv_phb *phb = hose->private_data;
2554         int i, hwirq, try;
2555
2556         memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2557
2558         /* 0 is reserved for the multiplexed PSL DSI interrupt */
2559         for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2560                 try = num;
2561                 while (try) {
2562                         hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2563                         if (hwirq >= 0)
2564                                 break;
2565                         try /= 2;
2566                 }
2567                 if (!try)
2568                         goto fail;
2569
2570                 irqs->offset[i] = phb->msi_base + hwirq;
2571                 irqs->range[i] = try;
2572                 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx  limit: %li\n",
2573                          i, irqs->offset[i], irqs->range[i]);
2574                 num -= try;
2575         }
2576         if (num)
2577                 goto fail;
2578
2579         return 0;
2580 fail:
2581         pnv_cxl_release_hwirq_ranges(irqs, dev);
2582         return -ENOSPC;
2583 }
2584 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2585
2586 int pnv_cxl_get_irq_count(struct pci_dev *dev)
2587 {
2588         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2589         struct pnv_phb *phb = hose->private_data;
2590
2591         return phb->msi_bmp.irq_count;
2592 }
2593 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2594
2595 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2596                            unsigned int virq)
2597 {
2598         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2599         struct pnv_phb *phb = hose->private_data;
2600         unsigned int xive_num = hwirq - phb->msi_base;
2601         struct pnv_ioda_pe *pe;
2602         int rc;
2603
2604         if (!(pe = pnv_ioda_get_pe(dev)))
2605                 return -ENODEV;
2606
2607         /* Assign XIVE to PE */
2608         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2609         if (rc) {
2610                 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2611                         "hwirq 0x%x XIVE 0x%x PE\n",
2612                         pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2613                 return -EIO;
2614         }
2615         set_msi_irq_chip(phb, virq);
2616
2617         return 0;
2618 }
2619 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2620 #endif
2621
2622 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2623                                   unsigned int hwirq, unsigned int virq,
2624                                   unsigned int is_64, struct msi_msg *msg)
2625 {
2626         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2627         unsigned int xive_num = hwirq - phb->msi_base;
2628         __be32 data;
2629         int rc;
2630
2631         /* No PE assigned ? bail out ... no MSI for you ! */
2632         if (pe == NULL)
2633                 return -ENXIO;
2634
2635         /* Check if we have an MVE */
2636         if (pe->mve_number < 0)
2637                 return -ENXIO;
2638
2639         /* Force 32-bit MSI on some broken devices */
2640         if (dev->no_64bit_msi)
2641                 is_64 = 0;
2642
2643         /* Assign XIVE to PE */
2644         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2645         if (rc) {
2646                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2647                         pci_name(dev), rc, xive_num);
2648                 return -EIO;
2649         }
2650
2651         if (is_64) {
2652                 __be64 addr64;
2653
2654                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2655                                      &addr64, &data);
2656                 if (rc) {
2657                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2658                                 pci_name(dev), rc);
2659                         return -EIO;
2660                 }
2661                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2662                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2663         } else {
2664                 __be32 addr32;
2665
2666                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2667                                      &addr32, &data);
2668                 if (rc) {
2669                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2670                                 pci_name(dev), rc);
2671                         return -EIO;
2672                 }
2673                 msg->address_hi = 0;
2674                 msg->address_lo = be32_to_cpu(addr32);
2675         }
2676         msg->data = be32_to_cpu(data);
2677
2678         set_msi_irq_chip(phb, virq);
2679
2680         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2681                  " address=%x_%08x data=%x PE# %d\n",
2682                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2683                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2684
2685         return 0;
2686 }
2687
2688 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2689 {
2690         unsigned int count;
2691         const __be32 *prop = of_get_property(phb->hose->dn,
2692                                              "ibm,opal-msi-ranges", NULL);
2693         if (!prop) {
2694                 /* BML Fallback */
2695                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2696         }
2697         if (!prop)
2698                 return;
2699
2700         phb->msi_base = be32_to_cpup(prop);
2701         count = be32_to_cpup(prop + 1);
2702         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2703                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2704                        phb->hose->global_number);
2705                 return;
2706         }
2707
2708         phb->msi_setup = pnv_pci_ioda_msi_setup;
2709         phb->msi32_support = 1;
2710         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2711                 count, phb->msi_base);
2712 }
2713 #else
2714 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2715 #endif /* CONFIG_PCI_MSI */
2716
2717 #ifdef CONFIG_PCI_IOV
2718 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2719 {
2720         struct pci_controller *hose;
2721         struct pnv_phb *phb;
2722         struct resource *res;
2723         int i;
2724         resource_size_t size;
2725         struct pci_dn *pdn;
2726         int mul, total_vfs;
2727
2728         if (!pdev->is_physfn || pdev->is_added)
2729                 return;
2730
2731         hose = pci_bus_to_host(pdev->bus);
2732         phb = hose->private_data;
2733
2734         pdn = pci_get_pdn(pdev);
2735         pdn->vfs_expanded = 0;
2736
2737         total_vfs = pci_sriov_get_totalvfs(pdev);
2738         pdn->m64_per_iov = 1;
2739         mul = phb->ioda.total_pe;
2740
2741         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2742                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2743                 if (!res->flags || res->parent)
2744                         continue;
2745                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2746                         dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n",
2747                                  i, res);
2748                         continue;
2749                 }
2750
2751                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2752
2753                 /* bigger than 64M */
2754                 if (size > (1 << 26)) {
2755                         dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2756                                  i, res);
2757                         pdn->m64_per_iov = M64_PER_IOV;
2758                         mul = roundup_pow_of_two(total_vfs);
2759                         break;
2760                 }
2761         }
2762
2763         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2764                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2765                 if (!res->flags || res->parent)
2766                         continue;
2767                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2768                         dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n",
2769                                  i, res);
2770                         continue;
2771                 }
2772
2773                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2774                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2775                 res->end = res->start + size * mul - 1;
2776                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2777                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2778                          i, res, mul);
2779         }
2780         pdn->vfs_expanded = mul;
2781 }
2782 #endif /* CONFIG_PCI_IOV */
2783
2784 /*
2785  * This function is supposed to be called on basis of PE from top
2786  * to bottom style. So the the I/O or MMIO segment assigned to
2787  * parent PE could be overrided by its child PEs if necessary.
2788  */
2789 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
2790                                   struct pnv_ioda_pe *pe)
2791 {
2792         struct pnv_phb *phb = hose->private_data;
2793         struct pci_bus_region region;
2794         struct resource *res;
2795         int i, index;
2796         int rc;
2797
2798         /*
2799          * NOTE: We only care PCI bus based PE for now. For PCI
2800          * device based PE, for example SRIOV sensitive VF should
2801          * be figured out later.
2802          */
2803         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2804
2805         pci_bus_for_each_resource(pe->pbus, res, i) {
2806                 if (!res || !res->flags ||
2807                     res->start > res->end)
2808                         continue;
2809
2810                 if (res->flags & IORESOURCE_IO) {
2811                         region.start = res->start - phb->ioda.io_pci_base;
2812                         region.end   = res->end - phb->ioda.io_pci_base;
2813                         index = region.start / phb->ioda.io_segsize;
2814
2815                         while (index < phb->ioda.total_pe &&
2816                                region.start <= region.end) {
2817                                 phb->ioda.io_segmap[index] = pe->pe_number;
2818                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2819                                         pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2820                                 if (rc != OPAL_SUCCESS) {
2821                                         pr_err("%s: OPAL error %d when mapping IO "
2822                                                "segment #%d to PE#%d\n",
2823                                                __func__, rc, index, pe->pe_number);
2824                                         break;
2825                                 }
2826
2827                                 region.start += phb->ioda.io_segsize;
2828                                 index++;
2829                         }
2830                 } else if ((res->flags & IORESOURCE_MEM) &&
2831                            !pnv_pci_is_mem_pref_64(res->flags)) {
2832                         region.start = res->start -
2833                                        hose->mem_offset[0] -
2834                                        phb->ioda.m32_pci_base;
2835                         region.end   = res->end -
2836                                        hose->mem_offset[0] -
2837                                        phb->ioda.m32_pci_base;
2838                         index = region.start / phb->ioda.m32_segsize;
2839
2840                         while (index < phb->ioda.total_pe &&
2841                                region.start <= region.end) {
2842                                 phb->ioda.m32_segmap[index] = pe->pe_number;
2843                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2844                                         pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2845                                 if (rc != OPAL_SUCCESS) {
2846                                         pr_err("%s: OPAL error %d when mapping M32 "
2847                                                "segment#%d to PE#%d",
2848                                                __func__, rc, index, pe->pe_number);
2849                                         break;
2850                                 }
2851
2852                                 region.start += phb->ioda.m32_segsize;
2853                                 index++;
2854                         }
2855                 }
2856         }
2857 }
2858
2859 static void pnv_pci_ioda_setup_seg(void)
2860 {
2861         struct pci_controller *tmp, *hose;
2862         struct pnv_phb *phb;
2863         struct pnv_ioda_pe *pe;
2864
2865         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2866                 phb = hose->private_data;
2867                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2868                         pnv_ioda_setup_pe_seg(hose, pe);
2869                 }
2870         }
2871 }
2872
2873 static void pnv_pci_ioda_setup_DMA(void)
2874 {
2875         struct pci_controller *hose, *tmp;
2876         struct pnv_phb *phb;
2877
2878         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2879                 pnv_ioda_setup_dma(hose->private_data);
2880
2881                 /* Mark the PHB initialization done */
2882                 phb = hose->private_data;
2883                 phb->initialized = 1;
2884         }
2885 }
2886
2887 static void pnv_pci_ioda_create_dbgfs(void)
2888 {
2889 #ifdef CONFIG_DEBUG_FS
2890         struct pci_controller *hose, *tmp;
2891         struct pnv_phb *phb;
2892         char name[16];
2893
2894         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2895                 phb = hose->private_data;
2896
2897                 sprintf(name, "PCI%04x", hose->global_number);
2898                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
2899                 if (!phb->dbgfs)
2900                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
2901                                 __func__, hose->global_number);
2902         }
2903 #endif /* CONFIG_DEBUG_FS */
2904 }
2905
2906 static void pnv_pci_ioda_fixup(void)
2907 {
2908         pnv_pci_ioda_setup_PEs();
2909         pnv_pci_ioda_setup_seg();
2910         pnv_pci_ioda_setup_DMA();
2911
2912         pnv_pci_ioda_create_dbgfs();
2913
2914 #ifdef CONFIG_EEH
2915         eeh_init();
2916         eeh_addr_cache_build();
2917 #endif
2918 }
2919
2920 /*
2921  * Returns the alignment for I/O or memory windows for P2P
2922  * bridges. That actually depends on how PEs are segmented.
2923  * For now, we return I/O or M32 segment size for PE sensitive
2924  * P2P bridges. Otherwise, the default values (4KiB for I/O,
2925  * 1MiB for memory) will be returned.
2926  *
2927  * The current PCI bus might be put into one PE, which was
2928  * create against the parent PCI bridge. For that case, we
2929  * needn't enlarge the alignment so that we can save some
2930  * resources.
2931  */
2932 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
2933                                                 unsigned long type)
2934 {
2935         struct pci_dev *bridge;
2936         struct pci_controller *hose = pci_bus_to_host(bus);
2937         struct pnv_phb *phb = hose->private_data;
2938         int num_pci_bridges = 0;
2939
2940         bridge = bus->self;
2941         while (bridge) {
2942                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
2943                         num_pci_bridges++;
2944                         if (num_pci_bridges >= 2)
2945                                 return 1;
2946                 }
2947
2948                 bridge = bridge->bus->self;
2949         }
2950
2951         /* We fail back to M32 if M64 isn't supported */
2952         if (phb->ioda.m64_segsize &&
2953             pnv_pci_is_mem_pref_64(type))
2954                 return phb->ioda.m64_segsize;
2955         if (type & IORESOURCE_MEM)
2956                 return phb->ioda.m32_segsize;
2957
2958         return phb->ioda.io_segsize;
2959 }
2960
2961 #ifdef CONFIG_PCI_IOV
2962 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
2963                                                       int resno)
2964 {
2965         struct pci_dn *pdn = pci_get_pdn(pdev);
2966         resource_size_t align, iov_align;
2967
2968         iov_align = resource_size(&pdev->resource[resno]);
2969         if (iov_align)
2970                 return iov_align;
2971
2972         align = pci_iov_resource_size(pdev, resno);
2973         if (pdn->vfs_expanded)
2974                 return pdn->vfs_expanded * align;
2975
2976         return align;
2977 }
2978 #endif /* CONFIG_PCI_IOV */
2979
2980 /* Prevent enabling devices for which we couldn't properly
2981  * assign a PE
2982  */
2983 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
2984 {
2985         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2986         struct pnv_phb *phb = hose->private_data;
2987         struct pci_dn *pdn;
2988
2989         /* The function is probably called while the PEs have
2990          * not be created yet. For example, resource reassignment
2991          * during PCI probe period. We just skip the check if
2992          * PEs isn't ready.
2993          */
2994         if (!phb->initialized)
2995                 return true;
2996
2997         pdn = pci_get_pdn(dev);
2998         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2999                 return false;
3000
3001         return true;
3002 }
3003
3004 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
3005                                u32 devfn)
3006 {
3007         return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
3008 }
3009
3010 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3011 {
3012         struct pnv_phb *phb = hose->private_data;
3013
3014         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3015                        OPAL_ASSERT_RESET);
3016 }
3017
3018 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3019        .dma_dev_setup = pnv_pci_dma_dev_setup,
3020 #ifdef CONFIG_PCI_MSI
3021        .setup_msi_irqs = pnv_setup_msi_irqs,
3022        .teardown_msi_irqs = pnv_teardown_msi_irqs,
3023 #endif
3024        .enable_device_hook = pnv_pci_enable_device_hook,
3025        .window_alignment = pnv_pci_window_alignment,
3026        .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3027        .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3028        .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3029        .shutdown = pnv_pci_ioda_shutdown,
3030 };
3031
3032 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3033                                          u64 hub_id, int ioda_type)
3034 {
3035         struct pci_controller *hose;
3036         struct pnv_phb *phb;
3037         unsigned long size, m32map_off, pemap_off, iomap_off = 0;
3038         const __be64 *prop64;
3039         const __be32 *prop32;
3040         int len;
3041         u64 phb_id;
3042         void *aux;
3043         long rc;
3044
3045         pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
3046
3047         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3048         if (!prop64) {
3049                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3050                 return;
3051         }
3052         phb_id = be64_to_cpup(prop64);
3053         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3054
3055         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3056
3057         /* Allocate PCI controller */
3058         phb->hose = hose = pcibios_alloc_controller(np);
3059         if (!phb->hose) {
3060                 pr_err("  Can't allocate PCI controller for %s\n",
3061                        np->full_name);
3062                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3063                 return;
3064         }
3065
3066         spin_lock_init(&phb->lock);
3067         prop32 = of_get_property(np, "bus-range", &len);
3068         if (prop32 && len == 8) {
3069                 hose->first_busno = be32_to_cpu(prop32[0]);
3070                 hose->last_busno = be32_to_cpu(prop32[1]);
3071         } else {
3072                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3073                 hose->first_busno = 0;
3074                 hose->last_busno = 0xff;
3075         }
3076         hose->private_data = phb;
3077         phb->hub_id = hub_id;
3078         phb->opal_id = phb_id;
3079         phb->type = ioda_type;
3080         mutex_init(&phb->ioda.pe_alloc_mutex);
3081
3082         /* Detect specific models for error handling */
3083         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3084                 phb->model = PNV_PHB_MODEL_P7IOC;
3085         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3086                 phb->model = PNV_PHB_MODEL_PHB3;
3087         else
3088                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3089
3090         /* Parse 32-bit and IO ranges (if any) */
3091         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3092
3093         /* Get registers */
3094         phb->regs = of_iomap(np, 0);
3095         if (phb->regs == NULL)
3096                 pr_err("  Failed to map registers !\n");
3097
3098         /* Initialize more IODA stuff */
3099         phb->ioda.total_pe = 1;
3100         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3101         if (prop32)
3102                 phb->ioda.total_pe = be32_to_cpup(prop32);
3103         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3104         if (prop32)
3105                 phb->ioda.reserved_pe = be32_to_cpup(prop32);
3106
3107         /* Parse 64-bit MMIO range */
3108         pnv_ioda_parse_m64_window(phb);
3109
3110         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3111         /* FW Has already off top 64k of M32 space (MSI space) */
3112         phb->ioda.m32_size += 0x10000;
3113
3114         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
3115         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3116         phb->ioda.io_size = hose->pci_io_size;
3117         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
3118         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3119
3120         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3121         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
3122         m32map_off = size;
3123         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
3124         if (phb->type == PNV_PHB_IODA1) {
3125                 iomap_off = size;
3126                 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
3127         }
3128         pemap_off = size;
3129         size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
3130         aux = memblock_virt_alloc(size, 0);
3131         phb->ioda.pe_alloc = aux;
3132         phb->ioda.m32_segmap = aux + m32map_off;
3133         if (phb->type == PNV_PHB_IODA1)
3134                 phb->ioda.io_segmap = aux + iomap_off;
3135         phb->ioda.pe_array = aux + pemap_off;
3136         set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
3137
3138         INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
3139         INIT_LIST_HEAD(&phb->ioda.pe_list);
3140         mutex_init(&phb->ioda.pe_list_mutex);
3141
3142         /* Calculate how many 32-bit TCE segments we have */
3143         phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
3144
3145 #if 0 /* We should really do that ... */
3146         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3147                                          window_type,
3148                                          window_num,
3149                                          starting_real_address,
3150                                          starting_pci_address,
3151                                          segment_size);
3152 #endif
3153
3154         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3155                 phb->ioda.total_pe, phb->ioda.reserved_pe,
3156                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3157         if (phb->ioda.m64_size)
3158                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3159                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3160         if (phb->ioda.io_size)
3161                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3162                         phb->ioda.io_size, phb->ioda.io_segsize);
3163
3164
3165         phb->hose->ops = &pnv_pci_ops;
3166         phb->get_pe_state = pnv_ioda_get_pe_state;
3167         phb->freeze_pe = pnv_ioda_freeze_pe;
3168         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3169
3170         /* Setup RID -> PE mapping function */
3171         phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
3172
3173         /* Setup TCEs */
3174         phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3175
3176         /* Setup MSI support */
3177         pnv_pci_init_ioda_msis(phb);
3178
3179         /*
3180          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3181          * to let the PCI core do resource assignment. It's supposed
3182          * that the PCI core will do correct I/O and MMIO alignment
3183          * for the P2P bridge bars so that each PCI bus (excluding
3184          * the child P2P bridges) can form individual PE.
3185          */
3186         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3187         hose->controller_ops = pnv_pci_ioda_controller_ops;
3188
3189 #ifdef CONFIG_PCI_IOV
3190         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3191         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3192 #endif
3193
3194         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3195
3196         /* Reset IODA tables to a clean state */
3197         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3198         if (rc)
3199                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3200
3201         /* If we're running in kdump kerenl, the previous kerenl never
3202          * shutdown PCI devices correctly. We already got IODA table
3203          * cleaned out. So we have to issue PHB reset to stop all PCI
3204          * transactions from previous kerenl.
3205          */
3206         if (is_kdump_kernel()) {
3207                 pr_info("  Issue PHB reset ...\n");
3208                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3209                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3210         }
3211
3212         /* Remove M64 resource if we can't configure it successfully */
3213         if (!phb->init_m64 || phb->init_m64(phb))
3214                 hose->mem_resources[1].flags = 0;
3215 }
3216
3217 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3218 {
3219         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3220 }
3221
3222 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3223 {
3224         struct device_node *phbn;
3225         const __be64 *prop64;
3226         u64 hub_id;
3227
3228         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3229
3230         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3231         if (!prop64) {
3232                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3233                 return;
3234         }
3235         hub_id = be64_to_cpup(prop64);
3236         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3237
3238         /* Count child PHBs */
3239         for_each_child_of_node(np, phbn) {
3240                 /* Look for IODA1 PHBs */
3241                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3242                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3243         }
3244 }